CN220962407U

CN220962407U - Protocol converter board card

Info

Publication number: CN220962407U
Application number: CN202323078437.0U
Authority: CN
Inventors: 王红霞; 刘鸿瑾; 李宾; 王小波; 李超; 宋佳伟; 张雷浩; 马远航; 赵倩; 高景泉
Original assignee: Beijing Sunwise Space Technology Ltd
Current assignee: Beijing Sunwise Space Technology Ltd
Priority date: 2023-11-15
Filing date: 2023-11-15
Publication date: 2024-05-14
Anticipated expiration: 2033-11-15

Abstract

When the protocol converter board card is applied, the protocol converter board card is connected between a remote monitoring PC and a target FPGA, the board card comprises an SoC chip and a JTAG interface which are arranged on a circuit board, the SoC chip is integrated with two dual-core Coretex-A9 processors, the SoC chip is used for being connected with the remote monitoring PC through a UART pin to perform low-speed information interaction, and is connected with a PHY chip arranged on the circuit board through an Ethernet pin to be connected with the remote monitoring PC through a first network port connected with the PHY chip to perform high-speed information interaction, the SoC chip is connected with the JTAG interface, and the JTAG interface is used for being connected with the target FPGA. And universal interfaces such as a domestic SoC chip, a JTAG interface, a CAN interface and the like are integrated on the board card, so that data protocol conversion and support for remote debugging are realized, the hardware structure is simplified, and the localization CAN be realized, and the cost is low.

Description

Protocol converter board card

Technical Field

The application belongs to the technical field of FPGA debugging, and particularly relates to a protocol converter board card.

Background

The FPGA is analyzed and debugged in real time, and is an important means for verifying the correctness of hardware logic. In order to facilitate the collaborative development of multiple persons, in the prior art, a data packet sent by an upper computer through an Ethernet network is often received through a CPU (central processing unit) outside an FPGA, such as an arm+fpga architecture or a dsp+fpga architecture, and the data packet is analyzed and a JTAG interface is simulated to update and debug the FPGA firmware, as shown in fig. 1, the system structure of the scheme is complex, and the problems of low data exchange performance and the like exist; on the other hand, with the continuous increase of the requirements of the application fields, the development of solutions which are localization, microminiaturization, low cost and autonomous and controllable are also urgent.

Disclosure of utility model

In order to solve the defects in the prior art, the application provides a protocol converter board card, and a SoC chip, a JTAG interface and various general interfaces are integrated on the board card, so that data protocol conversion and support for remote debugging are realized, the hardware structure is simplified, and localization autonomous and controllable can be realized.

In order to achieve the above object, the present utility model adopts the following technique:

When the protocol converter board card is applied, the protocol converter board card is connected between a remote monitoring PC and a target FPGA, the board card comprises an SoC chip and a JTAG interface, the SoC chip is integrated with two dual-core Coretex-A9 processors, the SoC chip is used for being connected with the remote monitoring PC through a UART pin to perform low-speed information interaction, and is connected with a PHY chip arranged on the circuit board through an Ethernet pin to be connected with the remote monitoring PC through a first network port connected with the PHY chip to perform high-speed information interaction, and the JTAG interface is used for being connected with the target FPGA.

Further, another PHY chip and a second network port are further arranged on the board card, another Ethernet pin of the SoC chip is connected with the another PHY chip, and the another PHY chip is connected with the second network port.

Further, the board card is also provided with a CAN interface, and CAN pins of the SoC chip are connected with the CAN interface.

Furthermore, the board card is also provided with a bit interface, and the GPIO pin of the SoC chip is connected with the bit interface.

Furthermore, the board card is also provided with an SPI interface, and an SPI pin of the SoC chip is connected with the SPI interface.

Furthermore, the board card is also provided with an I2C interface, and an I2C pin of the SoC chip is connected with the I2C interface.

Furthermore, the board card is also provided with a UART interface, and the other UART pin of the SoC chip is connected with the UART interface.

Further, the SoC chip adopts a domestic XYM2019 chip.

The utility model has the beneficial effects that:

The integrated SoC chip replaces the architecture of DSP+FPGA or ARM+FPGA in the prior art, so that the data protocol conversion and the remote debugging support are realized, the complexity of the system structure is reduced, and the hardware structure is simplified; and the used SoC chip adopts an autonomous controllable domestic chip, so that the cost is low and the cost is autonomous and controllable.

Drawings

Fig. 1 is a prior art debug scheme.

Fig. 2 is a board hardware configuration diagram of an embodiment of the present application.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present utility model more apparent, the following detailed description of the embodiments of the present utility model will be given with reference to the accompanying drawings, but the described embodiments of the present utility model are some, but not all embodiments of the present utility model.

The embodiment of the application provides a protocol converter board card which is connected between a remote monitoring PC and a target FPGA during application and is used for realizing data protocol conversion and supporting remote debugging.

The protocol converter board card of this example only adopts a chip, replaces the function of current ARM+FPGA or DSP+FPGA, and specifically, as shown in FIG. 2, the protocol converter board card of this example includes SoC chip, JTAG interface, etc. arranged on the circuit board of the circuit board.

Wherein, the SoC chip is integrated with two dual-core Coretex-A9 processors and is embedded with SRAM; for example, a domestic autonomous controllable microprocessor chip XYM2019 is adopted, which supports the IEEE Std 1149.1-1990 JTAG (Joint Test Action Group ) standard. The SoC chip is used for being connected with the remote monitoring PC through a UART pin so as to perform low-speed information interaction; and is connected with the remote monitoring PC through an Ethernet pin to perform high-speed information interaction, specifically, as shown in fig. 2, the Ethernet1 pin is connected to the network through a PHY chip and a first network port in sequence to connect with the remote monitoring PC. The SoC chip is connected with a JTAG interface, and the JTAG interface is used for connecting with a target FPGA.

When the method is applied, EDA tools of the Xilinx FPGA, such as Vivado and ISE, can be operated from a remote monitoring PC end, the data stream bit file to be downloaded is downloaded to the protocol converter board card through the first network port, the SoC chip is used for caching, and after reading, the data stream bit file can be downloaded to the target FPGA through the JTAG interface, so that the remote downloading or debugging of the target FPGA is realized.

Specifically, an off-chip memory RAM may be provided on the board card, which is connected to the SoC core. When the bit file of the data stream is smaller, caching through an embedded SRAM; when the data stream bit file is larger, the data stream bit file is cached through an external storage RAM.

Specifically, as a specific implementation form of the board card of this example, as shown in fig. 2, another PHY chip, a second network port, a CAN interface, a bit interface, an SPI interface, an I2C interface, and a UART interface are further provided on the board card, so as to provide more universal interface functions, and improve the practicability of the board card.

The other Ethernet pin of the SoC chip is connected to another PHY chip, and the other PHY chip is connected to the second network port, as shown in fig. 2, so as to provide a network interface communication manner for other purposes. The CAN pin of the SoC chip is connected with the CAN interface, so that a bus transmission interface is conveniently provided. The GPIO pin of the SoC chip is connected with the bit interface and used for providing a control bit operation interface. The SPI pin of the SoC chip is connected with the SPI interface and is used for providing a serial communication interface. The I2C pin of the SoC chip is connected with the I2C interface and used for providing a serial communication bus interface. The other UART pin of the SoC chip is connected with a UART interface and is used for providing a serial communication interface of a UART protocol.

The above description is only of the preferred embodiments of the present application and is not intended to limit the application, and it will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit and scope of the application.

Claims

1. The utility model provides a protocol converter integrated circuit board, when using, connect in between remote monitoring PC and the target FPGA, its characterized in that, the integrated circuit board of integrated circuit board includes SoC chip and JTAG interface of locating on the circuit board, soC chip is used for being connected with remote monitoring PC through a UART pin in order to carry out low-speed information interaction to be connected with the PHY chip of locating the circuit board through an Ethernet pin, in order to be connected with remote monitoring PC through the first net gape of being connected with this PHY chip in order to carry out high-speed information interaction, soC chip connects JTAG interface, JTAG interface is used for connecting the target FPGA.

2. The protocol converter board of claim 1, wherein the board is further provided with another PHY chip and a second network port, and another Ethernet pin of the SoC chip is connected to the another PHY chip, and the another PHY chip is connected to the second network port.

3. The protocol converter board of claim 1, wherein the board is further provided with a CAN interface, and CAN pins of the SoC chip are connected with the CAN interface.

4. The protocol converter board of claim 1, wherein the board is further provided with a bit interface, and the GPIO pin of the SoC chip is connected to the bit interface.

5. The protocol converter board of claim 1, wherein the board is further provided with an SPI interface, and an SPI pin of the SoC chip is connected to the SPI interface.

6. The protocol converter board of claim 1, wherein the board is further provided with an I2C interface, and an I2C pin of the SoC chip is connected to the I2C interface.

7. The protocol converter board of claim 1, wherein a UART interface is further provided on the board, and another UART pin of the SoC chip is connected to the UART interface.

8. The protocol converter board of claim 1, wherein the SoC chip is a homemade XYM2019 chip.