CN220962081U - Array substrate and display panel - Google Patents

Abstract

The utility model provides an array substrate and a display panel, wherein the array substrate comprises a plurality of grid scanning lines extending along a first direction and data lines extending along a second direction, the grid scanning lines and the data lines are crossed to define a plurality of pixel areas, each pixel area is provided with a sub-pixel, each sub-pixel comprises a first pixel electrode, a second pixel electrode and a plurality of transistors positioned on the same side of the first pixel electrode and the second pixel electrode, the first pixel electrode extends along the first direction, the second pixel electrode and the first pixel electrode are arranged at intervals in the second direction, and each second pixel electrode and each first pixel electrode comprise four display domains, so that each sub-pixel comprises eight display domains, eight-domain display is realized, the viewing angle is improved, and the problem of poor viewing angle of the existing three-grid liquid crystal display panel is further solved.

Description

Array substrate and display panel

Technical Field

The utility model relates to the technical field of display, in particular to an array substrate and a display panel.

Background

With the development of Liquid crystal display (Liquid CRYSTAL DISPLAY, LCD) technology, a Tri-gate (Tri-gate) type Liquid crystal display panel has been developed in the industry in order to reduce the cost of the Liquid crystal display panel. The tri-gate liquid crystal display panel has a plurality of pixel units arranged in rows and columns, and drives one pixel unit by using three adjacent scan lines (scan lines). Each pixel unit is composed of three sub-pixel units with different colors and arranged longitudinally, for example, each pixel unit comprises a red sub-pixel unit, a green sub-pixel unit and a blue sub-pixel unit, and each sub-pixel unit in the same row is electrically connected with one scanning line. In addition, the color of the sub-pixel units in any row is the same, for example, the sub-pixel units arranged in one row are red sub-pixel units, green sub-pixel units or blue sub-pixel units.

The pixel design of the tri-gate lcd panel generally adopts a four-domain (domain) display, however, the four-domain display makes the viewing angle of the tri-gate lcd panel poor.

Disclosure of utility model

The utility model provides an array substrate and a display panel, which are used for relieving the technical problem of poor visual angle of the existing tri-gate type liquid crystal display panel.

In order to solve the problems, the technical scheme provided by the utility model is as follows:

The embodiment of the utility model provides an array substrate, which comprises a plurality of grid scanning lines extending along a first direction and data lines extending along a second direction, wherein the grid scanning lines and the data lines are crossed to define a plurality of pixel areas, each pixel area is provided with a sub-pixel, and each sub-pixel comprises a first pixel electrode, a second pixel electrode and a plurality of transistors positioned on the same side of the first pixel electrode and the second pixel electrode, wherein the first pixel electrode and the second pixel electrode are arranged on the same side of the first pixel electrode and the second pixel electrode respectively, and the data lines are arranged on the first pixel electrode and the second pixel electrode respectively:

the first pixel electrode extends along the first direction;

The second pixel electrode extends along the first direction, the second pixel electrode and the first pixel electrode are arranged at intervals in the second direction, and the second pixel electrode and the first pixel electrode both comprise four display domains; and

The plurality of transistors includes a first transistor electrically connected to the first pixel electrode and a second transistor electrically connected to the second pixel electrode.

In the array substrate provided by the embodiment of the utility model, the plurality of transistors further includes a third transistor, a source electrode of the third transistor is electrically connected with a drain electrode of the second transistor, a drain electrode of the second transistor is also electrically connected with the second pixel electrode, and a source electrode of the second transistor is electrically connected with the data line;

The array substrate further comprises a shared discharging rod, wherein the shared discharging rod and the data line are arranged on the same layer and are electrically connected with the drain electrode of the third transistor.

In the array substrate provided by the embodiment of the utility model, the shared discharging rod comprises a first sub discharging rod extending along the first direction, and the first sub discharging rod is arranged corresponding to the grid scanning line.

In the array substrate provided by the embodiment of the utility model, the first sub-discharging rod is arranged above the grid scanning line, and the width of the first sub-discharging rod in the second direction is smaller than the width of the grid scanning line in the second direction.

In the array substrate provided by the embodiment of the utility model, the shared discharging rod further comprises a second sub discharging rod extending along the second direction, and the second sub discharging rod is connected with the first sub discharging rod;

The first pixel electrode comprises a first main electrode extending along the second direction, the second pixel electrode comprises a second main electrode extending along the second direction, and the second sub-discharging rod is arranged below the first main electrode and the second main electrode.

In the array substrate provided by the embodiment of the utility model, in the second direction, the first trunk electrode and the second trunk electrode are overlapped, the first trunk electrode is located in the middle area of the first pixel electrode, and the second trunk electrode is located in the middle area of the second pixel electrode.

In the array substrate provided by the embodiment of the utility model, the array substrate further comprises a first shading part extending along the second direction, and the first shading part is arranged corresponding to the second sub-discharging rod and is positioned below the second sub-discharging rod.

In the array substrate provided by the embodiment of the utility model, the first shading part and the grid scanning line are arranged on the same layer, and the width of the first shading part in the first direction is larger than that of the second sub-discharging rod in the first direction.

In the array substrate provided by the embodiment of the utility model, the array substrate further comprises a second shading part, wherein the second shading part is arranged corresponding to the data line and is positioned above the data line.

The embodiment of the utility model also provides a display panel, which comprises the array substrate of one of the embodiments.

The beneficial effects of the utility model are as follows: in the array substrate and the display panel provided by the utility model, the array substrate comprises a plurality of gate scanning lines extending along a first direction and data lines extending along a second direction, the gate scanning lines and the data lines are crossed to define a plurality of pixel areas, each pixel area is provided with one sub-pixel, each sub-pixel comprises a first pixel electrode, a second pixel electrode and a plurality of transistors positioned on the same side of the first pixel electrode and the second pixel electrode, the first pixel electrode extends along the first direction, the second pixel electrode extends along the first direction, in addition, in the second direction, the second pixel electrode and the first pixel electrode are arranged at intervals, and each sub-pixel comprises eight display domains, so that eight display domains are displayed, the viewing angle is improved, and the technical problem of poor viewing angle of the existing three-gate liquid crystal display panel is solved.

Drawings

In order to more clearly illustrate the embodiments or the technical solutions in the prior art, the following description will briefly introduce the drawings that are needed in the embodiments or the description of the prior art, it is obvious that the drawings in the following description are only some embodiments of the utility model, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of a subpixel of a related art tri-gate lcd panel.

Fig. 2 is a schematic top view of an array substrate according to an embodiment of the present utility model.

Fig. 3 is a detailed structural diagram of one sub-pixel in fig. 2.

Fig. 4 is a schematic diagram of fig. 3 after the first pixel electrode, the second pixel electrode, and the second light shielding electrode are removed.

FIG. 5 is a schematic cross-sectional view of the structure of FIG. 3 along the directions M-M ', N-N'.

Fig. 6 is a schematic cross-sectional structure of a display panel according to an embodiment of the utility model.

Detailed Description

The following description of the embodiments refers to the accompanying drawings, which illustrate specific embodiments in which the utility model may be practiced. The directional terms mentioned in the present utility model, such as [ upper ], [ lower ], [ front ], [ rear ], [ left ], [ right ], [ inner ], [ outer ], [ side ], etc., are only referring to the directions of the attached drawings. Accordingly, directional terminology is used to describe and understand the utility model and is not limiting of the utility model. In the drawings, like elements are designated by like reference numerals. In the drawings, the thickness of some layers and regions are exaggerated for clarity of understanding and ease of description. I.e., the size and thickness of each component shown in the drawings are arbitrarily shown, but the present utility model is not limited thereto.

Aiming at the problem of poor viewing angle of the tri-gate type liquid crystal display panel in the related art, the inventor of the utility model finds that: referring to fig. 1, fig. 1 is a schematic diagram of one subpixel of a related art tri-gate liquid crystal display panel, each subpixel includes one transistor 500 and one pixel electrode 600, the pixel electrode 600 is divided into four display domains (domains), and the pixel electrodes 600 of the four display domains are controlled by one transistor 500, so that they cannot be complemented in viewing angle, and the viewing angle is poor.

Therefore, the utility model provides an array substrate and a display panel to solve the problem of poor viewing angle.

Referring to fig. 1 to 5, fig. 2 is a schematic top view of an array substrate according to an embodiment of the utility model, fig. 3 is a detailed schematic structure of one sub-pixel in fig. 2, fig. 4 is a schematic diagram of fig. 3 after removing the first pixel electrode, the second pixel electrode, and the second light shielding electrode, and fig. 5 is a schematic cross-sectional structure of fig. 3 along the directions M-M ', N-N'. Referring to fig. 2, the array substrate 100 includes a substrate 10, and a plurality of gate scan lines GL and a plurality of data lines DL arranged on the substrate 10. The plurality of gate scan lines GL extend along a first direction X and are arranged at intervals along a second direction Y. The data lines DL extend along the second direction Y and are arranged at intervals along the first direction X. The first direction X and the second direction Y are different, for example, the first direction X is a row direction, and the second direction Y is a column direction.

The gate scan lines GL and the data lines DL cross to define a plurality of pixel areas PD, and each pixel area PD is provided with one sub-pixel SP, so that the array substrate 100 includes a plurality of sub-pixels SP, and the plurality of sub-pixels SP are arranged on the array substrate 100 in an array manner. Each gate scanning line GL is connected to one row of the sub-pixels SP, and each data line DL is connected to one column of the sub-pixels SP. In the second direction Y, any adjacent three of the sub-pixels SP constitute one pixel P. That is, each pixel P includes three sub-pixels SP sequentially arranged in the second direction Y, and the colors of the three sub-pixels SP sequentially arranged are different, for example, one red sub-pixel R, one green sub-pixel G, and one blue sub-pixel B may be included. The subpixels SP of three different colors of each pixel P are connected to the same data line DL. In the first direction X, the colors of the sub-pixels SP in each row may be the same or different. When the colors of the sub-pixels SP in each row are different, color shift occurring when a two-color-mixture picture is displayed can be improved.

The structure of the array substrate 100 will be specifically described below by taking one sub-pixel SP as an example.

Referring to fig. 3, the sub-pixel SP includes a first pixel electrode 20, a second pixel electrode 30, and a plurality of transistors on the same side of the first pixel electrode 20 and the second pixel electrode 30. The first pixel electrode 20 extends along the first direction X. The second pixel electrode 30 extends along a first direction X, and in the second direction Y, the second pixel electrode 30 is spaced from the first pixel electrode 20, and the second pixel electrode 30 and the first pixel electrode 20 each include four display domains. The materials of the second pixel electrode 30 and the first pixel electrode 20 each include a transparent conductive material such as Indium Tin Oxide (ITO).

The first pixel electrode 20 includes a first backbone electrode 21 extending in a second direction Y and a third backbone electrode 22 extending in the first direction X, and a length of the first backbone electrode 21 is smaller than a length of the third backbone electrode 22. The first and third main electrodes 21 and 22 divide the first pixel electrode 20 into four display domains. The first pixel electrode 20 further includes a plurality of first branch electrodes 23, the first branch electrodes 23 are connected to the first trunk electrode 21 or the third trunk electrode 22, and extend from the first trunk electrode 21 or the third trunk electrode 22 in different directions, and the extending directions of the first branch electrodes 23 in each display domain are the same, and the first branch electrodes 23 in two adjacent display domains are symmetrical with respect to the first trunk electrode 21 or the third trunk electrode 22.

The second pixel electrode 30 includes a second backbone electrode 31 extending in a second direction Y and a fourth backbone electrode 32 extending in the first direction X, and a length of the second backbone electrode 31 is smaller than a length of the fourth backbone electrode 32. The second and fourth main electrodes 31 and 32 divide the second pixel electrode 30 into four display domains such that the sub-pixel SP within each of the pixel regions PD includes eight display domains. The second pixel electrode 30 further includes a plurality of second branch electrodes 33, the second branch electrodes 33 are connected to the second main electrode 31 or the fourth main electrode 32, and extend from the second main electrode 31 or the fourth main electrode 32 in different directions, and the extending directions of the second branch electrodes 33 in each display domain are the same, and the second branch electrodes 33 in two adjacent display domains are symmetrical with respect to the second main electrode 31 or the fourth main electrode 32.

The transistors are located at a side of the first pixel electrode 20 close to the data line DL, and the transistors are also located at a side of the second pixel electrode 30 close to the data line DL, that is, the transistors are located between the data line DL and the first and second pixel electrodes 20 and 30.

The plurality of transistors includes a first transistor T1 and a second transistor T2, the first transistor T1 is electrically connected to the first pixel electrode 20, and the second transistor T2 is electrically connected to the second pixel electrode 30. The first transistor T1 and the second transistor T2 are both thin film transistors. The first transistor T1 is configured to provide a driving voltage to the first pixel electrode 20, the second transistor T2 is configured to provide a driving voltage to the second pixel electrode 30, and the driving voltage provided by the first transistor T1 to the first pixel electrode 20 is different from the driving voltage provided by the second transistor T2 to the second pixel electrode 30. In this way, the brightness difference between the corresponding areas of the first pixel electrode 20 and the second pixel electrode 30 can be adjusted by adjusting the voltage ratio between the first pixel electrode 20 and the second pixel electrode 30, thereby forming complementation in viewing angle and improving viewing angle.

In one embodiment, the area of the first pixel electrode 20 is the same as the area of the second pixel electrode 30, that is, the area ratio of the first pixel electrode 20 in the pixel region PD is the same as the area ratio of the second pixel electrode 30 in the pixel region PD, so as to further improve the viewing angle.

The following proceeds to explain how the first transistor T1 provides a different driving voltage to the first pixel electrode 20 than the second transistor T2 provides to the second pixel electrode 30.

In one embodiment, the plurality of transistors further comprises a third transistor T3, the third transistor T3 being of the same type as the first transistor T1 and/or the second transistor T2. The third transistor T3 is connected in series with the second transistor T2, and is configured to divide the voltage of the second transistor T2, so that the driving voltage of the second transistor T2 supplied to the second pixel electrode 30 is smaller than the driving voltage of the first transistor T1 supplied to the first pixel electrode 20, and further, the voltage of the second pixel electrode 30 is smaller than the voltage of the first pixel electrode 20.

The source S1 of the first transistor T1 is electrically connected to the data line DL, and the drain D1 of the first transistor T1 is electrically connected to the first pixel electrode 20. The source electrode S2 of the second transistor T2 is electrically connected to the data line DL, the drain electrode D2 of the second transistor T2 is electrically connected to the second pixel electrode 30, and the drain electrode D2 of the second transistor T2 is also electrically connected to the source electrode S3 of the third transistor T3. The gate G1 of the first transistor T1, the gate G2 of the second transistor T2, and the gate G3 of the third transistor T3 are all electrically connected to the same gate scanning line GL. Of course, the first transistor T1, the second transistor T2, and the third transistor T3 each further include an active layer (not shown in fig. 3), and the active layer will be described in detail later when a specific film structure of the array substrate 100 is described.

Further, the array substrate 100 further includes a shared discharging rod 40, and the shared discharging rod 40 is electrically connected to the drain D3 of the third transistor T3, so that the third transistor T3 divides the voltage of the second transistor T2. Optionally, the shared discharging rod 40 is arranged in the same layer as the data line DL.

It should be noted that the term "same layer setting" in the present utility model means that, in the preparation process, a film layer formed of the same material is subjected to patterning treatment to obtain at least two different structures, and the at least two different structures are set in the same layer. For example, the shared discharging rod 40 and the data line DL in this embodiment are obtained by patterning the same conductive film layer, and the shared discharging rod 40 and the data line DL are arranged in the same layer.

In one embodiment, the shared discharging bar 40 includes a first sub discharging bar 41 extending along the first direction X, and the first sub discharging bar 41 is disposed corresponding to the gate scan line GL. Specifically, the first sub-discharge bar 41 is disposed above the gate scan line GL, that is, the first sub-discharge bar 41 is located at a side of the gate scan line GL away from the substrate 10. It should be noted that, in the present utility model, the "above" or "below" of one structure refers to a spatial positional relationship using the substrate 10 as a reference plane, for example, the first structure is located above the second structure, which means that the first structure is located on a side of the second structure away from the substrate 10, and the first structure is located below the second structure, which means that the first structure is located on a side of the second structure close to the substrate 10. As such, the first sub-discharge bar 41 being disposed above the gate scan line GL means that the first sub-discharge bar 41 is located at a side of the gate scan line GL away from the substrate 10.

The width of the first sub-discharge bar 41 in the second direction Y is smaller than the width of the gate scan line GL in the second direction Y. More specifically, the front projection of the first sub-discharge rod 41 on the substrate 10 falls within the range of the front projection of the gate scanning line GL on the substrate 10, so that the gate scanning line GL can completely shield the first sub-discharge rod 41 to shield the first sub-discharge rod 41 from light.

In this way, by disposing the first sub-discharging rod 41 above the gate scanning line GL, not only the third transistor T3 may divide the voltage of the second transistor T2, but also the first sub-discharging rod 41 may be prevented from occupying the opening area of the sub-pixel SP, thereby improving the opening ratio of each sub-pixel SP, further improving the penetration ratio, and achieving the purpose of energy saving.

In another embodiment, referring to fig. 3 and 4, the shared discharging rod 40 further includes a second sub discharging rod 42 extending along the second direction Y, the second sub discharging rod 42 is connected to the first sub discharging rod 41, and the second sub discharging rod 42 is disposed in the same layer as the data line DL. Optionally, the second sub-discharging rod 42 is integrally disposed with the first sub-discharging rod 41. The second sub-discharging rods 42 are disposed corresponding to the first main electrode 21 and the second main electrode 31, so as to avoid that the second sub-discharging rods 42 affect the opening area of the sub-pixel SP.

Specifically, the second sub-discharging rod 42 is disposed below the first main electrode 21 and the second main electrode 31, that is, the second sub-discharging rod 42 is located at a side of the first main electrode 21 and the second main electrode 31 close to the substrate 10. The width of the second sub-discharging rod 42 in the first direction X is smaller than or equal to the width of the first main electrode 21 in the first direction X, and is also smaller than or equal to the width of the second main electrode 31 in the first direction X.

Since the second sub-discharge rod 42 is disposed below the first main electrode 21 and the second main electrode 31 and is blocked by the first main electrode 21 and the second main electrode 31, the position of the second sub-discharge rod 42 is schematically shown by a dotted line in fig. 3, and the first pixel electrode 20 and the second pixel electrode 30 above the second sub-discharge rod 42 are removed in fig. 4 to clearly show the position of the second sub-discharge rod 42.

Alternatively, in the second direction Y, the first main electrode 21 and the second main electrode 31 overlap, and the first main electrode 21 is located in a middle region of the first pixel electrode 20, and the first main electrode 21 divides the first pixel electrode 20 into two parts having the same area. The second main electrode 31 is located in the middle area of the second pixel electrode 30, and the second main electrode 31 divides the second pixel electrode 30 into two parts with the same area. In this way, the second sub-discharging rod 42 is disposed corresponding to the middle area of the first pixel electrode 20 and the second pixel electrode 30, and divides the eight display domains formed by the first pixel electrode 20 and the second pixel into two portions with the same area, so as to further optimize the viewing angle. Each section comprises four display domains, four of which are located on one side of the second sub-discharge rod 42 and the other four display domains are located on the other side of the second sub-discharge rod 42.

In one embodiment, the array substrate 100 further includes a first light shielding portion 51 extending along the second direction Y, where the first light shielding portion 51 is disposed corresponding to the second sub-discharge rod 42 and is located below the second sub-discharge rod 42 to shield the second sub-discharge rod 42 from light. It should be noted that, when the array substrate 100 is manufactured by using the 4Msak process, all structures disposed on the same layer as the data line DL include a metal layer and a semiconductor portion located below the metal layer, for example, the first sub-discharging rod 41 and the second sub-discharging rod 42 include a metal layer and a semiconductor portion located below the metal layer, so that the first light shielding portion 51 shields the second sub-discharging rod 42, and thus, light leakage of the semiconductor portion in the second sub-discharging rod 42 can be avoided, as shown in fig. 5.

Alternatively, the first light shielding portion 51 is disposed on the same layer as the gate scan line GL, and the width of the first light shielding portion 51 in the first direction X is greater than the width of the second sub-discharge rod 42 in the first direction X so as to completely shield the second sub-discharge rod 42. The first light shielding portion 51 is disconnected from the gate scan line GL, that is, there is no connection between the first light shielding portion 51 and the gate scan line GL, and the first light shielding portion 51 is insulated from the gate scan line GL.

In one embodiment, the array substrate 100 further includes a second light shielding portion 52, where the second light shielding portion 52 is disposed corresponding to the data line DL and is located above the data line DL to shield the data line DL from light. The second light shielding portion 52 is provided in the same layer as the first pixel electrode 20 and the second pixel electrode 30. Optionally, the width of the second light shielding portion 52 is greater than the width of the data line DL, so that the orthographic projection of the data line DL on the substrate 10 falls completely within the orthographic projection range of the second light shielding portion 52 on the substrate 10, so as to avoid light leakage at the position corresponding to the data line DL.

The specific film structure of the array substrate 100 will be specifically described below by taking the second transistor T2 as an example.

Referring to fig. 5, the array substrate 100 includes a second transistor T2 and a second pixel electrode 30 sequentially stacked on the substrate 10, and the second transistor T2 is electrically connected to the second pixel electrode 30 for supplying a driving voltage to the second pixel electrode 30.

Alternatively, the substrate 10 may be a rigid substrate or a flexible substrate; when the substrate 10 is a rigid substrate, the substrate may include a rigid substrate such as a glass substrate; when the substrate 10 is a flexible substrate, the substrate may include a Polyimide (PI) film, an ultrathin glass film, or the like.

Optionally, a buffer layer 11 may be further disposed between the substrate 10 and the second transistor T2, and the buffer layer 11 may prevent unwanted impurities or contaminants (e.g., moisture, oxygen, etc.) from diffusing from the substrate 10 into devices that may be damaged by these impurities or contaminants, while also providing a planar top surface.

The second transistor T2 includes the gate electrode G2, the active layer AS, the source electrode S2, and the drain electrode D2 sequentially stacked on the buffer layer 11. Of course, the array substrate 100 further includes an insulating layer between the elements of the second transistor T2, such AS a gate insulating layer 12 between the gate electrode G2 and the active layer AS of the second transistor T2, and a passivation layer 13 between the source electrode S2, the drain electrode D2 and the second pixel electrode 30 of the second transistor T2.

The active layer AS comprises a channel region, a source region and a drain region which are positioned at two sides of the channel region, and the grid G2 is arranged corresponding to the channel region. The source electrode S2 and the drain electrode D2 cover the corresponding source region and drain region, respectively. The second pixel electrode 30 is connected to the source electrode S2 or the drain electrode D2 through a via hole of the passivation layer 13, and the embodiment of the utility model is described by taking the electrical connection between the second pixel electrode 30 and the drain electrode D2 as an example.

The first light shielding portion 51 is located on the buffer layer 11 and is disposed on the same layer as the gate G2 of the second transistor T2, and the gate G2 of the second transistor T2 is disposed on the same layer as the gate scan line GL. The second sub-discharging rod 42 is located on the gate insulating layer 12 and is arranged on the same layer as the source S2 and the drain D2 of the second transistor T2, and the second sub-discharging rod 42 is arranged corresponding to the first light shielding portion 51. The second sub-discharging rod 42 includes a metal layer in the same layer AS the source S2 and the drain D2 of the second transistor T2 and a semiconductor portion in the same layer AS the active layer AS of the second transistor T2. The first main electrode 21 of the first pixel electrode 20 is located on the passivation layer 13, the first main electrode 21 is disposed corresponding to the second sub-discharging rod 42, and a gap is formed between the first main electrode 21 and the first branch electrode 23, which is a slit (slit) of the first pixel electrode 20.

Based on the same inventive concept, an embodiment of the present utility model further provides a display panel, referring to fig. 1 to fig. 6, and fig. 6 is a schematic cross-sectional structure of the display panel according to the embodiment of the present utility model. The display panel includes the array substrate 100 of one of the foregoing embodiments. The display panel is a liquid crystal display panel or the like, and the present embodiment describes the display panel as a liquid crystal display panel. Specifically, referring to fig. 6, the display panel 1000 includes a first substrate and a second substrate disposed opposite to each other, and one of the first substrate and the second substrate is the array substrate 100 of one of the foregoing embodiments. In this embodiment, the first substrate is taken as the array substrate 100 as an example, and the second substrate 200 is a color film substrate. The display panel 1000 further includes liquid crystal molecules 300 interposed between the array substrate 100 and the second substrate 200.

As can be seen from the above embodiments:

The utility model provides an array substrate and a display panel, wherein the array substrate comprises a plurality of grid scanning lines extending along a first direction and data lines extending along a second direction, the grid scanning lines and the data lines are crossed to define a plurality of pixel areas, each pixel area is provided with a sub-pixel, each sub-pixel comprises a first pixel electrode, a second pixel electrode and a plurality of transistors positioned on the same side of the first pixel electrode and the second pixel electrode, the first pixel electrode extends along the first direction, the second pixel electrode extends along the first direction, in addition, in the second direction, the second pixel electrode and the first pixel electrode are arranged at intervals, and each sub-pixel comprises eight display domains, so that eight display domains are displayed, the viewing angle is improved, and the technical problem of poor viewing angle of the existing three-grid liquid crystal display panel is solved.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.

The foregoing has described in detail embodiments of the present utility model, and specific examples have been employed herein to illustrate the principles and embodiments of the present utility model, the above description of the embodiments being only for the purpose of aiding in the understanding of the technical solution and core idea of the present utility model; those of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the utility model.

Claims (10)

1. The array substrate is characterized by comprising a plurality of gate scanning lines extending along a first direction and data lines extending along a second direction, wherein the gate scanning lines and the data lines are intersected to define a plurality of pixel areas, each pixel area is provided with a sub-pixel, and each sub-pixel comprises a first pixel electrode, a second pixel electrode and a plurality of transistors positioned on the same side of the first pixel electrode and the second pixel electrode, wherein:

the first pixel electrode extends along the first direction;

The second pixel electrode extends along the first direction, the second pixel electrode and the first pixel electrode are arranged at intervals in the second direction, and the second pixel electrode and the first pixel electrode both comprise four display domains; and

The plurality of transistors includes a first transistor electrically connected to the first pixel electrode and a second transistor electrically connected to the second pixel electrode.

2. The array substrate according to claim 1, wherein the plurality of transistors further includes a third transistor, a source of the third transistor is electrically connected to a drain of the second transistor, a drain of the second transistor is further electrically connected to the second pixel electrode, and a source of the second transistor is electrically connected to the data line;

The array substrate further comprises a shared discharging rod, wherein the shared discharging rod and the data line are arranged on the same layer and are electrically connected with the drain electrode of the third transistor.

3. The array substrate of claim 2, wherein the shared discharging bar includes a first sub discharging bar extending along the first direction, the first sub discharging bar being disposed corresponding to the gate scan line.

4. The array substrate of claim 3, wherein the first sub-discharge bar is disposed above the gate scan line, and a width of the first sub-discharge bar in the second direction is smaller than a width of the gate scan line in the second direction.

5. The array substrate of claim 3, wherein the shared discharging bar further comprises a second sub discharging bar extending along the second direction, the second sub discharging bar being connected to the first sub discharging bar;

The first pixel electrode comprises a first main electrode extending along the second direction, the second pixel electrode comprises a second main electrode extending along the second direction, and the second sub-discharging rod is arranged below the first main electrode and the second main electrode.

6. The array substrate of claim 5, wherein in the second direction, the first stem electrode and the second stem electrode overlap, and the first stem electrode is located in a middle region of the first pixel electrode, and the second stem electrode is located in a middle region of the second pixel electrode.

7. The array substrate according to claim 5, further comprising a first light shielding portion extending along the second direction, wherein the first light shielding portion is disposed corresponding to the second sub-discharge rod and is located below the second sub-discharge rod.

8. The array substrate of claim 7, wherein the first light shielding portion is disposed on the same layer as the gate scan line, and a width of the first light shielding portion in the first direction is greater than a width of the second sub-discharge bar in the first direction.

9. The array substrate according to claim 1, further comprising a second light shielding portion disposed corresponding to the data line and above the data line.

10. A display panel comprising the array substrate according to any one of claims 1 to 9.