CN220896677U - Frequency source circuit based on low-frequency phase-locked loop and low-phase noise reference source mixing mode - Google Patents
Frequency source circuit based on low-frequency phase-locked loop and low-phase noise reference source mixing mode Download PDFInfo
- Publication number
- CN220896677U CN220896677U CN202322878998.2U CN202322878998U CN220896677U CN 220896677 U CN220896677 U CN 220896677U CN 202322878998 U CN202322878998 U CN 202322878998U CN 220896677 U CN220896677 U CN 220896677U
- Authority
- CN
- China
- Prior art keywords
- frequency
- low
- phase
- reference source
- loop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000006243 chemical reaction Methods 0.000 claims abstract description 21
- 239000013078 crystal Substances 0.000 claims abstract description 10
- 238000001228 spectrum Methods 0.000 claims description 6
- 238000001914 filtration Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 7
- 238000004088 simulation Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000003786 synthesis reaction Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 101710170230 Antimicrobial peptide 1 Proteins 0.000 description 1
- 101710170231 Antimicrobial peptide 2 Proteins 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 238000000844 transformation Methods 0.000 description 1
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The utility model discloses a frequency source circuit based on a low-frequency phase-locked loop and low-phase noise reference source mixing mode, which comprises the following components: the device comprises a crystal oscillator, a power divider, a reference source unit and a main ring unit; the power divider is used for dividing a clock signal generated by a crystal oscillator into two paths and inputting the two paths into a reference source unit and a reference source unit respectively, the main loop unit comprises an analog phase discriminator HMC3716, a second low-pass filter and a main loop conversion loop ADF4401A which form a loop structure, the reference source unit comprises a phase-locked loop chip HMC830 and a first low-pass filter which are connected, and the reference source unit comprises a first amplifier, a frequency multiplier, a first band-pass filter, a harmonic generator and the like which are connected in sequence. The utility model realizes the frequency source design with small steps, agility and low phase noise by switching the low-frequency phase-locked loop switch and mixing with the low phase noise reference source.
Description
Technical Field
The utility model belongs to the technical field of microwave radio frequency components, relates to frequency source design, and particularly relates to a frequency source circuit based on a low-frequency phase-locked loop and low-phase-noise reference source mixing mode.
Background
In the field of microwave communication, the use environment of radio frequency transceiver equipment is diversified more and more, and many scenes have higher and higher requirements on system noise, and more stringent requirements are brought to scheme design of internal modules of the equipment. Frequency sources are an integral part of these systems, and their phase noise has a great influence on the performance of the entire system, so that ultra-low noise frequency sources are becoming an increasingly desirable target for design.
At present, in order to achieve the aim of low phase noise, the main using techniques are as follows: direct synthesis schemes, high clock frequency direct digital frequency synthesis schemes, phase-locked loop external up-conversion schemes, phase-locked loop internal down-conversion schemes, and the like. The scheme has advantages and disadvantages, and in order to ensure the balance of factors such as extremely low phase noise, low spurious level in broadband, small steps, low cost and the like, the down-conversion scheme in the phase-locked loop becomes the optimal choice under the current technical condition.
Disclosure of utility model
The technical purpose is that: aiming at the technical problems, the utility model provides a frequency source circuit based on a low-frequency phase-locked loop and low-phase-noise reference source mixing mode, and the frequency source design with small steps, frequency agility and low phase noise is realized through the low-frequency phase-locked loop switch switching and low-phase-noise reference source mixing mode.
The technical scheme is as follows: in order to achieve the technical purpose, the utility model adopts the following technical scheme:
A frequency source circuit based on a mixing mode of a low-frequency phase-locked loop and a low-phase noise reference source, comprising: the device comprises a crystal oscillator, a power divider, a reference source unit and a main ring unit; the power divider is used for dividing a 100MHz clock signal generated by a crystal oscillator into two paths and respectively inputting the two paths into the reference source unit and the reference source unit, the main loop unit comprises an analog phase discriminator HMC3716, a second low-pass filter and a main loop conversion loop ADF4401A which form a loop structure, the analog phase discriminator HMC3716 is provided with a first signal input end, a second signal input end and a phase demodulation output end, the main loop conversion loop ADF4401A is provided with a reference signal input end, a reference signal input end and a frequency source output end, and the second signal input end is connected with the reference signal input end;
The reference source unit comprises a first amplifier, a frequency multiplier, a first band-pass filter, a harmonic generator, a second band-pass filter and a second amplifier which are sequentially connected, wherein the output end of the second amplifier outputs a reference source of 4.5GHz ultra-low phase noise, and the reference source is input into the reference source input end of the ADF4401A of the main loop conversion loop;
The reference source unit comprises a phase-locked loop chip HMC830 and a first low-pass filter which are connected, wherein a 1.5-3 GHz VCO is integrated in the phase-locked loop chip HMC830, the first low-pass filter outputs a reference source with low phase noise of 0.5-0.7 GHz, and the reference source is input into a first signal input end of an analog phase discriminator HMC 3716;
The frequency source output end of the ADF4401A outputs a 5-5.2 GHz frequency signal, and the 5-5.2 GHz frequency signal is used as the output signal of the ultralow phase noise frequency source circuit and is connected to the second signal input end of the HMC3716 analog phase discriminator.
Preferably, the frequency multiplier is a passive frequency multiplier and is used for generating a 500MHz frequency multiplication signal; the harmonic generator adopts a comb spectrum generator and is used for exciting each subharmonic of a 500MHz frequency multiplication signal; the second band-pass filter is used for selecting 4.5GHz frequency signals from all subharmonics generated by the comb spectrum generator, and the second band-pass filter and the second amplifier are used for sequentially filtering and amplifying the 4.5GHz frequency signals and outputting a reference source of 4.5GHz ultra-low phase noise.
Preferably, the inside of the ADF4401A of the primary loop switching loop is integrated with a 4-8 GHz band VCO, which is configured to output an ultra-low phase noise frequency source of 5-5.2 GHz by means of down-conversion phase locking.
The beneficial effects are that: due to the adoption of the technical scheme, the utility model has the following beneficial effects:
The ultra-low phase frequency conversion source provided by the utility model can cover 5-5.2 GHz, has ultra-low phase noise, can reach the level of-126 dBc/Hz@10kHz when the output frequency is 5.1GHz, can expand the frequency range and the step on the basis of the scheme, and is applied to more scenes.
Drawings
FIG. 1 is a functional block diagram of a frequency source circuit based on a low frequency phase locked loop and low phase noise reference source mixing scheme;
FIG. 2 is a graph of reference loop phase noise for the reference cell of FIG. 1;
FIG. 3 is an internal functional block diagram of the ADF4401A of FIG. 1;
FIG. 4 is a circuit diagram of a filter in a main loop switching loop;
FIG. 5 is a phase noise plot of the frequency source circuit of FIG. 1;
The system comprises an OC 1-crystal oscillator, a PV-power divider, an AMP 1-first amplifier, a PM 1-passive frequency multiplier, a BPF 1-first band-pass filter, a CG 1-comb spectrum generator, a BPF 2-second band-pass filter, an AMP 2-second amplifier, an LPF 1-first low-pass filter and an LPF 2-second low-pass filter.
Detailed Description
Embodiments of the present utility model will be described in detail below with reference to the accompanying drawings.
The utility model provides an ultralow phase noise frequency source, which is characterized in that a down-mixing frequency conversion link is built on the basis of a conversion loop ADF4401A, a local oscillator is directly synthesized by adopting a high-stability crystal oscillator and is used as an ultralow phase noise reference source, the whole frequency source outputs 5-5.2 GHz, the frequency step is 25MHz, and the phase noise which is offset by 10kHz is-126 dBc/Hz, so that the design of a low-step and low-phase noise high-performance frequency source is achieved. The method is mainly realized in three parts: firstly, realizing an ultralow phase noise 4.5GHz reference source by a direct synthesis (frequency multiplication plus comb spectrum generation) mode; secondly, realizing a low-phase-noise 0.5-0.7 GHz reference source through phase locking; finally, down-conversion phase locking is carried out on the main loop part to realize 5-5.2 GHz ultra-low phase noise frequency source. The overall schematic block diagram is shown in fig. 1.
In the scheme, a first part adopts a 100MHz crystal oscillator OC1 with ultra-low phase noise as a clock signal, the output signal passes through a first amplifier AMP1 and a passive frequency multiplier FM1 to obtain a first-stage reference signal with the frequency of 500MHz, the reference signal passes through a first band-pass filter BPF1, then enters a harmonic generator to excite various harmonics with the frequency of 500MHz after being driven by the first amplifier, 4.5GHz is selected for filtering and amplifying by a second band-pass filter BPF2 and a second amplifier AMP2, namely 4.5GHz ultra-low phase noise point frequency is directly synthesized and output, and a frequency multiplication phase noise degradation formula is as follows:
PN＝PNREF+20lg(N)
Meanwhile, the phase noise can be deteriorated by about 2dB after the signals pass through the harmonic generator and the frequency multiplier, and the PN 4.5GHz = -168+20lg (45) +2 (dBc/Hz) can be calculated at the position of shifting by 10 kHz.
The second part in this scheme is a reference loop, which uses a phase-locked loop chip HMC830 of the integrated VCO, and the reference signal of the loop is a 100MHz signal from which the crystal oscillator power is split. The VCO frequency inside HMC830 is 1.5-3 GHz, and after the loop is locked, the internal four-frequency division output is needed, and when the phase demodulation frequency is fixed 100MHz, 25MHz frequency stepping can be achieved. As can be seen from the loop simulation, the index of-130 dBc/Hz can be reached when the offset is 10kHz, and the phase noise simulation curve is shown in FIG. 2.
The main loop part in the scheme is the core of the scheme, the phase discriminator adopts a high phase discrimination frequency analog phase discriminator HMC3716, the equivalent single sideband phase noise floor of 100MHz can reach-153 dBc/Hz@10kHz, and the whole loop noise is basically not deteriorated; ADF4401A integrated with 4-8 GHz frequency band VCO, frequency converter and intermediate frequency filter amplifier is selected as the primary loop conversion loop, so that noise superposition degradation is avoided, in-loop N value can be effectively reduced, and phase noise level is reduced. Fig. 3 is a diagram of the internal functional units of the conversion loop ADF 4401A. Fig. 4 is a circuit diagram of a filter in the main loop switching loop of fig. 1.
The main loop design is carried out according to the general schematic diagram of fig. 1, ADISIMPLL software is used for loop simulation, the circuit structure formed by a reference source and a conversion loop is equivalent to a VCO during simulation, then modeling is substituted into the software, and the loop phase noise simulation result is shown in fig. 5.
According to the calculation result, when 5.1GHz is output, the phase noise of the whole frequency source can reach-126 dBc/Hz@10kHz, and the phase noise level can be applied to most signal source use scenes. The application is not limited to the general vibration source, can be embedded into a communication receiving and transmitting system, and can exert the advantages of a high-sensitivity and time-limited system.
The foregoing has shown and described the basic principles, principal features and advantages of the utility model. It will be appreciated by persons skilled in the art that the above embodiments are not intended to limit the utility model in any way, and that all technical solutions obtained by means of equivalent substitutions or equivalent transformations fall within the scope of the utility model.
Claims (3)
1. A frequency source circuit based on a mixing mode of a low-frequency phase-locked loop and a low-phase noise reference source, comprising: a crystal oscillator (OC 1), a power divider (PV), a reference source unit and a main ring unit; the power divider is used for dividing a 100MHz clock signal generated by a crystal oscillator (OC 1) into two paths and respectively inputting the two paths into the reference source unit and the reference source unit; the main loop unit comprises an analog phase discriminator HMC3716, a second low pass filter (LPF 2) and a main loop conversion loop ADF4401A, wherein the analog phase discriminator HMC3716 is provided with a first signal input end, a second signal input end and a phase discriminator output end, the main loop conversion loop ADF4401A is provided with a reference signal input end, a reference signal input end and a frequency source output end, and the second signal input end is connected with the reference signal input end;
The reference source unit comprises a first amplifier (AMP 1), a frequency multiplier, a first band-pass filter (BPF 1), a harmonic generator, a second band-pass filter (BPF 2) and a second amplifier (AMP 2) which are sequentially connected, wherein the output end of the second amplifier (AMP 2) outputs a reference source of 4.5GHz ultra-low phase noise, and the reference source is input into the reference source input end of the main loop conversion loop ADF 4401A;
The reference source unit comprises a phase-locked loop chip HMC830 and a first low-pass filter (LPF 1) which are connected, wherein a 1.5-3 GHz VCO is integrated in the phase-locked loop chip HMC830, the first low-pass filter (LPF 1) outputs a reference source with low phase noise of 0.5-0.7 GHz, and the reference source is input into a first signal input end of an analog phase discriminator HMC 3716;
the frequency source output end of the primary loop conversion loop ADF4401A outputs a 5-5.2 GHz frequency signal, and the 5-5.2 GHz frequency signal is used as an output signal of the frequency source circuit and is connected to the second signal input end of the HMC3716 analog phase discriminator.
2. The frequency source circuit based on the mixing mode of the low-frequency phase-locked loop and the low-phase noise reference source according to claim 1, wherein: the frequency multiplier is a passive frequency multiplier (FM 1) and is used for generating a 500MHz frequency multiplication signal; the harmonic generator adopts a comb spectrum generator (CG 1) for exciting and generating each subharmonic of 500MHz frequency multiplication signals; the second band-pass filter (BPF 2) is used for selecting 4.5GHz frequency signals from all subharmonics generated by the comb spectrum generator (CG 1), and the second band-pass filter (BPF 2) and the second amplifier (AMP 2) are used for sequentially filtering and amplifying the 4.5GHz frequency signals and outputting a reference source of 4.5GHz ultra-low phase noise.
3. The frequency source circuit based on the mixing mode of the low-frequency phase-locked loop and the low-phase noise reference source according to claim 2, wherein: the inside of the ADF4401A of the primary loop conversion loop is integrated with a 4-8 GHz frequency band VCO, and the VCO is used for outputting an ultra-low phase noise frequency source of 5-5.2 GHz in a down-conversion phase locking mode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322878998.2U CN220896677U (en) | 2023-10-26 | 2023-10-26 | Frequency source circuit based on low-frequency phase-locked loop and low-phase noise reference source mixing mode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322878998.2U CN220896677U (en) | 2023-10-26 | 2023-10-26 | Frequency source circuit based on low-frequency phase-locked loop and low-phase noise reference source mixing mode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN220896677U true CN220896677U (en) | 2024-05-03 |
Family
ID=90836890
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202322878998.2U Active CN220896677U (en) | 2023-10-26 | 2023-10-26 | Frequency source circuit based on low-frequency phase-locked loop and low-phase noise reference source mixing mode |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN220896677U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118367927A (en) * | 2024-06-19 | 2024-07-19 | 成都青翎科技有限公司 | Phase-locked loop circuit and phase-locked loop method |
-
2023
- 2023-10-26 CN CN202322878998.2U patent/CN220896677U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118367927A (en) * | 2024-06-19 | 2024-07-19 | 成都青翎科技有限公司 | Phase-locked loop circuit and phase-locked loop method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108736889B (en) | Low spurious/low phase noise frequency synthesizer | |
| CN220896677U (en) | Frequency source circuit based on low-frequency phase-locked loop and low-phase noise reference source mixing mode | |
| JPH01151823A (en) | Frequency synthesizer | |
| JP2013523056A (en) | Frequency multiplier transceiver | |
| CN102237889B (en) | RF digital spur reduction | |
| Yu et al. | A Single-Chip 125-MHz to 32-GHz Signal Source in 0.18-$\mu $ m SiGe BiCMOS | |
| CN111106830B (en) | Fast and agile broadband frequency synthesizer | |
| CN102237890B (en) | Integrated RF transceiver circuit and method for forming digital clock signals | |
| CN113162617B (en) | Low-phase-noise X-band frequency source and modulation method thereof | |
| CN116470909A (en) | Low-phase noise fine stepping frequency synthesis circuit and synthesis method thereof | |
| WO1998036491A1 (en) | Voltage controlled ring oscillator frequency multiplier | |
| CN101256229A (en) | Receiving apparatus | |
| KR100997491B1 (en) | Communication Transmitter Using Offset Phase-Locked-Loop | |
| CN110729996A (en) | Phase-locked loop circuit and method for miniaturization double phase locking | |
| CN113726334A (en) | S-band low-phase-noise low-spurious fine-stepping frequency source component and using method | |
| CN113794473A (en) | Universal frequency synthesizer and synthesis method | |
| CN117176149A (en) | Circuit for realizing millimeter wave frequency expansion | |
| CN115940938A (en) | Low-phase-noise fast broadband frequency sweeping frequency source | |
| CN109412591B (en) | X-waveband fine-stepping frequency synthesis generation method and system | |
| CN117081588A (en) | Broadband low-phase-noise agile frequency synthesizer and signal synthesis method thereof | |
| KR101007210B1 (en) | High frequency synthesizer for airbone with compact size | |
| JP3825540B2 (en) | Receiver and transceiver | |
| CN103297044B (en) | Microwave signal source and method for producing microwave signal | |
| CN211239828U (en) | X-waveband 10Hz stepping low-stray-frequency source | |
| Zhang et al. | A 1.6-to-3.2/4.8 GHz dual-modulus injection-locked frequency multiplier in 0.18 μm digital CMOS |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |