CN220896528U

CN220896528U - EMC filter circuit

Info

Publication number: CN220896528U
Application number: CN202322443099.XU
Authority: CN
Inventors: 祝传美; 王灿; 黄伟康
Original assignee: Enwo New Energy Technology Shanghai Co ltd
Current assignee: Enwo New Energy Technology Shanghai Co ltd
Priority date: 2023-09-08
Filing date: 2023-09-08
Publication date: 2024-05-03
Anticipated expiration: 2033-09-08

Abstract

The utility model relates to an EMC filter circuit, and belongs to the technical field of circuit structures. The EMC filter circuit comprises a first surge absorption unit, a second surge absorption unit and a third surge absorption unit which are connected with a live wire L and a null wire N, wherein the first surge absorption unit, the second surge absorption unit and the third surge absorption unit are used for carrying out surge immunity on transient spike interference signals; the system also comprises a first-level EMC filtering module and a second-level EMC filtering module which are used for inhibiting common-mode interference signals and differential-mode interference signals. Therefore, the electromagnetic interference signal can be effectively restrained, accumulated charges are released, so that the signal stability is ensured, the EMC filter circuit meets the EMC requirements, the electromagnetic interference signal filter circuit can be widely applied to various micro-inverters and other electronic products, the safety of the products is ensured, and the service life of the products is prolonged.

Description

EMC filter circuit

Technical Field

The utility model relates to the technical field of circuit structures, in particular to the technical field of filter circuit structures, and specifically relates to an EMC filter circuit.

Background

EMC is electromagnetic compatibility (Electromagnetic Compatibility) that means that an electronic device or network system has a certain resistance to electromagnetic interference while not being able to generate excessive electromagnetic radiation. That is, the device or network system is required to operate normally in a relatively harsh electromagnetic environment, while not radiating excessive electromagnetic waves to interfere with the normal operation of other surrounding devices and networks.

In the field of micro-inverters, when the power increases, the existing conventional filter device cannot meet the EMC requirements. In the DC-AC conversion process, the transistor repeatedly works in the off and on states, thereby leading to the continuous formation of a superposition of the electric charge amounts of di/dt and du/dt in the PN junction of the transistor. If the electric charge is not released in time, a loop and a space electromagnetic field wave are formed, electromagnetic interference signals are generated, and the normal operation of the whole inverter is affected.

Therefore, how to provide an EMC filter circuit capable of effectively suppressing electromagnetic interference signals and releasing accumulated charges, so as to ensure stable signals and meet EMC requirements is a problem to be solved in the art.

Disclosure of utility model

The utility model aims to overcome the defects in the prior art and provide the EMC filter circuit which can effectively inhibit electromagnetic interference signals and release accumulated charges, thereby ensuring stable signals and meeting EMC requirements.

In order to achieve the above object, an EMC filter circuit of the present utility model has the following configuration:

The EMC filter circuit comprises a first surge absorption unit, a second surge absorption unit and a third surge absorption unit which are connected with a live wire L and a null wire N; the first surge absorbing unit, the second surge absorbing unit and the third surge absorbing unit are used for carrying out surge immunity on transient spike interference signals; the first sudden wave absorption unit and the second sudden wave absorption unit are connected with a second-level EMC filter module, the second sudden wave absorption unit and the third sudden wave absorption unit are connected with a first-level EMC filter module, and the first-level EMC filter module and the second-level EMC filter module are also connected with a ground wire G for inhibiting common-mode interference signals and differential-mode interference signals.

In the EMC filter circuit, the first surge absorption unit comprises a fifth piezoresistor RV5, a sixth piezoresistor RV6 and a first discharge tube, one ends of the fifth piezoresistor RV5 and the fifth piezoresistor RV6 are respectively connected to a live wire L and a zero wire N, the other ends of the fifth piezoresistor RV5 and the fifth piezoresistor RV6 are both connected to one end of the first discharge tube, and the other end of the first discharge tube is grounded; the first surge absorbing unit is used for carrying out surge immunity on transient spike interference signals received from the live wire L and the null wire N; the second surge absorption unit comprises a fourth piezoresistor RV4 and a second discharge tube, one end of the fourth piezoresistor RV4 is connected to the live wire L, the other end of the fourth piezoresistor RV4 is connected to one end of the second discharge tube, the other end of the second discharge tube is connected to the zero line N, and the second surge absorption unit is used for carrying out surge immunity on transient spike interference signals transmitted from the second-level EMC filtering module; the third surge absorption unit comprises a first piezoresistor RV1, a second piezoresistor RV2, a third piezoresistor RV3 and a first discharge tube, wherein one end of the first piezoresistor RV1 is connected to a live wire L, and the other end of the first piezoresistor RV1 is connected to a zero line N; one ends of the second piezoresistor RV2 and the third piezoresistor RV3 are respectively connected to the live wire L and the zero wire N, the other ends of the second piezoresistor RV2 and the third piezoresistor RV3 are connected with one end of the third discharge tube, the other end of the third discharge tube is grounded, and the third surge absorption unit is used for carrying out surge immunity on transient spike interference signals received from the primary EMC filtering module.

In the EMC filter circuit, the primary EMC filter module comprises a primary common mode rejection unit and a primary differential mode rejection unit, wherein the primary common mode rejection unit is used for rejecting common mode interference signals in signals output by the surge absorption unit and discharging the common mode interference signals to a ground wire G; the first-stage differential mode suppression unit is used for suppressing differential mode interference signals in signals output by the surge absorption unit.

In the EMC filter circuit, the primary EMC filter module comprises a first common mode inductance L1, a first capacitor C2, a first capacitor C3, a first capacitor C5 and a fuse, and is connected with a second surge absorption unit; one end of the capacitor C1 is connected to the live wire L, and the other end is connected to the zero line N; the output end of the first common mode inductor L1 is connected in parallel with the second capacitor C2; one end of the third capacitor C3 is connected to the live wire L, and the other end of the third capacitor C is connected with the ground wire; one end of the fifth capacitor C5 is connected to the zero line N, and the other end of the fifth capacitor C is connected with the ground wire; the fuse is connected in series with the live wire L.

In the EMC filter circuit, the first-stage common-mode rejection unit includes the first common-mode inductor L1, the third capacitor C3, and the fifth capacitor C5; the two coils of the first common-mode inductor L1 are wound on the same winding in the same direction and have the same number of turns, the numerical range of the common-mode inductance of the first common-mode inductor L1 is 1.8-4.7 mH, the numerical range of the differential-mode inductance is 100-300 mu H, the differential-mode inductance is used for performing attenuation inhibition on common-mode interference signals, and the common-mode interference signals on a live wire L and a null wire N are discharged to a ground wire G through a third capacitor C3 and a fifth capacitor C5 respectively; the primary differential mode suppression unit comprises leakage inductance of the first common mode inductor L1 and a second capacitor C2, and the differential mode interference signal is filtered through a low-pass filter formed by the leakage inductance and the second capacitor C2.

In the EMC filter circuit, the secondary EMC filter module comprises a secondary common mode rejection unit and a secondary differential mode rejection unit; the second-level common mode suppression unit is used for suppressing common mode interference signals in signals output by the first-level EMC filtering module and discharging the common mode interference signals to a ground wire G; the second-stage differential mode suppression unit is used for suppressing differential mode interference signals in the signals output by the first surge absorption unit.

In the EMC filter circuit, the second-level EMC filter module includes a second common-mode inductance L2, a fourth capacitance C4, a sixth capacitance C6, and a seventh capacitance C7; the input end of the second-level EMC filter module is connected with the output end of the first-level EMC filter module; one end of the fourth capacitor C4 is connected to the live wire L, and the other end of the fourth capacitor C is connected to the zero line N; one end of the sixth capacitor C6 is connected to the live wire L, and the other end of the sixth capacitor C is connected with the ground wire; one end of the seventh capacitor C7 is connected to the zero line N, and the other end of the seventh capacitor C is connected to the ground line.

In the EMC filter circuit, the second-stage common-mode rejection unit includes the second common-mode inductor L2, a sixth capacitor C6, and a seventh capacitor C7; the two coils of the second common-mode inductor L2 are wound on the same winding in the same direction and have the same number of turns, the value range of the common-mode inductance of the second common-mode inductor L2 is 1.8-4.7 mH, the value range of the differential-mode inductance is 100-300 mu H, the differential-mode inductance is used for playing a role in attenuation inhibition on common-mode interference signals, and the common-mode interference signals on a live wire L and a null wire N are discharged to a ground wire G through a sixth capacitor C6 and a seventh capacitor C7 respectively; the second-stage differential mode suppression unit comprises leakage inductance of the second common-mode inductor L2 and the fourth capacitor C4; the leakage inductance and the fourth capacitor C4 form a low-pass filter, and the differential mode interference signal is filtered.

The EMC filter circuit comprises a first surge absorption unit, a second surge absorption unit and a third surge absorption unit which are connected with a live wire L and a null wire N, wherein the first surge absorption unit, the second surge absorption unit and the third surge absorption unit are used for carrying out surge immunity on transient spike interference signals; the system also comprises a first-level EMC filtering module and a second-level EMC filtering module which are used for inhibiting common-mode interference signals and differential-mode interference signals. Therefore, the electromagnetic interference signal can be effectively restrained, accumulated charges are released, so that the signal stability is ensured, the EMC filter circuit meets the EMC requirements, the electromagnetic interference signal filter circuit can be widely applied to various micro-inverters and other electronic products, the safety of the products is ensured, and the service life of the products is prolonged.

Drawings

FIG. 1 is a block diagram of an EMC filter circuit of the present utility model;

FIG. 2 is a circuit diagram of an EMC filter circuit of the present utility model;

FIG. 3a is a schematic diagram of signals of the receiving/outputting of an EMC filter circuit without the present utility model;

Fig. 3b is a signal diagram of the reception/output of the EMC filter circuit to which the present utility model is added.

Detailed Description

In order to make the technical contents of the present utility model more clearly understood, the following examples are specifically described.

The electromagnetic interference signals in the signals received on the live wire L and the null wire N of the alternating current input end comprise common-mode interference signals and differential-mode interference signals, wherein the common-mode interference signals refer to electromagnetic interference signals transmitted between the live wire L (the null wire N) and the ground wire G, and the differential-mode interference signals refer to electromagnetic interference signals transmitted between the live wire L and the null wire N.

Fig. 1 is a block diagram showing an EMC filter circuit according to the present utility model.

In one embodiment, the EMC filter circuit includes a first surge absorbing unit, a second surge absorbing unit, and a third surge absorbing unit connected to the live line L and the neutral line N. The ac input may receive a transient spike interference signal, that is, a surge interference signal, so that the spike absorption module is used to clamp the potential of the received signal, thereby suppressing the transient spike interference signal. The first surge absorbing unit, the second surge absorbing unit and the third surge absorbing unit are used for carrying out surge immunity on transient spike interference signals. The first sudden wave absorption unit and the second sudden wave absorption unit are connected with a second-level EMC filter module, the second sudden wave absorption unit and the third sudden wave absorption unit are connected with a first-level EMC filter module, and the first-level EMC filter module and the second-level EMC filter module are also connected with a ground wire G for inhibiting common-mode interference signals and differential-mode interference signals. The first, second and third surge absorption modules primarily inhibit electromagnetic interference signals in signals received by the input end, and the first-stage and second-stage EMC filtering modules respectively inhibit common-mode interference signals and differential-mode interference signals in the electromagnetic interference signals in two stages, so that the anti-interference capability of the micro inverter is improved.

In a preferred embodiment, the EMC filter circuit is as shown in fig. 2. The first surge absorption unit comprises a fifth piezoresistor RV5, a sixth piezoresistor RV6 and a first discharge tube, one ends of the fifth piezoresistor RV5 and the fifth piezoresistor RV6 are respectively connected to a live wire L and a zero wire N, the other ends of the fifth piezoresistor RV5 and the fifth piezoresistor RV6 are respectively connected to one end of the first discharge tube, and the other ends of the first discharge tube are grounded; the first surge absorbing unit is used for carrying out surge immunity on transient spike interference signals received from the live wire L and the null wire N. The second surge absorption unit comprises a fourth piezoresistor RV4 and a second discharge tube, one end of the fourth piezoresistor RV4 is connected to the live wire L, the other end of the fourth piezoresistor RV4 is connected to one end of the second discharge tube, the other end of the second discharge tube is connected to the zero line N, and the second surge absorption unit is used for carrying out surge immunity on transient spike interference signals transmitted from the second-level EMC filtering module. The third surge absorption unit comprises a first piezoresistor RV1, a second piezoresistor RV2, a third piezoresistor RV3 and a first discharge tube, wherein one end of the first piezoresistor RV1 is connected to a live wire L, and the other end of the first piezoresistor RV1 is connected to a zero line N; one ends of the second piezoresistor RV2 and the third piezoresistor RV3 are respectively connected to the live wire L and the zero wire N, the other ends of the second piezoresistor RV2 and the third piezoresistor RV3 are connected with one end of the third discharge tube, the other end of the third discharge tube is grounded, and the third surge absorption unit is used for carrying out surge immunity on transient spike interference signals received from the primary EMC filtering module.

In a more preferred embodiment, as shown in fig. 2, the first-stage EMC filter module includes a first-stage common-mode rejection unit and a first-stage differential-mode rejection unit, where the first-stage common-mode rejection unit is configured to reject a common-mode interference signal in a signal output by the surge absorption unit, and bleed the common-mode interference signal to the ground line G through the ground node G1; the first-stage differential mode suppression unit is used for suppressing differential mode interference signals in signals output by the surge absorption unit. The first-stage EMC filter module comprises a first common-mode inductor L1, a first capacitor C2, a first capacitor C3, a first capacitor C5 and a fuse, and is connected with the second surge absorption unit; one end of the capacitor C1 is connected to the live wire L, and the other end is connected to the zero line N; the output end of the first common mode inductor L1 is connected in parallel with the second capacitor C2; one end of the third capacitor C3 is connected to the live wire L, and the other end of the third capacitor C is connected with the ground node G1; one end of the fifth capacitor C5 is connected to the zero line N, and the other end of the fifth capacitor C5 is connected with the ground node G1; the fuse is connected in series with the live wire L.

The first-stage common mode rejection unit comprises a first common mode inductor L1, a third capacitor C3 and a fifth capacitor C5; the two coils of the first common-mode inductor L1 are wound on the same winding in the same direction and have the same number of turns, the numerical range of the common-mode inductance of the first common-mode inductor L1 is 1.8-4.7 mH, and the numerical range of the differential-mode inductance is 100-300 mu H. Since the transmission directions and the magnitudes of the common-mode interference signals on the live wire L and the neutral wire N are the same, the magnetic fields generated by the two coils of the common-mode interference signals on the live wire L and the neutral wire N in the first common-mode inductor L1 are the same, and the magnetic fields show larger impedance, so that attenuation inhibition effect is achieved on the common-mode interference signals, and the common-mode interference signals on the live wire L and the neutral wire N are discharged to the ground wire G through the ground node G1 through the third capacitor C3 and the fifth capacitor C5 respectively. The primary differential mode suppression unit comprises leakage inductance of the first common mode inductor L1 and a second capacitor C2, and the differential mode interference signal is filtered through a low-pass filter formed by the leakage inductance and the second capacitor C2.

The second-level EMC filter module comprises a second-level common mode rejection unit and a second-level differential mode rejection unit; the second-level common mode suppression unit is used for suppressing common mode interference signals in signals output by the first-level EMC filtering module and discharging the common mode interference signals to a ground line G through a ground node G2; the second-stage differential mode suppression unit is used for suppressing differential mode interference signals in the signals output by the first surge absorption unit. The second-level EMC filter module comprises a second common-mode inductor L2, a fourth capacitor C4, a sixth capacitor C6 and a seventh capacitor C7; the input end of the second-level EMC filter module is connected with the output end of the first-level EMC filter module; one end of the fourth capacitor C4 is connected to the live wire L, and the other end of the fourth capacitor C is connected to the zero line N; one end of the sixth capacitor C6 is connected to the live wire L, and the other end of the sixth capacitor C is connected with the ground node G2; one end of the seventh capacitor C7 is connected to the zero line N, and the other end of the seventh capacitor C is connected to the ground node G2.

The second common mode rejection unit comprises a second common mode inductance L2, a sixth capacitor C6 and a seventh capacitor C7; the two coils of the second common-mode inductor L2 are wound on the same winding in the same direction and have the same number of turns, the numerical range of the common-mode inductance of the second common-mode inductor L2 is 1.8-4.7 mH, and the numerical range of the differential-mode inductance is 100-300 mu H. Since the transmission directions and the magnitudes of the common-mode interference signals on the live wire L and the neutral wire N are the same, the magnetic fields generated by the two coils of the common-mode interference signals on the live wire L and the neutral wire N in the inductor L2 are the same, and the magnetic fields show larger impedance, so that the attenuation suppression effect on the common-mode interference signals is achieved, and the common-mode interference signals on the live wire L and the neutral wire N are discharged to the ground wire G through the ground node G2 through the sixth capacitor C6 and the seventh capacitor C7 respectively. The second-stage differential mode suppression unit comprises leakage inductance of the second common-mode inductor L2 and the fourth capacitor C4; the leakage inductance and the fourth capacitor C4 form a low-pass filter, and the differential mode interference signal is filtered.

In practical application, the first, second and fourth capacitors C1, C2 and C4 are X capacitors, and the capacitance value is between 0.22 and 0.68 mu F; the third, fifth, sixth and seventh capacitances C3, C5, C6, C7 are Y capacitances, the capacitance value of the third and fifth capacitances C3, C5 is between 4.7 and 10nF, and the capacitance value of the sixth and seventh capacitances C6, C7 is between 1.0 and 2.2 nF. Each magnetic core in the first common-mode inductance L1 and the second common-mode inductance L2 is made of manganese-zinc ferrite and EE 20.

As shown in fig. 3a and 3b, signal diagrams of the reception/output of the EMC filter circuit to which the present utility model is not added and to which the present utility model is added, respectively. In case of an increase in the photovoltaic inverter power, EMC is optimized. Under the condition that signals received on the live wire L and the zero line N are the same, after the EMC filter circuit is added, the signals output on the live wire L and the zero line N are more stable, and it can be obviously seen that compared with the condition that the signals are not added, the electromagnetic interference signal suppression circuit effectively suppresses the influence of electromagnetic interference signals on output signals, thereby achieving the safety requirements, meeting the electromagnetic compatibility of electronic products and being widely applied to electronic products such as micro-inverters.

In this specification, the utility model has been described with reference to specific embodiments thereof. It will be apparent that various modifications and variations can be made without departing from the spirit and scope of the utility model. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims

1. An EMC filter circuit is characterized by comprising a first surge absorbing unit, a second surge absorbing unit and a third surge absorbing unit which are connected with a live wire L and a zero wire N; the first surge absorbing unit, the second surge absorbing unit and the third surge absorbing unit are used for carrying out surge immunity on transient spike interference signals; the first sudden wave absorption unit and the second sudden wave absorption unit are connected with a second-level EMC filter module, the second sudden wave absorption unit and the third sudden wave absorption unit are connected with a first-level EMC filter module, and the first-level EMC filter module and the second-level EMC filter module are also connected with a ground wire G for inhibiting common-mode interference signals and differential-mode interference signals.

2. The EMC filter circuit according to claim 1, characterized in that,

The first surge absorption unit comprises a fifth piezoresistor RV5, a sixth piezoresistor RV6 and a first discharge tube, one ends of the fifth piezoresistor RV5 and the fifth piezoresistor RV6 are respectively connected to a live wire L and a zero wire N, the other ends of the fifth piezoresistor RV5 and the fifth piezoresistor RV6 are both connected to one end of the first discharge tube, and the other end of the first discharge tube is grounded; the first surge absorbing unit is used for carrying out surge immunity on transient spike interference signals received from the live wire L and the null wire N;

The second surge absorption unit comprises a fourth piezoresistor RV4 and a second discharge tube, one end of the fourth piezoresistor RV4 is connected to the live wire L, the other end of the fourth piezoresistor RV4 is connected to one end of the second discharge tube, the other end of the second discharge tube is connected to the zero line N, and the second surge absorption unit is used for carrying out surge immunity on transient spike interference signals transmitted from the second-level EMC filtering module;

The third surge absorption unit comprises a first piezoresistor RV1, a second piezoresistor RV2, a third piezoresistor RV3 and a first discharge tube, wherein one end of the first piezoresistor RV1 is connected to a live wire L, and the other end of the first piezoresistor RV1 is connected to a zero line N; one ends of the second piezoresistor RV2 and the third piezoresistor RV3 are respectively connected to the live wire L and the zero wire N, the other ends of the second piezoresistor RV2 and the third piezoresistor RV3 are connected with one end of a third discharge tube, the other end of the third discharge tube is grounded, and the third surge absorption unit is used for performing surge immunity on the transient spike interference signals received from the primary EMC filtering module.

3. The EMC filter circuit according to claim 2, characterized in that,

The primary EMC filter module comprises a primary common mode suppression unit and a primary differential mode suppression unit, wherein the primary common mode suppression unit is used for suppressing a common mode interference signal in a signal output by the surge absorption unit and discharging the common mode interference signal to a ground wire G; the first-stage differential mode suppression unit is used for suppressing differential mode interference signals in signals output by the surge absorption unit.

4. The EMC filter circuit according to claim 3, characterized in that,

The first-stage EMC filter module comprises a first common-mode inductor L1, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fifth capacitor C5 and a fuse, and is connected with the second surge absorption unit; one end of the capacitor C1 is connected to the live wire L, and the other end is connected to the zero line N; the output end of the first common mode inductor L1 is connected in parallel with the second capacitor C2; one end of the third capacitor C3 is connected to the live wire L, and the other end of the third capacitor C is connected with the ground wire; one end of the fifth capacitor C5 is connected to the zero line N, and the other end of the fifth capacitor C is connected with the ground wire; the fuse is connected in series with the live wire L.

5. The EMC filter circuit according to claim 4, wherein,

The first-stage common mode rejection unit comprises a first common mode inductor L1, a third capacitor C3 and a fifth capacitor C5; the two coils of the first common-mode inductor L1 are wound on the same winding in the same direction and have the same number of turns, the numerical range of the common-mode inductance of the first common-mode inductor L1 is 1.8-4.7 mH, the numerical range of the differential-mode inductance is 100-300 mu H, the differential-mode inductance is used for performing attenuation inhibition on common-mode interference signals, and the common-mode interference signals on a live wire L and a null wire N are discharged to a ground wire G through a third capacitor C3 and a fifth capacitor C5 respectively;

The primary differential mode suppression unit comprises leakage inductance of the first common mode inductor L1 and a second capacitor C2, and the differential mode interference signal is filtered through a low-pass filter formed by the leakage inductance and the second capacitor C2.

6. The EMC filter circuit according to claim 3, characterized in that,

The second-level EMC filter module comprises a second-level common mode rejection unit and a second-level differential mode rejection unit;

The second-level common mode suppression unit is used for suppressing common mode interference signals in signals output by the first-level EMC filtering module and discharging the common mode interference signals to a ground wire G; the second-stage differential mode suppression unit is used for suppressing differential mode interference signals in the signals output by the first surge absorption unit.

7. The EMC filter circuit according to claim 6, characterized in that,

The second-level EMC filter module comprises a second common-mode inductor L2, a fourth capacitor C4, a sixth capacitor C6 and a seventh capacitor C7; the input end of the second-level EMC filter module is connected with the output end of the first-level EMC filter module; one end of the fourth capacitor C4 is connected to the live wire L, and the other end of the fourth capacitor C is connected to the zero line N; one end of the sixth capacitor C6 is connected to the live wire L, and the other end of the sixth capacitor C is connected with the ground wire; one end of the seventh capacitor C7 is connected to the zero line N, and the other end of the seventh capacitor C is connected to the ground line.

8. The EMC filter circuit according to claim 7, characterized in that,

The second-stage common mode rejection unit comprises a second common mode inductor L2, a sixth capacitor C6 and a seventh capacitor C7; the two coils of the second common-mode inductor L2 are wound on the same winding in the same direction and have the same number of turns, the value range of the common-mode inductance of the second common-mode inductor L2 is 1.8-4.7 mH, the value range of the differential-mode inductance is 100-300 mu H, the differential-mode inductance is used for playing a role in attenuation inhibition on common-mode interference signals, and the common-mode interference signals on a live wire L and a null wire N are discharged to a ground wire G through a sixth capacitor C6 and a seventh capacitor C7 respectively;

the second-stage differential mode suppression unit comprises leakage inductance of the second common-mode inductor L2 and the fourth capacitor C4; the leakage inductance and the fourth capacitor C4 form a low-pass filter, and the differential mode interference signal is filtered.