CN220872923U

CN220872923U - Bias circuit with high power supply rejection ratio and low temperature coefficient

Info

Publication number: CN220872923U
Application number: CN202322226474.5U
Authority: CN
Inventors: 魏涛; 汪洋; 陈必江
Original assignee: Shanghai Pingsheng Microelectronics Technology Co ltd
Current assignee: Shanghai Pingsheng Microelectronics Technology Co ltd
Priority date: 2023-08-18
Filing date: 2023-08-18
Publication date: 2024-04-30
Anticipated expiration: 2033-08-18

Abstract

The utility model discloses a bias circuit with high power supply rejection ratio and low temperature coefficient, and relates to the technical field of bias circuits. The bias circuit comprises a transistor M1, wherein the source electrode of the transistor M1 is electrically connected with the cathode of a diode D1, the drain electrode of the transistor M1 is electrically connected with one end of a resistor R1, the other end of the resistor R1 is electrically connected with one end of a resistor R2, the resistor R2 is electrically connected with the anode of the diode D1, and the grid electrode of the transistor M1 is electrically connected with the drain electrode of the transistor M1. When the power supply voltage V _DD is changed at a constant temperature, the change of the clamping voltage V1 is smaller, so that the change of I _REF is smaller, and a higher power supply rejection ratio is obtained; at a constant supply voltage V _DD, as the temperature drops or rises, the threshold voltage V _TH of M1 drops or rises, but the resistance of R1 increases or decreases, which results in less variation of I _REF than conventional bias circuits, resulting in a lower temperature coefficient.

Description

Bias circuit with high power supply rejection ratio and low temperature coefficient

Technical Field

The utility model relates to the technical field of bias circuits, in particular to a bias circuit with high power supply rejection ratio and low temperature coefficient.

Background

The bias circuit may provide a determined current bias or voltage bias to the functional module of the integrated circuit to ensure that the functional module may function properly. In a radio frequency communication system, gallium arsenide (GaAs) pseudomorphic doped heterojunction field effect transistors (pHEMT) have the characteristics of high frequency, high power, low noise, and the like, so that the device is widely applied to the manufacture of radio frequency front end chips.

Fig. 2 is a schematic diagram of a conventional bias circuit based on GAAS PHEMT process in the prior art, as shown in fig. 2, the bias circuit is composed of a pHEMT transistor M1 and a resistor R1 with short-circuited gate and drain, and since the GAAS PHEMT process cannot realize an N-type transistor and a P-type transistor on the same substrate at the same time, a bandgap reference structure similar to a MOS process cannot be adopted, so as to avoid the influence of the change of power supply voltage and temperature on bias voltage or bias current. Therefore, under the condition of larger change of the power supply voltage and the temperature, the bias voltage or bias current of the bias circuit based on GAAS PHEMT process is easier to generate larger fluctuation; in view of this, we propose a bias circuit with high power supply rejection ratio and low temperature coefficient.

Disclosure of Invention

Aiming at the defects of the prior art, the utility model provides a bias circuit with high power supply rejection ratio and low temperature coefficient, and solves the problems mentioned in the background art.

In order to achieve the above purpose, the utility model is realized by the following technical scheme: a bias circuit with high power supply rejection ratio and low temperature coefficient, the bias circuit comprises a transistor M1, wherein a source electrode of the transistor M1 is electrically connected with a cathode of a diode D1, a drain electrode of the transistor M1 is electrically connected with one end of a resistor R1, the other end of the resistor R1 is electrically connected with one end of a resistor R2, the resistor R2 is electrically connected with an anode of the diode D1, and a grid electrode of the transistor M1 is electrically connected with a drain electrode of the transistor M1.

Optionally, the resistor R1 and the resistor R2 are both negative temperature coefficient resistors.

Optionally, the other end of the resistor R2 is electrically connected to the V _DD end.

Optionally, a source electrode of the transistor M1 is grounded, and the transistor M1 is a pHEMT transistor with a short-circuited gate and drain.

Optionally, the diode D1 is a schottky diode, the terminal V _DD is a connection terminal of the power supply voltage V _DD, and when the power supply voltage V _DD changes, the forward biased schottky diode clamps, the potential between R1 and R2 is clamped to a relatively fixed voltage value V1, and the reference current。

Optionally, the V _GS is a gate-source voltage of the pHEMT transistor M1.

The utility model provides a bias circuit with high power supply rejection ratio and low temperature coefficient. The beneficial effects are as follows:

1. in the bias circuit with high power supply rejection ratio and low temperature coefficient, when the power supply voltage V _DD changes at a constant temperature, the change of the clamping voltage V1 is small, so that the change of the I _REF is small, and the high power supply rejection ratio is obtained.

2. The bias circuit with high power supply rejection ratio and low temperature coefficient is characterized in that when the temperature is reduced or increased at a constant power supply voltage V _DD, the threshold voltage V _TH of M1 is reduced or increased, but the resistance of R1 is increased or reduced, so that I _REF is smaller in change compared with the traditional bias circuit, and the lower temperature coefficient is obtained.

Drawings

FIG. 1 is a schematic diagram of a biasing circuit of the present utility model;

fig. 2 is a schematic diagram of a conventional bias circuit based on GAAS PHEMT process in the prior art.

Detailed Description

The following description of the embodiments of the present utility model will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present utility model, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

Fig. 2 is a schematic diagram of a conventional bias circuit based on GAAS PHEMT process in the prior art, as shown in fig. 2, the bias circuit is composed of a pHEMT transistor M1 with a shorted gate and drain and a resistor R1,

Reference current；

Wherein V _GS is the gate-source voltage of pHEMT transistor M1; m1 is set to be in a saturated state;

The relationship between the current I _DSAT and the gate-source voltage V _GS of the pHEMT transistor in the saturated state is known as:

；

Where q represents the electron charge amount, W _D/L represents the width-to-length ratio of the pHEMT transistor, μ ₀ represents the electron mobility, V _TH represents the gate-source threshold voltage of M1, and n _2D represents the two-dimensional electron gas concentration.

Since the gate current in this circuit is very small, then I _DSTA=I_RFE can be considered, and thus can be derived:

；

It can be approximated that I _REF and V _DD ¹ are positively correlated, so that when a large change in the supply voltage V _DD occurs, I _REF will have a large change, i.e., the supply rejection is relatively low; it can be also approximately considered that I _REF and V _TH ¹ are inversely related, since the threshold voltage V _TH of M1 is a positive temperature coefficient parameter, when the temperature decreases/increases, the threshold voltage of M1 decreases/increases, and under the condition that R1 is unchanged, the reference current I _REF will increase/decrease in a larger range, that is, the temperature coefficient is higher, the GAAS PHEMT process cannot realize the N-type transistor and the P-type transistor on the same substrate at the same time, and therefore, a bandgap reference structure similar to the MOS process cannot be adopted to avoid the influence of the change of the power supply voltage and the temperature on the bias voltage or the bias current. Therefore, under the condition of large change of power supply voltage and temperature, the bias voltage or bias current of the bias circuit based on GAAS PHEMT process is easy to generate large fluctuation.

FIG. 1 is a schematic diagram of a biasing circuit of the present utility model; as shown in fig. 1, the present utility model provides a bias circuit with high power supply rejection ratio and low temperature coefficient, the bias circuit includes a transistor M1, a source electrode of the transistor M1 is electrically connected with a cathode electrode of a diode D1, a drain electrode of the transistor M1 is electrically connected with one end of a resistor R1, the other end of the resistor R1 is electrically connected with one end of a resistor R2, the resistor R2 is electrically connected with an anode electrode of the diode D1, and a gate electrode of the transistor M1 is electrically connected with a drain electrode of the transistor M1.

The resistor R1 and the resistor R2 are both negative temperature coefficient resistors. The other end of the resistor R2 is electrically connected with the end V _DD. The source of the transistor M1 is grounded, and the transistor M1 is a pHEMT transistor with a short-circuited gate and drain.

It is noted that the diode D1 is a Schottky diode, the terminal V _DD is a connection terminal of the power voltage V _DD, and when the power voltage V _DD changes, the forward biased Schottky diode clamps, the potential between R1 and R2 is clamped to a relatively fixed voltage value V1, the reference current。

V _GS is the gate-source voltage of pHEMT transistor M1, pHEMT transistor M1 is set to saturation, and the relationship between current I _DSAT and gate-source voltage V _GS of pHEMT transistor in saturation is known as:

Where q represents the electron charge amount, W _D/L represents the width-to-length ratio of the pHEMT transistor, μ ₀ represents the electron mobility, V _TH represents the gate-source threshold voltage of M1, and n _2D represents the two-dimensional electron gas concentration. Since the gate current in this circuit is very small, then I _DSTA=I_REF can be considered, and thus can be derived:

。

In the bias circuit with high power supply rejection ratio and low temperature coefficient, when the power supply voltage V _DD changes at constant temperature, the change of the clamping voltage V1 is smaller, so that the change of I _REF is smaller, and the high power supply rejection ratio is obtained; at a constant supply voltage V _DD, as the temperature drops or rises, the threshold voltage V _TH of M1 drops or rises, but the resistance of R1 increases or decreases, which results in less variation of I _REF than conventional bias circuits, resulting in a lower temperature coefficient.

Although embodiments of the present utility model have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the utility model, the scope of which is defined in the appended claims and their equivalents.

Claims

1. A high power supply rejection ratio and low temperature coefficient bias circuit, characterized by: the bias circuit comprises a transistor M1, wherein a source electrode of the transistor M1 is electrically connected with a cathode of a diode D1, a drain electrode of the transistor M1 is electrically connected with one end of a resistor R1, the other end of the resistor R1 is electrically connected with one end of a resistor R2, the resistor R2 is electrically connected with an anode of the diode D1, and a gate electrode of the transistor M1 is electrically connected with a drain electrode of the transistor M1.

2. The high power rejection ratio and low temperature coefficient biasing circuit of claim 1, wherein: the resistor R1 and the resistor R2 are negative temperature coefficient resistors.

3. The high power rejection ratio and low temperature coefficient biasing circuit of claim 1, wherein: the other end of the resistor R2 is electrically connected with the end V _DD.

4. The high power rejection ratio and low temperature coefficient biasing circuit of claim 1, wherein: the source electrode of the transistor M1 is grounded, and the transistor M1 is a pHEMT transistor with a short circuit of grid and drain.

5. A high power rejection ratio and low temperature coefficient biasing circuit as in claim 3 wherein: the diode D1 is a Schottky diode, the terminal V _DD is a connection terminal of the power supply voltage V _DD, and when the power supply voltage V _DD changes, the Schottky diode biased forward clamps, the potential between R1 and R2 is clamped to a relatively fixed voltage value V1, and the reference current

6. The high power rejection ratio and low temperature coefficient biasing circuit of claim 5, wherein: the voltage V _GS is the gate-source voltage of pHEMT transistor M1.