CN220872896U - Low-power consumption power management system - Google Patents

Low-power consumption power management system Download PDF

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Publication number
CN220872896U
CN220872896U CN202322417919.8U CN202322417919U CN220872896U CN 220872896 U CN220872896 U CN 220872896U CN 202322417919 U CN202322417919 U CN 202322417919U CN 220872896 U CN220872896 U CN 220872896U
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switching tube
resistor
control
control unit
management system
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CN202322417919.8U
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代礼超
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Jiangsu Dartek Technology Co Ltd
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Jiangsu Dartek Technology Co Ltd
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Abstract

The utility model discloses a low-power consumption power management system, which comprises: the first control unit is used for receiving an access signal of external equipment and generating a first control signal; the switch unit is connected with the first control unit; the singlechip is connected with a power supply through a switch unit; the second control unit is connected with the switch unit and the singlechip, and generates a second control signal for starting the switch unit based on the characterization signal. According to the low-power consumption power management system, when external equipment is just connected to the system, the first control unit controls the switch unit to be turned on so that the singlechip is electrified, when an access signal is not generated after the external equipment is connected to the system, the second control unit is controlled to be turned on by the singlechip so as to keep the switch unit on for achieving the purpose of self-locking, and when the external equipment is removed, the second control unit is turned off by the singlechip so as to turn off the switch unit, so that the system enters the absolute low-power consumption.

Description

Low-power consumption power management system
Technical Field
The present utility model relates to the field of power management, and more particularly, to a low power consumption power management system.
Background
In the existing power management, the scheme is adopted to enable the singlechip to enter a low-power mode to reduce the system power consumption when the singlechip is not in operation, and the scheme has the defects that the singlechip enters the low-power mode but the power consumption still exists, and the scheme has higher requirements on the configuration of the singlechip, so that the code quantity and the memory space are increased.
The information disclosed in this background section is only for enhancement of understanding of the general background of the utility model and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person of ordinary skill in the art.
Disclosure of utility model
The utility model aims to provide a low-power-consumption power management system which can further reduce the power consumption of the system.
To achieve the above object, an embodiment of the present utility model provides a low power consumption power management system, including: the device comprises a first control unit, a switch unit, a singlechip and a second control unit.
The first control unit is used for receiving an access signal of external equipment and generating a first control signal; the switch unit is connected with the first control unit and is used for being started under the control of the first control signal; the singlechip is connected with the power supply through the switch unit, is communicated with the power supply when the switch unit is turned on, and is used for detecting the access of the external equipment and generating a characterization signal for characterizing whether the external equipment is accessed or not; the second control unit is connected with the switch unit and the singlechip, and generates a second control signal for replacing the first control signal to start the switch unit based on the characterization signal.
In one or more embodiments of the present utility model, the first control unit includes a first switching tube and a first resistor, where a control end of the first switching tube is used to receive an access signal of an external device, a first end of the first switching tube is connected to the switching unit, a second end of the first switching tube is connected to ground, a first end of the first resistor is connected to a control end of the first switching tube, and a second end of the first resistor is connected to a second end of the first switching tube.
In one or more embodiments of the present utility model, the power management system further includes a first capacitor and a second resistor connected in series to transmit an access signal of an external device to the first control unit.
In one or more embodiments of the present utility model, the switching unit includes a second switching tube and a third resistor, where a control end of the second switching tube is connected to the first control unit and the second control unit, a first end of the second switching tube is connected to the single chip microcomputer, a second end of the second switching tube is connected to the power supply, a first end of the third resistor is connected to a second end of the second switching tube, and a second end of the third resistor is connected to a control end of the second switching tube.
In one or more embodiments of the present utility model, the power management system further includes a fourth resistor, a first end of the fourth resistor being connected to the switching unit, and a second end of the fourth resistor being connected to the first control unit and the second control unit.
In one or more embodiments of the present utility model, the second control unit includes a third switching tube and a fifth resistor, where a control end of the third switching tube is connected to the single chip microcomputer, a first end of the third switching tube is connected to the switching unit, a second end of the third switching tube is connected to ground, a first end of the fifth resistor is connected to a control end of the third switching tube, and a second end of the fifth resistor is connected to a second end of the third switching tube.
In one or more embodiments of the utility model, the power management system further comprises a second capacitor and a sixth resistor connected in series to convey the characterization signal to the second control unit.
In one or more embodiments of the present utility model, the power management system further includes a third capacitor, a first end of the third capacitor is connected to a sixth resistor, and a second end of the third capacitor is connected to ground.
In one or more embodiments of the present utility model, a delay module is built in the singlechip to delay outputting the characterization signal.
In one or more embodiments of the present utility model, the power management system further includes a voltage stabilizing module, an input end of the voltage stabilizing module is connected to the switch unit, and an output end of the voltage stabilizing module is connected to the singlechip.
Compared with the prior art, according to the low-power-consumption power management system provided by the embodiment of the utility model, when external equipment is just connected to the system, the first control unit is used for controlling the switch unit to be turned on so as to enable the singlechip to be electrified, when an access signal is not generated after the external equipment is connected to the system, the second control unit is controlled by the singlechip to be turned on so as to keep the switch unit on, the purpose of self-locking is achieved, and when the external equipment is removed, the second control unit is turned off by the singlechip so as to turn off the switch unit, so that the whole system is turned off, and the purpose of enabling the system to enter absolute low power consumption is achieved.
Drawings
Fig. 1 is a schematic circuit diagram of a low power consumption power management system according to an embodiment of the present utility model.
Detailed Description
Specific embodiments of the utility model will be described in detail below with reference to the drawings, but it should be understood that the scope of the utility model is not limited to the specific embodiments.
Throughout the specification and claims, unless explicitly stated otherwise, the term "comprise" or variations thereof such as "comprises" or "comprising", etc. will be understood to include the stated element or component without excluding other elements or components.
The term "coupled" or "connected" in this specification includes both direct and indirect connections. An indirect connection is a connection made through an intermediary, such as an electrically conductive medium, which may have parasitic inductance or parasitic capacitance; indirect connections may also include connections through other active or passive devices, such as through circuits or components such as switches, follower circuits, and the like, that accomplish the same or similar functional objectives. Furthermore, in the present utility model, terms such as "first," "second," and the like, are used primarily to distinguish one technical feature from another, and do not necessarily require or imply a certain actual relationship, number or order between the technical features.
As shown in fig. 1, a low power consumption power management system includes: the device comprises a first control unit 10, a switch unit 20, a voltage stabilizing module 30, a singlechip 40 and a second control unit 50.
When the external device is connected to the power management system, the external device will send out an access signal, and the first control unit 10 is configured to receive the access signal of the external device and generate a first control signal.
The switch unit 20 is connected to the first control unit 10, and the switch unit 20 is configured to be turned on under the control of the first control signal. The singlechip 40 is connected with the power supply E through the switch unit 20, the singlechip 40 is communicated with the power supply E when the switch unit 20 is turned on, and the singlechip 40 is used for detecting the access of the external equipment and generating a characterization signal for characterizing whether the external equipment is accessed. In one embodiment, when the external device is connected to the power management system, the switch unit 20 is turned on, the singlechip 40 is powered on to detect the connection of the external device, and the power supply E is a battery pack.
The voltage stabilizing module 30 is connected between the switch unit 20 and the singlechip 40, the input end of the voltage stabilizing module 30 is connected with the switch unit 20, the output end of the voltage stabilizing module 30 is connected with the singlechip 40, and the voltage stabilizing module 30 is used for converting input voltage to provide adaptive voltage for the singlechip 40.
The second control unit 50 is connected to the switch unit 20 and the singlechip 40, the second control unit 50 generates a second control signal for replacing the first control signal to turn on the switch unit 20 based on the characterization signal, when the external device is disconnected from the power management system, the singlechip 40 does not output the characterization signal, the second control unit 50 does not output the second control signal any more, and the switch unit 20 is turned off.
Specifically, the first control unit 10 includes a first switching tube Q1 and a first resistor R1. In addition, the power management system further includes a first capacitor C1 and a second resistor R2, where the first capacitor C1 and the second resistor R2 are connected in series to transmit an access signal of an external device to the first control unit 10.
In an embodiment, a first end of the first capacitor C1 is configured to receive an access signal of an external device, a second end of the first capacitor C1 is connected to a first end of the second resistor R2, a second end of the second resistor R2 is connected to a control end of the first switch tube Q1, the control end of the first switch tube Q1 is configured to receive the access signal of the external device flowing through the first capacitor C1 and the second resistor R2, the first end of the first switch tube Q1 is connected to the switch unit 20, the second end of the first switch tube Q1 is connected to the ground GND, the first end of the first resistor R1 is connected to the control end of the first switch tube Q1, and the second end of the first resistor R1 is connected to the second end of the first switch tube Q1. The first capacitor C1 is used for filtering an access signal of an external device, and the second resistor R2 is a current limiting resistor.
In an embodiment, the first switching tube Q1 is an N-channel MOS tube, the control end of the first switching tube Q1 is a gate, the first end of the first switching tube Q1 is a drain, and the second end of the first switching tube Q1 is a source. When the control end of the first switching tube Q1 receives the high level signal, the first switching tube Q1 is turned on to generate a first control signal, and the first control signal is a low level signal. In other embodiments, the first switching tube Q1 may be an NPN transistor, or the first switching tube Q1 may be a P-channel MOS transistor or a PNP transistor, and the connection circuit of the first switching tube Q1 needs to be adaptively changed.
As shown in fig. 1, the switching unit 20 includes a second switching tube Q2 and a third resistor R3, and the power management system further includes a fourth resistor R4, a first end of the fourth resistor R4 is connected to the switching unit 20, and a second end of the fourth resistor R4 is connected to the first control unit 10 and the second control unit 50.
In an embodiment, the control end of the second switching tube Q2 is connected to the first end of the first switching tube Q1 through the fourth resistor R4, specifically, the control end of the second switching tube Q2 is connected to the first end of the fourth resistor R4, the second end of the fourth resistor R4 is connected to the first end of the first switching tube Q1 of the first control unit 10, the first end of the second switching tube Q2 is connected to the input end of the voltage stabilizing module 30, the output end of the voltage stabilizing module 30 is connected to the single chip microcomputer 40, and the second end of the second switching tube Q2 is connected to the power source E. The first end of the third resistor R3 is connected with the second end of the second switching tube Q2, and the second end of the third resistor R3 is connected with the control end of the second switching tube Q2. The fourth resistor R4 is a current limiting resistor.
In an embodiment, the second switching tube Q2 is a P-channel MOS tube, the control end of the second switching tube Q2 is a gate, the first end of the second switching tube Q2 is a drain, and the second end of the second switching tube Q2 is a source. When the control end of the second switching tube Q2 receives the low-level signal, the second switching tube Q2 is conducted so that the power supply E, the voltage stabilizing module 30 and the singlechip 40 are communicated, and the singlechip 40 is electrified. In other embodiments, the second switching tube Q2 may be a PNP-type triode, or the first switching tube Q1 may be an N-channel MOS tube or an NPN-type triode, and the connection circuit of the second switching tube Q2 needs to be adaptively changed.
As shown in fig. 1, the second control unit 50 includes a third switching tube Q3 and a fifth resistor R5, and the power management system further includes a second capacitor C2 and a sixth resistor R6, where the second capacitor C2 and the sixth resistor R6 are connected in series to transmit the characterization signal to the second control unit 50.
In an embodiment, the control end of the third switching tube Q3 is connected to the singlechip 40 through the second capacitor C2 and the sixth resistor R6, specifically, the control end of the third switching tube Q3 is connected to the first end of the sixth resistor R6, the second end of the sixth resistor R6 is connected to the first end of the second capacitor C2, and the second end of the second capacitor C2 is connected to the singlechip. The first end of the third switching tube Q3 is connected to the switching unit 20 through a fourth resistor R4, and specifically, the first end of the third switching tube Q3 is connected to the second end of the fourth resistor R4. The second end of the third switch is connected with the ground GND, the first end of the fifth resistor R5 is connected with the control end of the third switch tube Q3, and the second end of the fifth resistor R5 is connected with the second end of the third switch tube Q3. The second capacitor C2 is used for filtering the characterization signal, and the sixth resistor R6 is a current limiting resistor.
In an embodiment, the third switching tube Q3 is an N-channel MOS tube, the control end of the third switching tube Q3 is a gate, the first end of the third switching tube Q3 is a drain, and the second end of the third switching tube Q3 is a source. When the control end of the third switching tube Q3 receives the high level signal, the third switching tube Q3 is turned on to generate a second control signal, and the second control signal is a low level signal. In other embodiments, the third switching tube Q3 may be an NPN transistor, or the third switching tube Q3 may be a P-channel MOS transistor or a PNP transistor, and the connection circuit of the third switching tube Q3 needs to be adaptively changed.
In an embodiment, the power management system further includes a third capacitor C3, a first end of the third capacitor C3 is connected to the second end of the sixth resistor R6, and a second end of the third capacitor C3 is connected to the ground GND. The third capacitor C3 plays a role in delay, so that when the singlechip 40 does not output the characterization signal, the characterization signal does not disappear immediately, but disappears after delay, which also represents that the third switching tube Q3 is turned off after a period of delay. In other embodiments, a delay module is built into the singlechip 40 to delay outputting the characterization signal.
When the external device is connected to the power management system, the external device sends out an access signal, and when the grid electrode of the first switching tube Q1 receives the access signal, the first end and the second end of the first switching tube Q1 are conducted. At this time, the gate of the second switching tube Q2 is connected to the ground GND through the fourth resistor R4 and the first switching tube Q1, the second end and the first end of the second switching tube Q2 are turned on, and the power source E supplies power to the singlechip 40 through the turned-on second switching tube Q2 and the voltage stabilizing module 30. After the singlechip 40 is powered on, the external equipment is detected and a characterization signal is output to the control end of the third switching tube Q3, the first end and the second end of the third switching tube Q3 are conducted, and the grid electrode of the second switching tube Q2 is communicated with the ground GND through the fourth resistor R4 and the third switching tube Q3, so that the second switching tube Q2 is kept continuously conducted.
After the external equipment is connected to the power management system, an access signal is sent out only in a short time to enable the first switching tube Q1 and the second switching tube Q2 to be conducted, and when the access signal is stopped being sent out, the third switching tube Q3 is controlled to be conducted after the power is supplied through the singlechip 40, so that the second switching tube Q2 is continuously conducted to form self-locking. After the external device is removed, the singlechip 40 cannot detect the external device and does not generate a characterization signal any more, and after a period of time delay, the third switching tube Q3 is turned off to turn off the second switching tube Q2, so that the whole system is powered off and enters absolute low power consumption.
The foregoing descriptions of specific exemplary embodiments of the present utility model are presented for purposes of illustration and description. It is not intended to limit the utility model to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teachings or may be acquired from other forms, structures, arrangements, proportions, and with other components, materials and parts. The exemplary embodiments were chosen and described in order to explain the principles of the utility model and its practical application to thereby enable others skilled in the art to make and utilize the utility model in various exemplary embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the utility model be defined by the claims and their equivalents.

Claims (10)

1. A low power consumption power management system, comprising:
The first control unit is used for receiving an access signal of external equipment and generating a first control signal;
The switch unit is connected with the first control unit and is used for being started under the control of the first control signal;
The single chip microcomputer is connected with the power supply through the switch unit, is communicated with the power supply when the switch unit is turned on, and is used for detecting the access of the external equipment and generating a characterization signal for characterizing whether the external equipment is accessed or not; and
The second control unit is connected with the switch unit and the singlechip and is used for replacing the first control signal to start the second control signal of the switch unit based on the characterization signal.
2. The low power consumption power management system of claim 1, wherein the first control unit comprises a first switching tube and a first resistor, a control end of the first switching tube is used for receiving an access signal of an external device, a first end of the first switching tube is connected with the switching unit, a second end of the first switching tube is connected with ground, a first end of the first resistor is connected with a control end of the first switching tube, and a second end of the first resistor is connected with a second end of the first switching tube.
3. The low power consumption power management system of claim 1, further comprising a first capacitor and a second resistor connected in series to transmit an access signal of an external device to the first control unit.
4. The low power consumption power management system of claim 1, wherein the switching unit comprises a second switching tube and a third resistor, a control end of the second switching tube is connected with the first control unit and the second control unit, a first end of the second switching tube is connected with the single chip microcomputer, a second end of the second switching tube is connected with the power supply, a first end of the third resistor is connected with a second end of the second switching tube, and a second end of the third resistor is connected with a control end of the second switching tube.
5. The low power consumption power management system of claim 1, further comprising a fourth resistor, a first terminal of the fourth resistor being coupled to the switching unit, and a second terminal of the fourth resistor being coupled to the first control unit and the second control unit.
6. The low power consumption power management system of claim 1, wherein the second control unit comprises a third switching tube and a fifth resistor, a control end of the third switching tube is connected with the single chip microcomputer, a first end of the third switching tube is connected with the switching unit, a second end of the third switching tube is connected with the ground, a first end of the fifth resistor is connected with the control end of the third switching tube, and a second end of the fifth resistor is connected with the second end of the third switching tube.
7. The low power consumption power management system of claim 1, further comprising a second capacitor and a sixth resistor connected in series to deliver the characterization signal to the second control unit.
8. The low power consumption power management system of claim 7, further comprising a third capacitor, a first terminal of the third capacitor connected to a sixth resistor, and a second terminal of the third capacitor connected to ground.
9. The low power consumption power management system of claim 1, wherein the single chip microcomputer is embedded with a delay module to delay outputting the characterization signal.
10. The low power consumption power management system of claim 1, further comprising a voltage stabilizing module, wherein an input end of the voltage stabilizing module is connected to the switch unit, and an output end of the voltage stabilizing module is connected to the single chip microcomputer.
CN202322417919.8U 2023-09-06 2023-09-06 Low-power consumption power management system Active CN220872896U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202322417919.8U CN220872896U (en) 2023-09-06 2023-09-06 Low-power consumption power management system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202322417919.8U CN220872896U (en) 2023-09-06 2023-09-06 Low-power consumption power management system

Publications (1)

Publication Number Publication Date
CN220872896U true CN220872896U (en) 2024-04-30

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Application Number Title Priority Date Filing Date
CN202322417919.8U Active CN220872896U (en) 2023-09-06 2023-09-06 Low-power consumption power management system

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