CN220820522U - LDO circuit suitable for power supply of radio frequency power amplifier chip - Google Patents
LDO circuit suitable for power supply of radio frequency power amplifier chip Download PDFInfo
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- CN220820522U CN220820522U CN202322229526.4U CN202322229526U CN220820522U CN 220820522 U CN220820522 U CN 220820522U CN 202322229526 U CN202322229526 U CN 202322229526U CN 220820522 U CN220820522 U CN 220820522U
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Abstract
The utility model relates to the technical field of radio frequency amplifiers, in particular to an LDO circuit suitable for power supply of a radio frequency power amplifier chip, which comprises: the positive voltage power supply circuit is connected to the drain electrode of the radio frequency power amplifier chip, the negative voltage power supply circuit is connected to the grid electrode of the radio frequency power amplifier chip, and the negative voltage power supply circuit supplies power to the radio frequency power amplifier chip in preference to the positive voltage power supply circuit. The LDO circuit suitable for supplying power to the radio frequency power amplification chip disclosed by the utility model has the advantages that the function of adding the gate voltage VGS firstly when supplying power to the power amplification chip and then adding the drain voltage VD after detecting the gate voltage without errors is realized, so that the problem of module damage caused by wrong power-on sequence when an engineer uses the power amplification module can be avoided.
Description
Technical Field
The utility model relates to the technical field of radio frequency amplifiers, in particular to an LDO circuit suitable for power supply of a radio frequency power amplifier chip.
Background
The solid-state radio frequency power amplifier (power amplifier) is a core component of a radio frequency front end transmitting path, and has the functions of amplifying a radio frequency signal with low power to obtain enough radio frequency output power, and then feeding the radio frequency output power to an antenna to radiate, so that higher communication quality, stronger battery endurance and longer communication distance are realized, and the stability and strength of a communication signal are directly determined by the performance of the radio frequency power amplifier.
With the continuous migration of human wireless communication to the high end of the electromagnetic spectrum, the solid-state radio frequency power amplifier is increasingly applied to high-frequency test instruments and test systems, and is widely applied to radar, communication, navigation, satellite communication, electronic countermeasure, aerospace and other systems.
In the design process of the power amplifier, the power amplifier chip is a relatively expensive device in the radio frequency microwave circuit, the working voltage and the working current of the power amplifier chip are generally large, the power amplifier chip is easily damaged due to improper operation, and the important point is the power-on sequence of the power amplifier chip. The power amplifier has the advantages that the power amplifier tube is powered on, namely, the power amplifier tube is burnt out, and the power amplifier tube is of a field effect tube type, and belongs to a voltage control current type, as shown in fig. 1, the magnitude of drain current IDS depends on the magnitude of gate voltage VGS, and when the power amplifier is powered on, if drain voltage VD precedes gate voltage VGS, a proper static working point is not regulated by the gate voltage, and an accident that the field effect tube is burnt out due to overlarge drain current IDS occurs.
Disclosure of utility model
The utility model aims to solve the technical problems that: the power amplification chip aims to solve the technical problem that in the prior art, when power is supplied to the power amplification chip, the power amplification chip is easy to burn due to wrong power-on sequence. The utility model provides an LDO circuit suitable for supplying power to a radio frequency power amplification chip, which realizes the function of adding a gate voltage VGS when the power amplification chip is supplied with power, detecting the gate voltage without error and then adding a drain voltage VD, and can avoid the problem of module damage caused by wrong power-up sequence when an engineer uses a power amplification module. The technical scheme adopted for solving the technical problems is as follows: an LDO circuit suitable for power supply of a radio frequency power amplifier chip, comprising:
The positive voltage power supply circuit is connected to the drain electrode of the radio frequency power amplification chip, the negative voltage power supply circuit is connected to the grid electrode of the radio frequency power amplification chip, and the negative voltage power supply circuit supplies power to the radio frequency power amplification chip in preference to the positive voltage power supply circuit.
Further, the positive voltage power supply circuit adopts an LT1764A chip.
Further, let LT1764A chip be U2, the first pin, the second pin, the sixteenth pin and the seventeenth pin of U2 all ground, the tenth pin, the twelfth pin, the thirteenth pin and the fourteenth pin of U2 connect external power source V1, the seventh pin, the eighth pin and the ninth pin of U2 all ground and connect capacitor C5's one end, capacitor C5's the other end inserts external power source V1, the sixth pin of U2 connects resistor R1's one end and resistor R2's one end, resistor R1's the other end connects U2's ninth pin, the one end and the other end of resistor R2 of capacitor C6 are connected to the third pin, fourth pin and fifth pin and output voltage V2, capacitor C6's the other end ground.
Further, the output voltage V2 is connected to one end of the resistor R3 and the source of the PMOS transistor Q1, the other end of the resistor R3 is connected to the gate of the PMOS transistor Q1, and the drain of the PMOS transistor Q1 outputs the voltage V3, which is connected to the drain of the rf power amplifier chip through the output voltage V3.
Further, the chip model of the PMOS tube Q1 is FDMA291P.
Further, the negative-pressure power supply circuit adopts an LTC1261 chip.
Further, let LT1764A chip be U1, the first pin of U1 inserts output voltage V2, the third pin of U1 is connected through electric capacity C2 to the second pin of U1, the fourth pin of U1 is grounded and connect electric capacity C1's one end, output signal V2 is connected to the other end of electric capacity C1, the one end and the one end of resistance R5 of the fifth pin connection resistance R4 of U1, the fourth pin of resistance R5 is connected to U1, one end and the one end of electric capacity C4 of electric capacity C3 are grounded, the sixth pin of resistance R4 is connected to the other end of U1, the other end of electric capacity C3 and the other end of electric capacity C4, electric capacity V4 is output to the other end of electric capacity C4, output voltage V4 connects the grid of radio frequency power amplifier chip, the grid of positive voltage power supply circuit's PMOS pipe Q1 is connected to the seventh pin of U1, the eighth pin of U1 is grounded.
The LDO circuit suitable for power supply of the radio frequency power amplification chip has the advantages that the function of adding the grid voltage VGS firstly when the power amplification chip is powered on and then adding the drain voltage VD after detecting the grid voltage without errors is achieved, and the problem that an engineer damages the power amplification module due to wrong power-on sequence can be avoided.
Drawings
The utility model will be further described with reference to the drawings and examples.
FIG. 1 is a schematic diagram of a conventional power amplifying chip package;
FIG. 2 is a positive voltage power supply circuit diagram of an LDO circuit suitable for supplying power to a radio frequency power amplifier chip;
FIG. 3 is a negative voltage power supply circuit diagram of the LDO circuit suitable for supplying power to the radio frequency power amplifier chip;
Fig. 4 is a schematic diagram of a power circuit of the present utility model for powering a power amplifying chip.
Detailed Description
The utility model will now be described in further detail with reference to the accompanying drawings. The drawings are simplified schematic representations which merely illustrate the basic structure of the utility model and therefore show only the structures which are relevant to the utility model.
In the description of the present utility model, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present utility model and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present utility model. Furthermore, features defining "first", "second" may include one or more such features, either explicitly or implicitly. In the description of the present utility model, unless otherwise indicated, the meaning of "a plurality" is two or more.
In the description of the present utility model, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present utility model will be understood in specific cases by those of ordinary skill in the art.
As shown in fig. 2 to 4, which are preferred embodiments of the present utility model, an LDO circuit suitable for supplying power to a radio frequency power amplifier chip, comprises: the positive voltage power supply circuit is connected to the drain electrode of the radio frequency power amplifier chip, the negative voltage power supply circuit is connected to the grid electrode of the radio frequency power amplifier chip, and the negative voltage power supply circuit supplies power to the radio frequency power amplifier chip in preference to the positive voltage power supply circuit.
As shown in fig. 2, the positive voltage power supply circuit adopts an LT1764A chip, the LT1764A chip is set as U2, the first pin, the second pin, the sixteenth pin and the seventeenth pin of the U2 are all grounded, the tenth pin, the twelfth pin, the thirteenth pin and the fourteenth pin of the U2 are all grounded and connected with one end of a capacitor C5, the other end of the capacitor C5 is connected to the external power supply V1, the sixth pin of the U2 is connected with one end of a resistor R1 and one end of a resistor R2, the other end of the resistor R1 is connected with the ninth pin of the U2, the third pin, the fourth pin and the fifth pin of the U2 are connected with one end of a capacitor C6 and the other end of the resistor R2 and output a voltage V2, and the other end of the capacitor C6 is grounded.
The output voltage V2 is connected with one end of the resistor R3 and the source electrode of the PMOS tube Q1, the other end of the resistor R3 is connected with the grid electrode of the PMOS tube Q1, the drain electrode of the PMOS tube Q1 outputs the voltage V3, the drain electrode of the radio frequency power amplifier chip is connected through the output voltage V3, and the chip model of the PMOS tube Q1 is FDMA291P.
The negative-pressure power supply circuit adopts an LTC1261 chip, the LT1764A chip is U1, a first pin of the U1 is connected with an output voltage V2, a second pin of the U1 is connected with a third pin of the U1 through a capacitor C2, a fourth pin of the U1 is grounded and connected with one end of the capacitor C1, the other end of the capacitor C1 is connected with an output signal V2, a fifth pin of the U1 is connected with one end of a resistor R4 and one end of a resistor R5, the other end of the resistor R5 is connected with the fourth pin of the U1, one end of the capacitor C3 and one end of the capacitor C4 and grounded, the other end of the resistor R4 is connected with a sixth pin of the U1, the other end of the capacitor C3 and the other end of the capacitor C4, the other end of the capacitor C4 is connected with an output voltage V4, the output voltage V4 is connected with a grid of the radio-frequency power amplifier chip, a seventh pin of the U1 is connected with a grid of a PMOS tube Q1 of the positive-pressure power supply circuit, and an eighth pin of the U1 is grounded.
The positive voltage power supply circuit part is powered by an LT1764A chip, an external power supply V1 enters the chip through a twelfth pin, a thirteenth pin and a fourteenth pin of U2, ideal voltage is obtained after the voltage is reduced by the chip, positive voltage V2 is output by a third pin, a fourth pin and a fifth pin of U2, a capacitor C5 and a capacitor C6 are filter capacitors at the input side and the output side respectively, and the capacitance is 10uF. For different power amplification chips, the positive voltage power supply required by the chips is different, so that the output voltage V2 of the chips can be controlled through a sixth pin of U2, a resistor R1 and a resistor R2, and the positive voltage required by the power amplification chips is obtained by calculating by using the formula v2=1.21V (R1/R2) + (IADJ) and changing the resistance values of the resistor R1 and the resistor R2.
The negative voltage power supply circuit part adopts an LTC1261 chip for power supply, the positive voltage power supply circuit part outputs voltage V2 as input power supply of the LTC1261, after chip conversion, negative voltage V4 is output as gate voltage VGS of the power amplifier, the capacitor C1 is a filter capacitor at the input side, the capacitance value is 10uF, the capacitor C3 and the capacitor C4 are filter capacitors at the output side, and the capacitance values are 4.7uF and 10uF respectively. For power amplifying chips, this is usually achieved by varying the value of the output voltage V4 in order to obtain different output powers. The output voltage V4 of the chip is controlled by the fifth pin of U1, the resistor R4 and the resistor R5, the negative pressure required by the power amplification chip is obtained by changing the resistance values of R4 and R5 by calculating the formula V4= -1.24V (1+R4/R5).
The drain voltage V2 and the gate voltage V4 required by the power amplification chip are obtained through the positive and negative part circuits, and in the actual use process, the power-on sequence needs to be considered at all times, so that the chip damage caused by the power-on sequence error is avoided. Therefore, the PMOS tube Q1 is further added as a switch at the rear stage of the output voltage V2 of the positive voltage power supply circuit part, so as to control the on-off of the positive voltage source output. The on and off of the PMOS tube Q1 are controlled by the level of the control signal, the PMOS tube Q1 is turned off when the control signal is in a high level, the PMOS tube Q1 is turned on when the control signal is in a low level, and meanwhile, the seventh pin of the U1 is monitored by matching with the output voltage of the negative-pressure power supply circuit to obtain a power-on sequence of negative before positive.
The specific principle is that when the output voltage V4 of the negative pressure chip LTC1261 is detected to be normal, the seventh pin can send a control signal, usually a low-level signal, to control the PMOS tube FDMA291P to be conducted, and the output voltage V2 of the positive pressure circuit is changed into V3 after passing through the PMOS tube to supply power to the drain electrode of the power amplification chip; when the abnormal value of the output voltage V4 of the negative-pressure chip LTC1261 is detected, the seventh pin can send a control signal, usually a high-level signal, to control the PMOS tube FDMA291P to be turned off, the output voltage V2 of the positive-pressure circuit can not be changed into V3 through the PMOS tube to supply power to the drain electrode of the power amplification chip, so that the order of firstly negative and then positive when the power amplification chip is supplied with power is realized, and the chip damage is avoided.
The LDO circuit suitable for supplying power to the radio frequency power amplification chip disclosed by the utility model has the advantages that the function of adding the gate voltage VGS firstly when supplying power to the power amplification chip and then adding the drain voltage VD after detecting the gate voltage without errors is realized, so that the problem of module damage caused by wrong power-on sequence when an engineer uses the power amplification module can be avoided.
With the above-described preferred embodiments according to the present utility model as an illustration, the above-described descriptions can be used by persons skilled in the relevant art to make various changes and modifications without departing from the scope of the technical idea of the present utility model. The technical scope of the present utility model is not limited to the description, but must be determined as the scope of the claims.
Claims (7)
1. An LDO circuit suitable for power supply of a radio frequency power amplifier chip, comprising:
The positive voltage power supply circuit is connected to the drain electrode of the radio frequency power amplification chip, the negative voltage power supply circuit is connected to the grid electrode of the radio frequency power amplification chip, and the negative voltage power supply circuit supplies power to the radio frequency power amplification chip in preference to the positive voltage power supply circuit.
2. The LDO circuit for powering a radio frequency power amplifier chip as recited in claim 1, wherein the positive voltage power supply circuit employs an LT1764A chip.
3. The LDO circuit of claim 2, wherein the LT1764A chip is set as U2, the first, second, sixteenth and seventeenth pins of U2 are all grounded, the tenth, twelfth, thirteenth and fourteenth pins of U2 are all grounded and connected to one end of the capacitor C5, the other end of the capacitor C5 is connected to the external power V1, the sixth pin of U2 is connected to one end of the resistor R1 and one end of the resistor R2, the other end of the resistor R1 is connected to the ninth pin of U2, the third, fourth and fifth pins of U2 are connected to one end of the capacitor C6 and the other end of the resistor R2 and output the voltage V2, and the other end of the capacitor C6 is grounded.
4. The LDO circuit for supplying power to a radio frequency power amplifier chip as set forth in claim 3, wherein the output voltage V2 is connected to one end of the resistor R3 and the source of the PMOS transistor Q1, the other end of the resistor R3 is connected to the gate of the PMOS transistor Q1, and the drain of the PMOS transistor Q1 outputs the voltage V3, which is connected to the drain of the radio frequency power amplifier chip via the output voltage V3.
5. The LDO circuit for powering a radio frequency power amplifier chip as claimed in claim 4, wherein the chip type of the PMOS transistor Q1 is FDMA291P.
6. The LDO circuit for powering a radio frequency power amplifier chip as recited in claim 5, wherein the negative voltage power supply circuit employs an LTC1261 chip.
7. The LDO circuit for powering a radio frequency power amplifier chip as claimed in claim 6, wherein the LT1764A chip is set as U1, the first pin of U1 is connected to an output voltage V2, the second pin of U1 is connected to the third pin of U1 through a capacitor C2, the fourth pin of U1 is grounded and connected to one end of the capacitor C1, the other end of the capacitor C1 is connected to an output signal V2, the fifth pin of U1 is connected to one end of a resistor R4 and one end of a resistor R5, the other end of the resistor R5 is connected to the fourth pin of U1, one end of the capacitor C3 and one end of the capacitor C4 are grounded, the other end of the resistor R4 is connected to the sixth pin of U1, the other end of the capacitor C3 and the other end of the capacitor C4, the other end of the capacitor C4 is connected to the gate of the radio frequency power amplifier chip, the seventh pin of U1 is connected to the gate of a PMOS tube Q1 of the positive voltage power supply circuit, and the eighth pin of U1 is grounded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322229526.4U CN220820522U (en) | 2023-08-17 | 2023-08-17 | LDO circuit suitable for power supply of radio frequency power amplifier chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322229526.4U CN220820522U (en) | 2023-08-17 | 2023-08-17 | LDO circuit suitable for power supply of radio frequency power amplifier chip |
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| Publication Number | Publication Date |
|---|---|
| CN220820522U true CN220820522U (en) | 2024-04-19 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202322229526.4U Active CN220820522U (en) | 2023-08-17 | 2023-08-17 | LDO circuit suitable for power supply of radio frequency power amplifier chip |
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| Country | Link |
|---|---|
| CN (1) | CN220820522U (en) |
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2023
- 2023-08-17 CN CN202322229526.4U patent/CN220820522U/en active Active
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