CN220798258U - Reference frequency locking device and satellite terminal equipment - Google Patents
Reference frequency locking device and satellite terminal equipment Download PDFInfo
- Publication number
- CN220798258U CN220798258U CN202322485091.XU CN202322485091U CN220798258U CN 220798258 U CN220798258 U CN 220798258U CN 202322485091 U CN202322485091 U CN 202322485091U CN 220798258 U CN220798258 U CN 220798258U
- Authority
- CN
- China
- Prior art keywords
- signal
- reference frequency
- conversion module
- band
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000006243 chemical reaction Methods 0.000 claims abstract description 52
- 238000001914 filtration Methods 0.000 claims abstract description 9
- 239000013078 crystal Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 6
- 230000008569 process Effects 0.000 abstract description 6
- 238000004891 communication Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 238000001514 detection method Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 229920006395 saturated elastomer Polymers 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Landscapes
- Radio Relay Systems (AREA)
Abstract
The utility model discloses a reference frequency locking device and satellite terminal equipment, wherein the reference frequency locking device comprises a waveform conversion module, a band-pass filter, a power amplifier and a phase-locked loop, wherein the waveform conversion module converts an input signal into a first signal, the band-pass filter is used for filtering the first signal to obtain a second signal, the second signal is amplified to obtain a third signal, and finally the phase-locked loop locks the frequency of the third signal. The reference frequency locking device provided by the embodiment of the utility model can lock the signal to the required reference frequency without delay, does not need complex logic judgment in the process, has low delay, high reliability and low cost, and solves the technical problems of complex implementation logic, high cost and high time delay of the frequency locking device in the prior art.
Description
Technical Field
The present utility model relates to the field of communications, and in particular, to a reference frequency locking device and a satellite terminal device.
Background
The reference frequency of the traditional satellite terminal equipment is 10MHz, and along with the development of Ka frequency band high-throughput satellites, the Ka frequency band satellite terminal is increasingly applied, but as the local oscillation frequency of the Ka frequency band is 2.2 times of the Ku frequency band, under the system with the same performance, the satellite terminal of the Ka frequency band transmits phase noise to be deteriorated by at least 6.9dB. In order to solve this problem, a satellite terminal device with a reference frequency of 50MHz has been developed, and the reference frequency of 50MHz can effectively optimize the phase noise of a Ka band satellite device, but there are a large number of satellite communication systems with only 10MHz reference frequency or only 50MHz reference frequency on the market, so that the newly developed satellite terminal device must adapt to the original system reference frequency requirements, that is, can meet both 10MHz and 50MHz.
To achieve this, it is generally necessary to provide a frequency locking device on a satellite terminal device, however, the frequency locking device in the prior art has complex logic, high cost and high time.
Disclosure of utility model
The utility model provides a reference frequency locking device and satellite terminal equipment, which are used for solving the technical problems of complex implementation logic, high cost and higher time delay of the frequency locking device in the prior art.
In a first aspect, an embodiment of the present utility model provides a reference frequency locking apparatus, including: the device comprises a waveform conversion module, a band-pass filter, a power amplifier and a phase-locked loop;
the output end of the waveform conversion module is connected with the input end of the band-pass filter, the input end of the waveform conversion module is used for receiving an input signal, and the waveform conversion module is used for converting the input signal into a first signal;
the output end of the band-pass filter is connected with the input end of the power amplifier, and the band-pass filter is used for filtering the first signal to obtain a second signal;
The output end of the power amplifier is connected with the input end of the phase-locked loop, and the power amplifier is used for amplifying the second signal to obtain a third signal;
the phase-locked loop is used for locking the frequency of the third signal.
Preferably, the input signal is a signal including a reference frequency, and the waveform conversion module is configured to convert the input signal into a square wave signal.
Preferably, the waveform conversion module includes, but is not limited to, any one of a schmitt trigger, an and gate, or a zero-crossing comparator.
Preferably, the input signal is a square wave signal or a sine wave signal, and the reference frequency of the input signal is 10MHz or 50MHz;
When the reference frequency of the input signal is 10MHz, the waveform conversion module is used for converting the input signal into a square wave signal of 10 MHz;
When the reference frequency of the input signal is 50MHz, the waveform conversion module is used for converting the input signal into a square wave signal of 50 MHz.
Preferably, the band-pass filter is configured to filter the first signal, and filter other signals except for the target frequency in the first signal to obtain the second signal.
Preferably, the target frequency is 50MHz.
Preferably, the band-pass filter is a narrow-band crystal filter.
Preferably, the power amplifier is a high gain low power amplifier.
Preferably, the input power range of the power amplifier is-5 dBm to +5dBm.
In a second aspect, an embodiment of the present utility model provides a satellite terminal device, including the reference frequency locking device of the first aspect, and a processor, where the processor is connected to an output end of a phase-locked loop in the frequency locking device.
The embodiment of the utility model provides a reference frequency locking device, which comprises a waveform conversion module, a band-pass filter, a power amplifier and a phase-locked loop, wherein the waveform conversion module converts an input signal into a first signal, the band-pass filter is used for filtering the first signal to obtain a second signal, the second signal is amplified to obtain a third signal, and finally the phase-locked loop locks the frequency of the third signal. The reference frequency locking device provided by the embodiment of the utility model can lock the signal to the required reference frequency without delay, does not need complex logic judgment in the process, has low delay, high reliability and low cost, and solves the technical problems of complex implementation logic, high cost and high time delay of the frequency locking device in the prior art.
Drawings
Fig. 1 is a schematic structural diagram of a frequency locking device in the prior art according to an embodiment of the present utility model.
Fig. 2 is a schematic structural diagram of a frequency locking device according to an embodiment of the present utility model.
Fig. 3 is a schematic working diagram of a frequency locking device according to an embodiment of the present utility model.
Fig. 4 shows signal components of a10 MHz square wave signal in the frequency domain according to an embodiment of the present utility model.
Fig. 5 is a schematic working diagram of another frequency locking device according to an embodiment of the present utility model.
Fig. 6 is a schematic diagram of an operation of an and gate according to an embodiment of the present utility model.
In the figure: the device comprises a waveform conversion module U1, a band-pass filter LB1, a power amplifier PA1 and a phase-locked loop PLL.
Detailed Description
In order to make the technical problems solved by the present utility model, the technical solutions adopted and the technical effects achieved more clear, the technical solutions of the embodiments of the present utility model are described in further detail below, and it is obvious that the described embodiments are only some embodiments of the present utility model, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to fall within the scope of the utility model.
In the description of the present utility model, unless explicitly stated and limited otherwise, the terms "connected," "connected," and "fixed" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present utility model will be understood in specific cases by those of ordinary skill in the art.
In the present utility model, unless expressly stated or limited otherwise, a first feature "above" or "below" a second feature may include both the first and second features being in direct contact, as well as the first and second features not being in direct contact but being in contact with each other through additional features therebetween. Moreover, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is higher in level than the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly under and obliquely below the second feature, or simply means that the first feature is less level than the second feature.
The reference frequency is the frequency of the clock signal, and the reference frequency has the function of enabling the clock signal of the whole satellite communication system to achieve synchronization in frequency and phase and achieving good demodulation effect. In the prior art, in order to enable newly developed satellite terminal equipment to adapt to the original system reference frequency requirement, a frequency locking device needs to be arranged in the satellite terminal equipment, and the structure of the traditional frequency locking device is shown in fig. 1, generally, two filters LB and two detectors J are arranged at an input port of the satellite terminal equipment so as to detect the frequency of a current input signal, then the detectors J transmit detection voltage to an MCU through an AD/DA conversion module, and the MCU configures different data for a phase-locked loop according to the current reference frequency, so that the purpose of local oscillation locking is achieved. However, this design scheme needs to be implemented by providing two band-pass filters, two detection modules and two AD conversion modules, and has complex logic and high manufacturing cost, and it is difficult to achieve phase noise close to theoretical calculation when the same hardware parameters are matched with different reference signals in the prior art. In addition, the design scheme also needs to carry out detection logic judgment on the reference frequency, then carries out configuration programming on the phase-locked loop according to the detection result, and the local oscillator can be accurately locked after the phase-locked loop is successfully configured, so that the time delay is larger, and the design scheme cannot be suitable for part of satellite communication systems requiring quick frequency locking.
In order to solve the above technical problems, an embodiment of the present utility model provides a reference frequency locking device, as shown in fig. 2, and fig. 2 is a schematic structural diagram of the reference frequency locking device according to the embodiment of the present utility model. In fig. 2, the reference frequency locking device includes a waveform conversion module U1, a band-pass filter LB1, a power amplifier PA1, and a phase-locked loop PLL.
The output end of the waveform conversion module U1 is connected with the input end of the band-pass filter LB1, the input end of the waveform conversion module U1 is used for receiving an input signal, and the waveform conversion module U1 is used for converting the input signal into a first signal.
In this embodiment, the reference frequency locking device includes a waveform conversion module U1, where an output end of the waveform conversion module U1 is connected to an input end of the band-pass filter LB1, and an output end of the waveform conversion module U1 is connected to an input end of the band-pass filter LB 1. In this embodiment, the input end of the waveform conversion module U1 is configured to receive an input signal, and the waveform conversion module U1 is configured to convert the input signal into the first signal after receiving the input signal. In one embodiment, the first signal is a square wave signal, and the waveform conversion module U1 is configured to convert the input signal into the square wave signal. For example, when the input signal is a sine wave signal, the waveform conversion module U1 may convert the sine wave signal into a square wave signal, thereby obtaining the first signal.
The output end of the band-pass filter LB1 is connected with the input end of the power amplifier PA1, and the band-pass filter LB1 is used for filtering the first signal to obtain a second signal.
In this embodiment, the output end of the band-pass filter LB1 is connected to the input end of the power amplifier PA1, and after obtaining the first signal, the waveform conversion module U1 transmits the first signal to the band-pass filter LB1, where the band-pass filter LB1 is used to filter the first signal to obtain the second signal. For example, when the reference frequency of the satellite communication system is 50MHz, the band-pass filter LB1 may filter the first signal to remove signals other than 50MHz from the first signal.
The output end of the power amplifier PA1 is connected with the input end of the phase-locked loop PLL, and the power amplifier PA1 is used for amplifying the second signal to obtain a third signal.
The reference frequency locking device further comprises a power amplifier PA1, wherein an output end of the power amplifier PA1 is connected with an input end of the phase-locked loop PLL, the band-pass filter LB1 transmits the second signal to the power amplifier PA1 after obtaining the second signal, and the power amplifier PA1 amplifies the second signal to obtain a third signal. For example, when the second signal is a 50MHz signal, the power amplifier PA1 is used to amplify the 50MHz signal.
The phase-locked loop PLL is used to lock the frequency of the third signal.
The power amplifier PA1 amplifies the second signal to obtain a third signal, and then transmits the third signal to the phase-locked loop PLL, and the phase-locked loop PLL locks the frequency of the third signal. For example, if the frequency of the third signal is 50MHz, the phase-locked loop PLL is used to lock the frequency of the third signal to 50MHz. In one embodiment, the output end of the phase-locked loop PLL is further connected to the processor, and the phase-locked loop PLL may transmit the third signal after frequency locking to the processor, where the processor performs parameter configuration on the 50MHz signal, for example, setting in the software and hardware parameters to perform optimization processing only for 50MHz, for example, using a high phase discrimination frequency, ensuring optimization of phase noise of the system, and so on.
The embodiment of the utility model provides a reference frequency locking device, which comprises a waveform conversion module, a band-pass filter, a power amplifier and a phase-locked loop, wherein the waveform conversion module converts an input signal into a first signal, the band-pass filter is used for filtering the first signal to obtain a second signal, the power amplifier amplifies the second signal to obtain a third signal, and the phase-locked loop locks the frequency of the third signal. The reference frequency locking device provided by the embodiment of the utility model can lock the signal to the required reference frequency without delay, does not need complex logic judgment in the process, has high reliability and low cost, and solves the technical problems of complex implementation logic, high cost and higher time delay of the frequency locking device in the prior art.
On the basis of the above embodiment, the input signal is a signal including a reference frequency, and the waveform conversion module U1 is configured to convert the input signal into a square wave signal.
In one embodiment, the input signal is a signal including a reference frequency, and the waveform conversion module U1 is configured to convert the input signal into a square wave signal. The input signal is a square wave signal or a sine wave signal, the reference frequency of the input signal is 10MHz or 50MHz, and when the reference frequency of the input signal is 10MHz, the waveform conversion module U1 is configured to convert the input signal into a square wave signal of 10 MHz; when the reference frequency of the input signal is 50MHz, the waveform conversion module U1 is configured to convert the input signal into a square wave signal of 50 MHz.
In this embodiment, the waveform conversion module U1 includes, but is not limited to, any one of a schmitt trigger, an and gate, or a zero-crossing comparator. Wherein the schmitt trigger is a comparator circuit comprising positive feedback. For a standard schmitt trigger, when the input voltage is higher than the forward threshold voltage, the output is high; when the input voltage is lower than the negative threshold voltage, the output is low; when the input is between the positive and negative threshold voltages, the output is unchanged, that is, the output is turned from the high level to the low level, or the threshold voltages corresponding to the turning from the low level to the high level are different. The output will change only when there is a sufficient change in the input voltage, and the schmitt trigger is essentially a flip-flop. The schmitt trigger can be used as a waveform shaping circuit and can shape the waveform of an analog signal into a square waveform which can be processed by a digital circuit. AND gates are also known as AND circuits, logical AND circuits. Is the basic logic gate that performs the and operation. There are a plurality of inputs and an output. The output is high only when all inputs are high (logic 1) at the same time, otherwise the output is low (logic 0). The zero-crossing comparator is a comparator with a zero-turning threshold value and is used for detecting whether an input value is zero or not, and the principle is that the comparator is used for comparing two input voltages. For example, one of the two input voltages is a reference voltage Vr, the other is a voltage to be measured Vu, typically Vr is connected from the non-inverting input terminal, and Vu is connected from the inverting input terminal. And outputting a forward or reverse saturated voltage according to the result of comparing the input voltage, and obtaining a measurement result of the voltage to be measured when the reference voltage is known, wherein the zero-crossing comparator is the reference voltage zero.
For example, when the waveform conversion module U1 includes a schmitt trigger, the schmitt trigger may employ 74AHC1G14 of an semiconductor, and under a +5v power supply condition, the corresponding speed is provided for the waveform conversion module U1 to be less than 13nS in a full temperature section, so that the conversion response speed requirement from a sine wave to a square wave signal in the present utility model can be completely satisfied. As shown in fig. 3, when a sine wave signal or a square wave signal with a frequency of 10MHz is input into the schmitt trigger, the 10MHz sine wave signal or the square wave signal can be converted into a square wave signal with a frequency of 10MHz by using the characteristics of the schmitt trigger, and the signal component of the square wave signal with a frequency of 10MHz output by the schmitt trigger in the frequency domain is shown in fig. 4. Similarly, when a sine wave signal or a square wave signal with the frequency of 50MHz is input into the schmitt trigger, the schmitt trigger can convert the sine wave signal or the square wave signal with the frequency of 50MHz into the square wave signal with the frequency of 50MHz, and the specific process is shown in fig. 5.
In addition, when the waveform conversion module U1 includes an and gate, a high level signal may be applied to one input terminal of the and gate, and the input signal may be input to the other input terminal of the and gate, and the input signal may be converted into a square wave signal using the operation characteristics of the and gate, as shown in fig. 6.
On the basis of the above embodiment, the band-pass filter LB1 is configured to filter the first signal, and filter other signals except the target frequency in the first signal to obtain the second signal.
In this embodiment, the band-pass filter LB1 is configured to filter the first signal, and filter other signals except the target frequency in the first signal, so as to obtain the second signal with the target frequency. In one embodiment, the target frequency is 50MHz, that is, the band-pass filter LB1 is used to filter out other signals except 50MHz in the first signal, so as to obtain the second signal.
Specifically, when the input signal of the band pass filter LB1 is a 10MHz square wave signal, the band pass filter LB1 functions to extract the fifth order harmonic (50 MHz in this embodiment) and suppress signals of other frequency components. When the input signal of the band pass filter LB1 is a 50MHz square wave signal, the band pass filter LB1 functions to extract the fundamental frequency component (50 MHz in this embodiment) and suppress signals of other frequency components.
It should be noted that, after the waveform conversion module U1 converts the input signal into the square wave signal, the frequency spectrum component of the square wave signal in the frequency domain represents the frequency distribution and the amplitude of the sine wave frequency component included in the time domain waveform, and the square wave signal with the frequency f can be obtained according to the expansion result of the fourier equation, where the square wave signal is composed of f,3f,5f … … countless sine waves with the frequency of the square wave frequency being odd multiples. By utilizing the characteristic, a 50MHz band-pass filter LB1 is arranged behind the waveform conversion module U1, and a sine wave component with the frequency of 50MHz can be taken out, namely, a second signal obtained after the filtering of the band-pass filter LB1 is a sine wave signal. In addition, in the present embodiment, the band-pass filter LB1 is a narrow-band crystal filter, and for other satellite communication systems with low requirements, the band-pass filter LB1 of the lumped-parameter element may be used.
Based on the above embodiments, the power amplifier PA1 is a high-gain low-power amplifier.
In this embodiment, the power amplifier PA1 is a high-gain low-power amplifier, and the working state of the power amplifier PA1 needs to be set in the class C working state to ensure that the amplitude of the input reference power is stable in the full temperature section. The C-type working state means that the working time of the lean tube is less than half period, and the lean tube is suitable for high-frequency resonance power amplification.
Based on the above embodiments, the input power range of the power amplifier PA1 is-5 dBm to +5dBm.
In the embodiment, the input power range of the high-gain low-power amplifier is-5 dBm to +5dBm, so that the high-gain low-power amplifier is ensured to be in a saturated working state, and multiple harmonics can be excited. Specifically, after 5 subharmonics are excited, the bias resonance point of the high-gain low-power amplifier is set at 50MHz, and the subharmonic power is equivalent to the fundamental wave power, so that signals with the frequency of 50MHz in the subharmonics can be extracted and amplified.
The embodiment of the utility model provides a reference frequency locking device, which comprises a waveform conversion module, a band-pass filter, a power amplifier and a phase-locked loop, wherein the waveform conversion module converts an input signal into a first signal, the band-pass filter is used for filtering the first signal to obtain a second signal, the second signal is amplified to obtain a third signal, and finally the phase-locked loop locks the frequency of the third signal. The reference frequency locking device provided by the embodiment of the utility model can lock the signal to the required reference frequency without delay, does not need complex logic judgment in the process, has high reliability and low cost, and solves the technical problems of complex implementation logic, high cost and higher time delay of the frequency locking device in the prior art. In addition, the power consumption of the device for converting the sine wave into the square wave is at the uA level, and the power consumption is reduced by 50% compared with the prior art. And secondly, the utility model can make the reference frequency locking device be applied to a system with self-adaptive requirements on arbitrary fundamental wave and harmonic reference frequency by changing the frequency band range of the corresponding frequency of the rear-stage band-pass filter, and has wide application range.
In another embodiment, the embodiment of the utility model also provides a satellite terminal device, which comprises the reference frequency locking device and a processor, wherein the processor is connected with the output end of a phase-locked loop in the frequency locking device. The reference frequency locking device comprises a waveform conversion module, a band-pass filter, a power amplifier and a phase-locked loop, wherein the waveform conversion module converts an input signal into a first signal, the band-pass filter is used for filtering the first signal to obtain a second signal, the second signal is amplified to obtain a third signal, and the phase-locked loop locks the frequency of the third signal. The phase-locked loop may then input the frequency-locked third signal into the processor, and the processor may perform parameter configuration on the frequency-locked third signal to implement processing of the third signal. The reference frequency locking device provided by the embodiment of the utility model can lock the signal to the required reference frequency without delay, does not need complex logic judgment in the process, has high reliability and low cost, and solves the technical problems of complex implementation logic, high cost and higher time delay of the frequency locking device in the prior art.
The foregoing embodiments have been provided for the purpose of illustrating the general principles of the present utility model, and are not to be construed as limiting the scope of the utility model. It should be noted that any modifications, equivalent substitutions, improvements, etc. made by those skilled in the art without departing from the spirit and principles of the present utility model are intended to be included in the scope of the present utility model.
Claims (10)
1. A reference frequency locking device, comprising: the device comprises a waveform conversion module, a band-pass filter, a power amplifier and a phase-locked loop;
the output end of the waveform conversion module is connected with the input end of the band-pass filter, the input end of the waveform conversion module is used for receiving an input signal, and the waveform conversion module is used for converting the input signal into a first signal;
The output end of the band-pass filter is connected with the input end of the power amplifier, and the band-pass filter is used for filtering the first signal to obtain a second signal;
The output end of the power amplifier is connected with the input end of the phase-locked loop, and the power amplifier is used for amplifying the second signal to obtain a third signal;
the phase-locked loop is used for locking the frequency of the third signal.
2. A reference frequency locking apparatus as claimed in claim 1, wherein the input signal is a signal comprising a reference frequency, and the waveform conversion module is configured to convert the input signal into a square wave signal.
3. A reference frequency locking arrangement according to claim 2, wherein the waveform conversion module includes, but is not limited to, any one of a schmitt trigger, an and gate or a zero-crossing comparator.
4. A reference frequency locking apparatus according to claim 2, wherein the input signal is a square wave signal or a sine wave signal, and the reference frequency of the input signal is 10MHz or 50MHz;
When the reference frequency of the input signal is 10MHz, the waveform conversion module is used for converting the input signal into a square wave signal of 10 MHz;
When the reference frequency of the input signal is 50MHz, the waveform conversion module is used for converting the input signal into a square wave signal of 50 MHz.
5. A reference frequency locking apparatus as claimed in claim 1, wherein the band pass filter is arranged to filter a first signal, and to filter other signals of the first signal than the target frequency to obtain a second signal.
6. A reference frequency locking apparatus as defined in claim 5, wherein said target frequency is 50MHz.
7. A reference frequency locking arrangement as claimed in claim 5, wherein the band pass filter is a narrow band crystal filter.
8. The reference frequency locking device of claim 1 wherein the power amplifier is a high gain low power amplifier.
9. The reference frequency locking apparatus of claim 8 wherein the power amplifier has an input power in the range of-5 dBm to +5dBm.
10. A satellite terminal device comprising a reference frequency locking arrangement according to any one of claims 1 to 9 and a processor connected to an output of a phase locked loop in the frequency locking arrangement.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322485091.XU CN220798258U (en) | 2023-09-12 | 2023-09-12 | Reference frequency locking device and satellite terminal equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322485091.XU CN220798258U (en) | 2023-09-12 | 2023-09-12 | Reference frequency locking device and satellite terminal equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN220798258U true CN220798258U (en) | 2024-04-16 |
Family
ID=90665528
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202322485091.XU Active CN220798258U (en) | 2023-09-12 | 2023-09-12 | Reference frequency locking device and satellite terminal equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN220798258U (en) |
-
2023
- 2023-09-12 CN CN202322485091.XU patent/CN220798258U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102870328B (en) | There is the PLL charge pump of the coupling to bias node of minimizing | |
| CN109547052B (en) | Ultra-wideband frequency modulation composite transceiver for communication and distance measurement | |
| CN103134983B (en) | Based on Terahertz related detection system and the method for single frequency mixer | |
| CN100386645C (en) | Method of detecting surface flow speed of river lake using radar electric wave and its radar system | |
| KR20160006678A (en) | Logarithmic Amplifier with Universal Demodulation Capabilities | |
| CN104158553B (en) | A kind of phase-locked receive mixing loop | |
| CN220798258U (en) | Reference frequency locking device and satellite terminal equipment | |
| CN205792524U (en) | Radar clock multiplier based on step-recovery diode | |
| Cheng et al. | Reference-less ultra-low-power wake-up receiver with noise suppression | |
| CN101340196B (en) | Multichannel digital detection IF amplifier | |
| CN204392230U (en) | The integrated receiving unit of a kind of 8mm | |
| Zhou et al. | Energy detection technique for ultra-low power high sensitivity wake-up receiver | |
| CN109799386B (en) | Power detector | |
| CN108183876B (en) | FSK signal demodulation and pulse recovery system and method | |
| CN105429632A (en) | Miniature integrated microwave local oscillator signal generator | |
| CN218570220U (en) | Satellite-borne low-phase-noise frequency source | |
| CN203933647U (en) | Signal magnitude detector and comprise the wireless receiver of this signal magnitude detector | |
| CN204068933U (en) | The microwave local oscillation signal generator of small integrated | |
| CN117420351B (en) | Instantaneous frequency measurement circuit | |
| CN209731217U (en) | A kind of signal amplifying apparatus | |
| CN102055543A (en) | Demodulating broadcasting receiver | |
| CN115529054B (en) | Phase tracking receiver system | |
| CN212932775U (en) | W-band large dynamic detection circuit | |
| CN216490452U (en) | Communication equipment and frequency synthesis device thereof | |
| CN106849969B (en) | K-waveband frequency synthesizer in five-channel receiver for space electronic reconnaissance |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |