CN220732797U - SWIO protocol-oriented packet grabbing analysis circuit - Google Patents
SWIO protocol-oriented packet grabbing analysis circuit Download PDFInfo
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- CN220732797U CN220732797U CN202420469246.2U CN202420469246U CN220732797U CN 220732797 U CN220732797 U CN 220732797U CN 202420469246 U CN202420469246 U CN 202420469246U CN 220732797 U CN220732797 U CN 220732797U
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Abstract
The utility model discloses a packet grabbing analysis circuit facing SWIO protocol, which is connected between a first channel and a second channel of a logic analyzer and comprises a variable resistor, a first SWPIO signal line and a second SWPIO signal line; the first channel of the logic analyzer is connected with the first end of the variable resistor, and the second channel of the logic analyzer is connected with the second end of the variable resistor; the first end of the variable resistor is connected with one end of the first SWPIO signal line, and the second end of the variable resistor is connected with one end of the second SWPIO signal line. According to the utility model, the variable resistor is arranged, and voltage drop occurs at two ends of the variable resistor, so that the logic analyzer can detect voltage change according to the set trigger voltage, the problem that the logic analyzer in the prior art cannot detect logic coding of an S2 signal is solved, and the data analysis requirement of a developer on the SWIO protocol can be met.
Description
Technical Field
The utility model relates to a packet grabbing analysis circuit oriented to an SWIO protocol, and belongs to the technical field of near field communication.
Background
Near field communication (Near Field Communication, abbreviated NFC) is a short range wireless communication technology. Its application area is very wide, including but not limited to:
electronic payment: NFC technology enables mobile devices such as mobile phones to be used as electronic wallets for contactless payment transactions.
Identity authentication: the NFC technology can be used for an access control system, and the physical or logical access authority is controlled by performing identity verification through NFC tags or equipment.
Mobile identity recognition: NFC technology supports identification between mobile devices, such as bus certificates or tickets in public transportation systems.
Anti-counterfeiting: the NFC technology can be used for anti-counterfeiting labels and helps to identify the authenticity of commodities.
SWIO (Single Wire Protocol Input/Output) is a single-wire half duplex communication protocol for communication between an NFC controller chip (NFCC) and a SIM card. In the SWIO protocol, the S1 signal and the S2 signal are two different signals that play a vital role in the communication between the SIM card and the reader. Specifically: the S1 signal is a voltage signal for a signal line representing data. UICC card (universal integrated circuit card) receives data by detecting the high and low level of S1 signal, this modulation mode is called level width modulation. The S2 signal is a current signal and adopts a load modulation mode. The effective transmission of the S2 signal depends on the state of the S1 signal, and the S2 signal is only effective when the S1 signal is high. In summary, in the SWIO protocol, the use of the S1 and S2 signals in combination ensures that data can be transferred between the SIM card and the card reader without errors.
In the debugging process of NFC products, it is often necessary to grab packets to analyze the data of the SWIO protocol. Logic analyzers are commonly used in the prior art for packet-grabbing analysis of data. Logic analyzers are instruments that collect and display digital signals from test equipment using clock signals, the most important function being timing decisions. Since logic analyzers do not have as many voltage levels as oscilloscopes, typically only two voltages (logically 1 and 0) are displayed. After the reference voltage is set, the logic analyzer judges the detected signal through the comparator, wherein the signal higher than the reference voltage is 1, the signal lower than the reference voltage is 0, and a digital waveform is formed between 1 and 0. However, since the current signal is used when the slave device returns data to the master device in the SWIO protocol, and the logic analyzer can only collect the voltage signal and cannot analyze the current signal, the simple use of the logic analyzer cannot meet the data analysis requirement of the developer on the SWIO protocol.
Disclosure of Invention
The utility model aims to provide a packet grabbing analysis circuit oriented to an SWIO protocol.
In order to achieve the technical purpose, the utility model adopts the following technical scheme:
the packet grabbing analysis circuit facing the SWIO protocol is connected between a first channel and a second channel of the logic analyzer and comprises a variable resistor, a first SWPIO signal line and a second SWPIO signal line; wherein,
the first channel of the logic analyzer is connected with the first end of the variable resistor, and the second channel of the logic analyzer is connected with the second end of the variable resistor;
the first end of the variable resistor is connected with one end of the first SWPIO signal line, and the second end of the variable resistor is connected with one end of the second SWPIO signal line.
Preferably, the other end of the first SWPIO signal line is connected with the NFC controller chip.
Wherein preferably, the other end of the second SWPIO signal line is connected with a Class C type SIM card.
Preferably, the first channel of the logic analyzer is an S1 signal in the SWIO protocol, and the second channel of the logic analyzer is an S2 signal in the SWIO protocol.
Preferably, the S1 signal is a voltage signal from the NFC controller chip to the Class C SIM card; the S2 signal is a current signal from the Class C type SIM card to the NFC controller chip.
Wherein, the resistance value of the variable resistor is preferably 575 to 767Ω.
Compared with the prior art, the variable resistor is connected in series on the signal line connecting the NFC controller chip and the SIM card, and voltage drop occurs at two ends of the variable resistor, so that the logic analyzer can detect voltage change according to the set trigger voltage, the problem that the logic analyzer in the prior art cannot detect logic coding of the S2 signal is solved, and the data analysis requirement of a developer on the SWIO protocol can be met.
Drawings
Fig. 1 is a schematic circuit diagram of a packet grabbing analysis circuit according to an embodiment of the present utility model;
FIG. 2 is a schematic diagram of states of logic 1 and logic 0 in S1 and S2 signals defined in SWIO protocol;
fig. 3 is a schematic logic level diagram of a packet grabbing analysis circuit in a working state according to an embodiment of the present utility model.
Detailed Description
The technical contents of the present utility model will be described in detail with reference to the accompanying drawings and specific examples.
As shown in fig. 1, an embodiment of the present utility model provides a packet grabbing parsing circuit for SWIO protocol. The packet grabbing analysis circuit is connected between a first channel and a second channel of the logic analyzer and comprises a variable resistor R1, a first SWPIO signal line 1 and a second SWPIO signal line 2; the first channel of the logic analyzer is connected with a first end (namely an end A which is one end connected with the NFCC) of the variable resistor R1, and the second channel of the logic analyzer is connected with a second end (namely an end B which is one end connected with the SIM card) of the variable resistor R1; the first end of the variable resistor R1 is connected to one end of the first SWPIO signal line 1, and the second end of the variable resistor R1 is connected to one end of the second SWPIO signal line 2.
Wherein the first Channel (Channel 1) of the logic analyzer is designated as the S1 signal and the second Channel (Channel 2) is designated as the S2 signal. Each channel can be distinguished between a high level (logic 1) and a low level (logic 0) according to a set threshold voltage. For example, if the threshold voltage range of one logic analyzer is 0.7V to 1.4V, a signal higher than 1.4V will be recognized as high level, and a signal lower than 0.7V will be recognized as low level.
The following describes the working principle of the present utility model, taking as an example a near field communication scenario in which the above-mentioned packet capturing and analyzing circuit is applied between an NFC controller chip and a Class C type SIM card (abbreviated as Class C).
As shown in fig. 1, the NFC controller chip is connected to the C terminal of the first SWPI0 signal line 1; the Class C SIM card is connected to the D terminal of the second SWPIO signal line 2. In one embodiment of the utility model, the S1 signal is a voltage signal from the NFC controller chip to the Class C SIM card; the S2 signal is the current signal from the Class C type SIM card to the NFC controller chip. Wherein the voltage drop between logic 0 of the S2 signal and logic 1 of the S2 signal is 80mV.
As shown in fig. 2, the S1 signal, the logic 0 and the logic 1 of the S2 signal are defined by the SWIO protocol, namely: logic 1 of the S1 signal when the high level duty ratio is 3/4 in one bit period; the high duty cycle of one bit period is 1/4 of the logic 0 of the S1 signal. When the current signal is a logic 0 of the S1 signal, the current signal is a logic 1 of the S2 signal; if the current signal is not present, it is a logic 0 of the S signal.
As shown in fig. 3, the PC upper computer reads the voltage signal and the current signal collected by the logic analyzer, and obtains the resistance value of the variable resistor R1 through calculation. Specifically, according to the regulation of the current value range corresponding to the S2 signal in the SWIO protocol, the current corresponding to the S2 signal is set to be 0.6-0.8 mA, and according to the current value corresponding to the S2 signal, the impedance of the Class C type SIM card when in internal conduction is calculated to be 100-133 omega.
The calculation formula of the impedance of the Class C type SIM card when the inside of the Class C type SIM card is conducted is as follows:
impedance = voltage drop ≡s2 signal current
V corresponding to S1 signal IH min The calculation formula of (2) is as follows:
wherein the VCC of the Class C type SIM card is 1.8V, namely V IH min Is 1.26V.
Wherein V is IH min The minimum value of the input high level corresponding to the S1 signal.
Because the greater the voltage drop, the easier it is for the logic analyzer to identify it, and because the voltage of the S2 signal at logic 0 (V S20 ) Equivalent to the Voltage (VCC) corresponding to the S1 signal, so V S20 Must not be less than V IH min I.e. V S20 ≥1.26V。
Wherein V is S20 The calculation formula is as follows:
V S20 =vcc-voltage drop
Therefore, the maximum value of the pressure drop is 0.54V.
According to the proportional relation, in the situation that the current corresponding to the S2 signal is set to be 0.6-0.8 mA, when the voltage drop is 80mV, the impedance of the Class C type SIM card when the internal conduction is 100-133 omega, and when the voltage drop is 0.54V, the impedance of the Class C type SIM card when the internal conduction is 675-900 omega.
Since the impedance of the Class C SIM card when it is turned on is a fixed value, that is, 100 to 133 Ω, it is necessary to connect a resistor having a resistance value of (675-100) to (900-133 Ω), that is, a resistance value of the variable resistor R1, to be 575 to 767Ω in series to a signal line connecting the NFC controller chip and the SIM card. From this, it can be seen that the resistance of the variable resistor R1 is proportional to the voltage drop.
After setting the variable resistor R1, when the state of the S2 signal is set to logic 1, the voltage values of both ends of the variable resistor R1 are not equal. For example, the voltage value of the first terminal of the variable resistor R1 is 1.26V, and the voltage value of the second terminal is 1.8V. Therefore, the trigger voltage of the logic analyzer can be set within the voltage range across the variable resistor R1, i.e., within 1.26V to 1.8V. In a preferred embodiment of the utility model, the trigger voltage may be set to an intermediate value of 1.26V to 1.8V, i.e. 1.53V, in order for the logic analyzer to collect data better.
According to the utility model, the variable resistor is connected in series on the signal line connecting the NFC controller chip and the SIM card, and voltage drop occurs at two ends of the variable resistor, so that the logic analyzer can detect voltage change according to the set trigger voltage, the problem that the logic analyzer in the prior art cannot detect logic coding of the S2 signal is solved, and the data analysis requirement of a developer on the SWIO protocol can be met.
On the basis, a logic analyzer can be used for sampling signal waveforms and exporting sampling results into CSV files in the process of data interaction between the NFC controller chip and the Class C type SIM card. And then, importing the exported CSV file into data analysis software, extracting pulse high-level duration time of each of the S1 signal and the S2 signal according to the time stamp information of the level change obtained by sampling, and further extracting bit streams of the S1 signal and the S2 signal according to the specified contents of logic 0 and logic 1 of the S1 signal and the S2 signal for use when a developer performs SWIO protocol analysis.
The packet grabbing analysis circuit for the SWIO protocol provided by the utility model is described in detail. Any obvious modifications to the present utility model, without departing from the spirit thereof, would constitute an infringement of the patent rights of the utility model and would take on corresponding legal liabilities.
Claims (6)
1. The packet grabbing analysis circuit facing the SWIO protocol is connected between a first channel and a second channel of a logic analyzer and is characterized by comprising a variable resistor, a first SWPIO signal line and a second SWPIO signal line; wherein,
the first channel of the logic analyzer is connected with the first end of the variable resistor, and the second channel of the logic analyzer is connected with the second end of the variable resistor;
the first end of the variable resistor is connected with one end of the first SWPIO signal line, and the second end of the variable resistor is connected with one end of the second SWPIO signal line.
2. The packet-grabbing parsing circuit of claim 1, wherein:
and the other end of the first SWPIO signal line is connected with the NFC controller chip.
3. The packet-grabbing parsing circuit of claim 1, wherein:
and the other end of the second SWPIO signal line is connected with a Class C type SIM card.
4. The packet-grabbing parsing circuit of claim 1, wherein:
the first channel of the logic analyzer is an S1 signal in the SWIO protocol, and the second channel of the logic analyzer is an S2 signal in the SWIO protocol.
5. The packet-grabbing parsing circuit of claim 4, wherein:
the S1 signal is a voltage signal from the NFC controller chip to the Class C type SIM card; the S2 signal is a current signal from the Class C type SIM card to the NFC controller chip.
6. The packet-grabbing parsing circuit of claim 1, wherein:
the resistance value of the variable resistor is 575-767Ω.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202420469246.2U CN220732797U (en) | 2024-03-12 | 2024-03-12 | SWIO protocol-oriented packet grabbing analysis circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202420469246.2U CN220732797U (en) | 2024-03-12 | 2024-03-12 | SWIO protocol-oriented packet grabbing analysis circuit |
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| CN220732797U true CN220732797U (en) | 2024-04-05 |
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| CN202420469246.2U Active CN220732797U (en) | 2024-03-12 | 2024-03-12 | SWIO protocol-oriented packet grabbing analysis circuit |
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