CN220729416U

CN220729416U - Integrated magnetic switch chip

Info

Publication number: CN220729416U
Application number: CN202320675001.0U
Authority: CN
Inventors: 何生生; 王为; 李泽宏; 李勇
Original assignee: Guizhou E Chip Microelectronics Technology Co ltd; GUIZHOU YAGUANG ELECTRONICS TECHNOLOGY CO LTD
Current assignee: Guizhou E Chip Microelectronics Technology Co ltd; GUIZHOU YAGUANG ELECTRONICS TECHNOLOGY CO LTD
Priority date: 2023-03-28
Filing date: 2023-03-28
Publication date: 2024-04-05
Anticipated expiration: 2033-03-28

Abstract

The application discloses integrated magnetic switch chip for improve integrated magnetic switch chip data acquisition's accuracy. The application comprises the following steps: the circuit comprises a Wheatstone bridge, a low offset amplifier, a first schmitt trigger, a second schmitt trigger, a power supply module, a digital control module, a first transistor, a second transistor, a ground pin, a clock input pin CKI, a clock transmission pin CKO and an output pin; the power supply module is respectively connected with the Wheatstone bridge, the low-offset amplifier and the first Schmitt trigger; the Wheatstone bridge is respectively connected with the low-offset amplifier and the first transistor; the digital control module is respectively connected with the low offset amplifier, the first schmitt trigger, the second schmitt trigger, the clock input pin CKI, the clock transmitting pin CKO and the first transistor; the first Schmitt trigger is respectively connected with the low-offset amplifier and the second transistor; the output pin is respectively connected with the second schmitt trigger and the second transistor; the first and second transistors are connected to a ground pin.

Description

Integrated magnetic switch chip

Technical Field

The embodiment of the application relates to the field of magnetic switches, in particular to an integrated magnetic switch chip.

Background

The magnetic switch is a component for performing switch control by magnetic signals. The magnetic signal of the magnetic switch has extremely strong penetrating power, can easily penetrate through common barriers such as non-magnetic materials of plastics, metals, wood, rocks and the like, realizes complete transmission of the signal, and is not influenced by dust, greasy dirt, smog and background light sources in the environment in the signal transmission process. The characteristics enable the magnetic switch to be widely applied to various non-contact control systems with unique advantages, and the specific application relates to the fields of military national defense, medical electronics, industrial control, consumer electronics and the like. At present, magnetic switches can be generally divided into two types: the traditional type is a non-integrated magnetic switch represented by a reed pipe and an electromagnetic induction coil, and the other type is an integrated magnetic switch developed by combining a magnetic sensitive element with a Hall effect device and a magnetic resistance effect device as cores and a microelectronic process. The traditional non-integrated magnetic switch is gradually replaced by the integrated magnetic switch due to the defects of large volume, short service life, low sensitivity and the like.

Today, it is generally required in industry to measure various non-electric physical quantities, such as temperature, pressure, liquid level height, etc., and to convert the physical quantities into analog electrical signals by a transmitter to be transmitted to a control room or display device of hundreds of meters. The current transducer with 4-20mA current is most widely adopted in industrial detection at present, and the reason for adopting a current signal is that the current transducer is not easy to be disturbed. And the internal resistance of the current source is infinite, the precision is not affected when the lead resistor is connected in series in the loop, and hundreds of meters can be transmitted on a common twisted pair. In industrial applications, where the distance between the measuring device and the control room or display device may be tens to hundreds of meters, two-wire 4-20mA current transmitters are commonly used for cost reasons. The upper limit is 20mA because of the explosion-proof requirement: the spark energy caused by the on-off of the 20mA current is insufficient to ignite the gas; the reason why the lower limit does not take 0mA is to be able to detect a broken wire. The power consumption of the tested device and the signal conditioning circuit is required to be smaller than 4mA when the device works normally, otherwise, the transmitter cannot output zero potential of 4 mA.

Currently, in the operation of detecting the level of a liquid in an industrial water storage device, a non-contact liquid level detection scheme is generally selected, such as radar liquid level detection, infrared liquid level detection, ultrasonic liquid level detection, and the like. However, the traditional low-power consumption magnetic switch liquid level detection scheme uses reed pipes, a magnetic floater is arranged in the industrial water storage device, and the reed pipes are arranged in cascade at equal intervals along the wall surface of the device. The reed switch detects an external magnetic field, realizes circuit breaking through mechanical movement, and is an ideal switching device electrically. The liquid level detection device has the advantages of simple structure, simple and convenient manufacturing process, low power consumption, wide application in liquid level detection, low precision and sensitivity, poor reliability and incapability of meeting the real-time high-precision detection of the liquid level.

In order to solve the technical defects, the traditional integrated magnetic switch chip is adopted to replace the reed switch, the integrated magnetic switch chip periodically detects an external magnetic field according to wake-sleep, and an internal timer is set to be in a wake-up state every time only one chip is in, so that low-power consumption high-precision liquid level detection can be realized. However, in the application process, the clock frequency of the internal timer of the traditional integrated magnetic switch chip has randomness, and a plurality of chips are likely to be in an awake state at the same time, namely a common frequency phenomenon. Since there is no communication function between the cascade chips, the common frequency phenomenon cannot be eliminated. The common frequency phenomenon causes large GND fluctuation, the port sampling voltage VADC is interfered, and the error reporting of the liquid level height is caused, namely the common frequency phenomenon can reduce the accuracy of data acquisition of the integrated magnetic switch chip.

Disclosure of Invention

The application discloses integrated magnetic switch chip for improve integrated magnetic switch chip data acquisition's accuracy.

The first aspect of the present application provides an integrated magnetic switch chip, comprising:

the Digital Control circuit comprises a Wheatstone bridge, a low offset amplifier, a first Schmitt trigger, a second Schmitt trigger, a power supply module, a Digital Control module, a first transistor NMOS, a second transistor NMOS, a ground pin GND, a clock input pin CKI, a clock transmission pin CKO and an output pin OUT, wherein the Digital Control module is internally provided with a CNT module;

the power supply module is respectively connected with the Wheatstone bridge, the low-offset amplifier and the first Schmitt trigger;

the Wheatstone bridge is respectively connected with the low-offset amplifier and the first transistor NMOS;

the Digital Control module is respectively connected with the low offset amplifier, the first Schmidt trigger, the second Schmidt trigger, the clock input pin CKI, the clock transmitting pin CKO and the first transistor NMOS;

the first Schmitt trigger is respectively connected with the low offset amplifier and the second transistor NMOS;

the output pin OUT is respectively connected with the second Schmitt trigger and the second transistor NMOS;

The first transistor NMOS and the second transistor NMOS are both connected to the ground pin GND.

Optionally, the integrated magnetic switch chip further comprises a low-power consumption clock OSC;

the low power clock OSC is connected to the Digital Control module Digital Control.

Optionally, the Digital Control module is divided into an inner module and an outer module;

the outer module comprises a CONFIG_EN module, a cut-off enabling module, a CNT module and an OSC TRIM module;

the CONFIG_EN module is respectively connected with the cut-off enabling module and the second Schmitt trigger;

the cut-off enabling module is respectively connected with the CNT module, the clock input pin CKI and the clock transmitting pin CKO;

the OSC TRIM module is connected with the low-power-consumption clock OSC;

the OSC TRIM module is connected with the internal module through a CLK signal line;

the CNT module is connected with the internal module through a DUT_EN signal line;

the CNT module is connected to the clock input pin CKI.

Optionally, the disable enabling module includes a Tgate module and an RX/TX module;

the Tgate module is respectively connected with the CONFIG_EN module, the clock input pin CKI and the clock transmission pin CKO;

the RX/TX module is connected with the CNT module, the clock input pin CKI and the clock transmission pin CKO respectively.

Optionally, the power supply module includes a power supply voltage pin VCC and a reference voltage module VREG;

The power supply voltage pin VCC is connected with the reference voltage module VREG;

the reference voltage module VREG is respectively connected with the Wheatstone bridge, the low offset amplifier and the first Schmitt trigger.

Optionally, the wheatstone bridge is composed of a magnetic sensor R1, a magnetic sensor R2, a magnetic sensor R3 and a magnetic sensor R4;

the magnetic sensor R1, the magnetic sensor R2, the magnetic sensor R3 and the magnetic sensor R4 are sequentially connected to form an electric bridge.

Optionally, interfaces of the magnetic sensor R1 and the magnetic sensor R2 are connected with a low-offset amplifier;

the interfaces of the magnetic sensor R3 and the magnetic sensor R4 are connected with a low-offset amplifier;

the interfaces of the magnetic sensor R2 and the magnetic sensor R3 are connected with a first transistor NMOS;

the interfaces of the magnetic sensor R1 and the magnetic sensor R4 are connected with a power supply module.

Optionally, the magnetic sensor R1, the magnetic sensor R2, the magnetic sensor R3, and the magnetic sensor R4 are Hall magneto-resistance, AMR magneto-resistance, GMR magneto-resistance, or TMR magneto-resistance.

A second aspect of the present application provides a cascade chip comprising: MCU module, integrated magnetic switch chip group, resistor R5;

the MCU module comprises an IN_LH interface and a START interface;

the IN_LH interface of the MCU module is connected with the first end of the resistor R5;

the IN_LH interface of the MCU module is connected with an output pin OUT of each integrated magnetic switch chip IN the integrated magnetic switch chip set;

The START interface of the MCU module is connected with the integrated magnetic switch chip set;

the second end of the resistor R5 is connected with a power supply VCC;

the ground pin GND of each integrated magnetic switch chip in the integrated magnetic switch chip group is grounded;

the power supply module of each integrated magnetic switch chip in the integrated magnetic switch chip group is connected with a power supply VCC.

Optionally, a clock input pin CKI of a first integrated magnetic switch chip in the integrated magnetic switch chipset is connected with a START interface of the MCU module;

the clock transmitting pin CKO of the first integrated magnetic switch chip is connected with the clock input pin CKI of the second integrated magnetic switch chip;

the clock transmitting pin CKO of the (n-1) th integrated magnetic switch chip is connected with the clock input pin CKI of the (n) th integrated magnetic switch chip.

From the above technical solutions, the embodiments of the present application have the following advantages:

in the application, the integrated magnetic switch chip specifically comprises a Wheatstone bridge, a low offset amplifier, a first Schmidt trigger, a second Schmidt trigger, a power supply module, a Digital Control module Digital Control, a first transistor NMOS, a second transistor NMOS, a ground pin GND, a clock input pin CKI, a clock sending pin CKO and an output pin OUT, wherein the Digital Control module Digital Control is provided with a CNT module. The concrete connection mode is as follows: the power supply module is respectively connected with the Wheatstone bridge, the low-offset amplifier and the first Schmitt trigger. The wheatstone bridge is connected with the low-offset amplifier and the first transistor NMOS respectively. Digital number The Control module Digital Control is respectively connected with the low offset amplifier, the first schmitt trigger, the second schmitt trigger, the clock input pin CKI, the clock transmitting pin CKO and the first transistor NMOS. The first Schmitt trigger is respectively connected with the low offset amplifier and the second transistor NMOS. The output pin OUT is connected to the second schmitt trigger and the second transistor NMOS, respectively. The first transistor NMOS and the second transistor NMOS are both connected to the ground pin GND. The Digital Control module is provided with the CNT module, the CNT module is used for operation, specifically, the CNT module counts the period of a signal input by CKI, and the integrated magnetic switch chip can be enabled to work if and only if the counting result is equal to the chip number. Therefore, only one chip works at a time, the common frequency phenomenon that a plurality of chips work together due to clock common frequency is avoided, GND fluctuation is reduced, and port sampling voltage V is reduced _ADC Interference, improved integrated magnetic switch chip data acquisition's accuracy.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required for the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a chip system architecture of an integrated magnetic switch chip of the present application;

FIG. 2 is a schematic diagram of key waveforms of the integrated magnetic switch chip in the Active mode;

FIG. 3 is a schematic diagram of key waveforms of the integrated magnetic switch chip in the Reset operation mode;

FIG. 4 is a schematic diagram of the upper current path of the integrated magnetic switch chip of the present application;

FIG. 5 is a schematic diagram of clock calibration & switch numbering modes of an integrated magnetic switch chip of the present application;

FIG. 6 is a schematic diagram of a configuration mode chip timing diagram of an integrated magnetic switch chip according to the present application;

FIG. 7 is an external module schematic diagram of Digital Control of the integrated magnetic switch chip;

FIG. 8 is a schematic diagram of a chip system architecture of a cascaded chip of the present application;

FIG. 9 is a schematic diagram of key signal waveforms of the cascaded chips of the present application;

fig. 10 is a schematic diagram of key waveforms of an ith chip Ui of the cascade chip in the present application.

Detailed Description

In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system configurations, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.

It should be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It should also be understood that the term "and/or" as used in this specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.

As used in this specification and the appended claims, the term "if" may be interpreted as "when..once" or "in response to a determination" or "in response to detection" depending on the context. Similarly, the phrase "if a determination" or "if a [ described condition or event ] is detected" may be interpreted in the context of meaning "upon determination" or "in response to determination" or "upon detection of a [ described condition or event ]" or "in response to detection of a [ described condition or event ]".

In addition, in the description of the present application and the appended claims, the terms "first," "second," "third," and the like are used merely to distinguish between descriptions and are not to be construed as indicating or implying relative importance.

Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.

In the prior art, various non-electric physical quantities such as temperature, pressure, liquid level height and the like are commonly required to be measured in industry, and the physical quantities are converted into analog electric signals through transmitters and then transmitted to a control room or display device which is hundreds of meters away. The current transducer with 4-20mA current is most widely adopted in industrial detection at present, and the reason for adopting a current signal is that the current transducer is not easy to be disturbed. And the internal resistance of the current source is infinite, the precision is not affected when the lead resistor is connected in series in the loop, and hundreds of meters can be transmitted on a common twisted pair. In industrial applications, where the distance between the measuring device and the control room or display device may be tens to hundreds of meters, two-wire 4-20mA current transmitters are commonly used for cost reasons. The upper limit is 20mA because of the explosion-proof requirement: the spark energy caused by the on-off of the 20mA current is insufficient to ignite the gas; the reason why the lower limit does not take 0mA is to be able to detect a broken wire. The power consumption of the tested device and the signal conditioning circuit is required to be smaller than 4mA when the device works normally, otherwise, the transmitter cannot output zero potential of 4 mA.

Currently, in the operation of detecting the level of a liquid in an industrial water storage device, a non-contact liquid level detection scheme is generally selected, such as radar liquid level detection, infrared liquid level detection, ultrasonic liquid level detection, and the like. However, the main drawbacks of the above solution are: (1) The cost is high, the response speed is low, the sensitivity is low, the periodic maintenance is needed, and the service life is short. (2) The liquid level measuring range measured by the scheme is generally not more than 20m, when the liquid level height to be measured and the precision requirement thereof are higher, the power consumption can exceed the minimum current (4 mA) of a 4-20mA transmitter, and the high-precision liquid level measurement requirement of an industrial large-scale liquid storage device can not be met.

The traditional low-power consumption magnetic switch liquid level detection scheme is to use reed pipes, wherein a magnetic floater is arranged in an industrial water storage device, and the reed pipes are arranged in cascade at equal intervals along the wall surface of the device. The reed switch detects an external magnetic field, realizes circuit breaking through mechanical movement, and is an ideal switching device electrically. The liquid level detector is simple in structure, simple and convenient in manufacturing process, low in power consumption and wide in application in liquid level detection, but the liquid level detector is also insufficient: (1) The precision and the sensitivity are low, the reliability is poor, and the real-time high-precision detection of the liquid level cannot be satisfied. (2) Because it is a mechanical movable switch, it has short life, is sensitive to vibration, and is large in size and difficult to integrate.

Moreover, the common frequency phenomenon will cause instantaneous large current, so that the power chip is overloaded, and if the power chip is not limited by overcurrent, the power chip may be burnt. The common frequency phenomenon causes the power supply voltage drop of the chip, and the abnormal reset of the chip can be caused.

Based on this, this application discloses an integrated form magnetic switch chip for improve integrated form magnetic switch chip data acquisition's accuracy.

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

Referring to fig. 1, 2, 3, 4, 5, 6, 7, 8 and 9, one embodiment of an integrated magnetic switch chip is provided, comprising:

the power supply module is respectively connected with the Wheatstone bridge, a Low offset amplifier (Low offset AMP) and a first Schmitt trigger;

In this embodiment, the integrated magnetic switch chip can induce the change of the external magnetic field, convert the magnetic signal into an electrical signal, and then compare the potential of the signal with the set threshold voltage through the integrated circuit, so as to obtain an open-drain output result, and then indicate the level of the output. The power supply voltage range of the integrated magnetic switch chip is 1.65V-5.5V, and the working temperature is-40-125 ℃. In this embodiment, the integrated magnetic switch chip works in a wake-sleep cycle in the magnetic field detection process, and the wake-sleep cycle is adjustable. Specifically, the 5 pins are a power supply voltage pin VCC, a ground pin GND, a clock input pin CKI, a clock transmission pin CKO, and an output pin OUT. And the supply voltage pin VCC is located in the supply module.

The integrated magnetic switch chip in the embodiment can meet the low-power consumption high-precision liquid level measurement requirement of medium-large industrial liquid storage devices, reduce the common frequency phenomenon and improve the accuracy of data acquisition of the integrated magnetic switch chip.

The integrated magnetic switch chip has multiple clock input pins CKI (clock input pins CKI) functions, one is used as clock input of a CNT mode, the other is used as RST of the CNT mode chip, the third is used as enabling of an Active mode, and the fourth is used as a communication interface of a configuration mode to receive upper-level or host MCU data.

The integrated magnetic switch chip has a plurality of clock transmission pins CKO (clock transmission pins CKO) functions, one is used as a clock output of the CNT mode, and the other is used as a communication interface of the configuration mode to transmit configuration data to a lower stage.

The low power magnetic switch chip can be configured to support single chip applications and multi-chip cascade applications. As will be described in detail later.

the OSC TRIM module is connected with the low-power-consumption clock OSC;

the CNT module is connected to the clock input pin CKI.

OSC is the on-chip clock of the chip that controls the period of magnetic field detection. The second trigger is mainly used for preventing the OUT pin from being triggered by mistake, and the OUT pin is only pulled down and the OUT pin is pulled down until the time set by us. The vreg provides a Wheatstone magnetic bridge and a supply voltage of a low offset amplifier, the low offset amplifier amplifies an output signal sensed by the magnetic bridge and inputs the output signal into the Schmitt trigger, and when the amplified signal exceeds the threshold value of the Schmitt trigger, the output of the Schmitt trigger is reversed, so that the basic function of the magnetic switch is realized.

Referring to fig. 2 and 3, fig. 2 and 3 are schematic diagrams of key waveforms of the integrated magnetic switch chip in two working modes of Active and single chip Reset.

When configured as a single-chip application, there are two modes of operation, single-chip Active and single-chip Reset. When the high level time T of the pin CKI is greater than T _s1 (i.e. t>T _s1 Ts1 is a preset time threshold), the chip will enter an Active mode, and the self-circulation wake-sleep detection external magnetic field is started: each circuit module in the wake-up state can work to detect external magnetismA field that refreshes and transmits the magnetic field detection result to pin OUT (output pin OUT); and in the sleep state, all circuit modules are closed, and only the built-in low-power-consumption clock works. When the low level time T of the pin CKI is greater than T _RST Time (t)>T _RST Wherein T is _RST For another preset time threshold value), the chip will enter Reset mode, the chip is Reset, only the built-in low power consumption clock OSC and part of digital control modules work, and the pin OUT recovers the high resistance state. The wake-up-sleep cycle of the chip under a single chip application will first complete the setup in configuration mode. The single chip application is passed through with pins CKI and CKO.

Wherein CKI is an input voltage waveform signal of a chip on a CKI pin, I represents a chip number of a plurality of chips in cascade connection, and I _cc (i) Indicating the current consumption of the ith chip, and OUT (i) indicating the output of the ith chip.

Referring to fig. 4, fig. 4 is a schematic diagram illustrating an upper current flow of the integrated magnetic switch chip. First, VDD power-up operation is performed, and the osc_ok signal is pulled high through the low power consumption always OSC start. In this embodiment, pulling high the osc_ok signal indicates that clock start is completed, the OUT pin monitors whether pulled low, if not pulled low, continues monitoring, if pulled low, determines whether the pin OUT is pulled low from high to low and the low time T is greater than TENC, if yes, enters the operation of configuration mode, and if no, waits again. When the configuration is successful, judging whether the pin CKI is in high level, if so, judging whether the time T of the high level is smaller than the preset value T _s1 If yes, CNT mode is performed, if yes, active mode is performed, if T is greater than T _RST When the Reset mode is entered.

After the integrated magnetic switch chip is powered on, the OUT pin enters a signal receiving state, and when the OUT pin is pulled down from a high level to a low level and the time T of the low level is greater than T _ENC (T>T _ENC ，T _ENC A preset time threshold) into a chip configuration mode. Single chip elapsed configuration time TCONFIG (where T _CONFIG =20×clk), and exits the calibration mode, while the multi-chip requires a configuration time n×t _CONFIG After (N is the number of chip cascade), finishing and exiting the calibration moduleA formula (I); the enable receiving pin CKI enters a signal receiving state, and the entered operation mode is determined according to the high level time t of the input signal.

Referring to fig. 5, fig. 5 is a schematic diagram of clock calibration & switch numbering modes of an integrated magnetic switch chip.

INT_LH is the pin signal, T, of the MCU in the cascaded chip _OUTL I.e. the time the OUT pin of the chip is pulled low, T _ENC Is a time prescribed by any designer.

CKI (1) is the CKI signal corresponding to the first chip, and CKO (N) is the CKO signal corresponding to the Nth chip.

FIG. 6 is a timing diagram of a configuration mode chip, handshaking: clk, clock alignment: 2 x clk, calibration accuracy 1%, mode set: clk,00: encoding; 01: active reset time; 10: preOP gain, data coding: 12 x clk,12bit may set a code value, end flag: 2 clk.

Pin OUT is pulled low from high to low and low time T is greater than T _ENC (T>T _ENC ) Entering a chip configuration mode, and completing Active reset time setting or serial number coding setting by sending a command to the CKI: 1) Active reset time setting under single chip application: the mode setting value is 01, the reset time of the Active mode chip is set, and 13 gears are total 0/0.1/0.2/0.4/0.8/1/2/4/8/16/32/64/128 ms. 2) The following sequence number coding modes are applied to the multi-chip cascade connection: the mode setting value is 00, the host MCU writes a serial number 1 into the 1 st chip, after the 1 st chip is written, a serial number 2 is written into the 2 nd chip through CKO, and the like until all chip serial numbers are written, and at most 4095 serial number values can be supported; if the ith chip configuration fails, feeding back a write-in code to the host through the CKO/CKI bus; if they are all normal, no signal is fed back. After the chip is configured, the chip automatically enters a CNT working mode, and monitors and counts the clock signal of an input pin CKI. By sending commands to CKI in configuration mode, the command packet reference timing is described as follows: handshake is completed in the first two clock cycles, clock calibration is completed in the two clock cycles, and the calibration precision is 1%; the fifth and sixth clock cycles complete the mode setting, where the mode setting value 00 is a sequence number code, mode setting The value 01 is the setting of Active reset time; setting a 12 bit code value setting immediately following 12 clock cycles; the last two clock cycles are end marks, and the configuration mode is completed and exited.

Referring to fig. 7, fig. 7 is an external module schematic diagram of Digital Control of the Digital Control module. The configuration mode scheme specifically comprises the following steps: pin OUT detects that it is pulled low from high and low for a time T greater than T _ENC (T>T _ENC ) At this time, the CONFIG_EN module will send a signal to Tgate&RX/TX module (ring enable module), tgate is turned off and RX/TX is enabled, pins CKI and CKO are no longer through, while Tgate&The RX/TX module sends a signal to the CNT module to turn it off. The pin CKI receives an external input command to finish the setting of the Active reset time or the serial number coding. After the chip configuration is completed, the CNT module is re-enabled, and the pin CKI will transmit a command to the pin CKO through TX and input into the pin CKI of the next chip. If the configuration fails, pin CKO will feed back the write code to the host through RX and pin CKI.

The CNT module is a serial number configuration module and is used for counting, enabling a chip to work when the period of a signal input from a CKI pin is equal to a set chip number, and inputting DUT_EN into an internal module of a digital control module. clk is an on-chip clock, and is also an internal module input to the digital control module digotal as a digital clock signal.

Please refer to fig. 8, 9-10. Fig. 8 is a schematic diagram of a cascaded chip structure. Fig. 9 is a schematic diagram of key signal waveforms of a cascaded chip. Fig. 10 is a schematic diagram of key waveforms of the ith chip Ui of the cascade chip.

Optionally, the cascade chip comprises an MCU module, an integrated magnetic switch chip set and a resistor R5;

the MCU module comprises an IN_LH interface and a START interface;

the second end of the resistor R5 is connected with a power supply VCC;

Referring to fig. 8 and 9, the cascade chip includes an MCU, a pull-up resistor R5, a magnetic float, and a plurality of chips arranged in series at equal intervals. The START pin of the MCU is connected with the CKI (1) pin of the first chip U1, the CK0 (i) of the ith chip Ui at the back is connected with the CKI (i-1) pin of the (i-1) chip U (i-1) at the front (i=2-n), the output pins OUT of all the magnetic switch chips are connected with the INT_LH pin of the MCU and the pull-up resistor R, and the power supply voltage pin VCC of the magnetic switch chips is connected with the other end of the pull-up resistor VCC.

As shown in FIG. 10, when the CKI high time T is less than T _s1 (t<T _s1 ) When the chip enters a CNT mode, the outside continuously transmits a clock signal to a pin CKI, and if and only if the number of the CKI clock cycles is equal to the serial number of the chip, each circuit module in the chip can work, an external magnetic field is detected, and a magnetic field detection result is refreshed and transmitted to a pin OUT. After the detection is finished, the Reset mode is automatically entered, the chip is Reset, only a low-power-consumption clock and part of digital control modules are built in to work, and the pin OUT is recovered to a high-resistance state. The serial number of the chip under the multi-chip cascade application will be set up in configuration mode first. The multi-chip cascade application is through-connected with the lower pin CKI and the pin CKI.

When configured for multi-chip cascade applications, there are two modes of operation, multi-chip CNT and multi-chip Reset. When the high level time T of the CKI pin is less than T _s1 (t<T _s1 ) When the chip enters a CNT mode, the outside continuously transmits a clock signal to a pin CKI, and if and only if the number of the CKI clock cycles is equal to the serial number of the chip, each circuit module in the chip can work, an external magnetic field is detected, and a magnetic field detection result is refreshed and transmitted to a pin OUT. After the detection is finished, the Reset mode is automatically entered, the chip is Reset, only a low-power-consumption clock and part of digital control modules are built in to work, and the pin OUT is recovered to a high-resistance state. The serial number of the chip under the multi-chip cascade application will be set up in configuration mode first. The multi-chip cascade application is through-connected with the lower pin CKI and the pin CKI.

After the chip is powered up, the OUT pin enters a signal receiving state, when the OUT pin is pulled down from a high level to a low level and the low level time T is greater than TENC (T)>TENC) timeEntering a chip configuration mode. Single chip elapsed configuration time T _CONFIG (T _CONFIG =20×clk), and exits the calibration mode, while the multi-chip requires a configuration time n×t _CONFIG (N is the number of chip cascade connection) and exiting the calibration mode; the enable receiving pin CKI enters a signal receiving state, and the entered operation mode is determined according to the high level time t of the input signal.

The pin OUT enters a chip configuration mode when the high level is pulled down to the low level and the low level time T is greater than TENC (T > TENC), and the Active reset time setting or the serial number coding setting is completed by sending a command (command packet reference timing specification) to the CKI: 1) Active reset time setting under single chip application: the mode setting value is 01, the reset time of the Active mode chip is set, and 13 gears are total 0/0.1/0.2/0.4/0.8/1/2/4/8/16/32/64/128 ms. 2) The following sequence number coding modes are applied to the multi-chip cascade connection: the mode setting value is 00, the host MCU writes a serial number 1 into the 1 st chip, after the 1 st chip is written, a serial number 2 is written into the 2 nd chip through CKO, and the like until all chip serial numbers are written, and at most 4095 serial number values can be supported; if the ith chip configuration fails, feeding back a write-in code to the host through the CKO/CKI bus; if they are all normal, no signal is fed back. After the chip is configured, the chip automatically enters a CNT working mode, and monitors and counts the clock signal of an input pin CKI.

The configuration mode scheme specifically comprises the following steps: pin OUT detects that it is pulled low from high and low for a time T greater than T _ENC (T>T _ENC ) At this time, the CONFIG_EN module will send a signal to Tgate&RX/TX module, tgate is turned off and RX/TX is enabled, pins CKI and CKI are no longer through, while Tgate&The RX/TX module sends a signal to the CNT module to turn it off. The pin CKI receives an external input command to finish the setting of the Active reset time or the serial number coding. After the chip configuration is completed, the CNT module is re-enabled, and the pin CKI will transmit a command to the pin CKO through TX and input into the pin CKI of the next chip. If the configuration fails, pin CKO will feed back the write code to the host through RX and pin CKI.

By sending commands to CKI in configuration mode, the command packet reference timing is described as follows: handshake is completed in the first two clock cycles, clock calibration is completed in the two clock cycles, and the calibration precision is 1%; the fifth clock period and the sixth clock period complete mode setting, wherein the mode setting value 00 is serial number coding, and the mode setting value 01 is Active reset time setting; setting a 12 bit code value setting immediately following 12 clock cycles; the last two clock cycles are end marks, and the configuration mode is completed and exited.

An application scene under the multi-chip cascade mode is a high-precision low-power consumption liquid level detection scheme, and the liquid level detection scheme comprises an MCU, a pull-up resistor, a magnetic floater and a plurality of chips which are arranged in series at equal intervals. The START pin of the MCU is connected with the CKI (1) pin of the first chip U1, the CK0 (i) of the ith chip Ui at the back is connected with the CKI (i-1) pin of the (i-1) chip U (i-1) at the front (i=2-n), the output pins OUT of all the magnetic switch chips are connected with the INT_LH pin of the MCU and the pull-up resistor R, and the power supply voltage pin VCC of the magnetic switch chips is connected with the other end of the pull-up resistor VCC.

The liquid level detection process is as follows: the magnetic switch chips are distributed at equal intervals along the wall surface of the device, the unit interval is set to be LSB, the chip serial number configuration is completed, the CNT mode is entered, the START pins of the MCU continuously send clock signals to the chip braid, all the chip pins CKO and CKI are directly connected and count the rising times count of the CKI, and all the circuit modules in the chip can work when and only when the CKI clock cycle count is equal to the chip set serial number i, the external magnetic field is detected, and the magnetic field detection result is refreshed and sent to the pin OUT. After the detection is finished, the Reset mode is automatically entered, the chip is Reset, only a low-power-consumption clock and part of digital control modules are built in to work, and the pin OUT is recovered to a high-resistance state. When the liquid level reaches a certain height, a magnetic switch Ui close to the float is closed, a pull-up resistor connected with an OUT (i) pin of the magnetic switch chip Ui is pulled to GND, the INT_LH pin voltage of the MCU is pulled to GND, and the count value i directly corresponds to the liquid level height at the moment, namely the measured liquid level height is:

Height＝i*LSB

In the liquid level detection scheme, the requirements of the traditional scheme on series resistor strings, corresponding bias circuits and high-precision ADC (analog to digital converter) are omitted. The MCU counts the time from Start to INT_line being pulled down, and the liquid level height is converted, so that the scheme is simple and reliable.

In the liquid level detection scheme, the chips work successively, only one low-power-consumption magnetic switch chip wakes up at any time of the power Line VCC_line and the ground Line GND_line, the power consumption of the single low-power-consumption magnetic switch chip is not more than 500nA, the minimum current limit of the industrial 4-20mA transmitter is met, and the liquid level low-power consumption detection of the medium-large liquid storage device is realized.

In the above liquid level detection scheme, the chips are arranged at equal intervals in the LSB, and if the Height of the liquid storage device is FS_height, the liquid level measurement precision is as follows:

in the following description, the LSB is assumed to be 1 cm, if the height of the liquid storage device is 10m, the liquid level measurement precision is 1%o, and if the height of the liquid storage device is 40m, the liquid level precision is 0.25%o, so that the liquid level high-precision detection of the medium-sized and large-sized liquid storage device is realized.

In the present application, the terms "upper", "lower", "left", "right", "front", "rear", "top", "bottom", "inner", "outer", "middle", "vertical", "horizontal", "lateral", "longitudinal", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are merely used to illustrate the relative positional relationships between the components or portions, and do not particularly limit the specific mounting orientations of the components or portions.

Also, some of the terms described above may be used to indicate other meanings in addition to orientation or positional relationships, for example, the term "upper" may also be used to indicate some sort of attachment or connection in some cases. The specific meaning of these terms in this application will be understood by those of ordinary skill in the art as appropriate.

Furthermore, the terms "mounted," "configured," "provided," "connected," and "connected" are to be construed broadly. For example, it may be a fixed connection, a removable connection, or a unitary construction; may be a mechanical connection, or an electrical connection; may be directly connected, or indirectly connected through intervening media, or may be in internal communication between two devices, elements, or components. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art as the case may be.

Furthermore, the structures, proportions, sizes, etc. shown in the drawings herein are shown and described in detail for purposes of illustration only, and are not intended to limit the scope of the invention, which is defined in the claims, unless otherwise indicated, and which are otherwise used by those skilled in the art to which the invention pertains.

Claims

1. An integrated magnetic switch chip, comprising:

the Digital Control module Digital Control is respectively connected with the low offset amplifier, the first schmitt trigger, the second schmitt trigger, the clock input pin CKI, the clock transmitting pin CKO and the first transistor NMOS;

the first schmitt trigger is respectively connected with the low-offset amplifier and the second transistor NMOS;

2. The integrated magnetic switching chip of claim 1, further comprising a low power clock OSC;

the low-power-consumption clock OSC is connected with the Digital Control module.

3. The integrated magnetic switching chip of claim 2, wherein the Digital Control module is divided into an inner module and an outer module;

the OSC TRIM module is connected with the low-power-consumption clock OSC;

the CNT module is connected with the inner module through a DUT_EN signal line;

the CNT module is connected to the clock input pin CKI.

4. The integrated magnetic switching chip of claim 3, wherein the turn-off enable module comprises a Tgate module and an RX/TX module;

The Tgate module is respectively connected with the CONFIG_EN module, the clock input pin CKI and the clock transmitting pin CKO;

the RX/TX module is respectively connected with the CNT module, the clock input pin CKI and the clock transmission pin CKO.

5. The integrated magnetic switching chip of claim 1, wherein the power supply module comprises a supply voltage pin VCC and a reference voltage module VREG;

the reference voltage module VREG is respectively connected with the Wheatstone bridge, the low-offset amplifier and the first Schmitt trigger.

6. The integrated magnetic switching chip according to any one of claims 1 to 5, wherein the wheatstone bridge is composed of a magnetic sensor R1, a magnetic sensor R2, a magnetic sensor R3, a magnetic sensor R4;

7. The integrated magnetic switch chip according to claim 6, wherein interfaces of the magnetic sensor R1 and the magnetic sensor R2 are connected with the low offset amplifier;

the interfaces of the magnetic sensor R3 and the magnetic sensor R4 are connected with the low-offset amplifier;

The interfaces of the magneto-sensitive element R2 and the magneto-sensitive element R3 are connected with the first transistor NMOS;

and interfaces of the magnetic sensor R1 and the magnetic sensor R4 are connected with the power supply module.

8. The integrated magnetic switching chip of claim 6, wherein the magnetic sensor R1, the magnetic sensor R2, the magnetic sensor R3, and the magnetic sensor R4 are Hall magnetoresistance, AMR magnetoresistance, GMR magnetoresistance, or TMR magnetoresistance.

9. The integrated magnetic switch chip of claim 1, wherein the cascade chip comprises an MCU module, an integrated magnetic switch chip set, a resistor R5;

the MCU module comprises an IN_LH interface and a START interface;

the second end of the resistor R5 is connected with a power supply VCC;

10. The integrated magnetic switching chip of claim 9, wherein a clock input pin CKI of a first integrated magnetic switching chip in the integrated magnetic switching chip set is connected with a START interface of the MCU module;