CN220710324U - Semiconductor device with a semiconductor layer having a plurality of semiconductor layers - Google Patents

Abstract

The utility model discloses a semiconductor device, which comprises a source electrode, a drain electrode, a gate electrode, a bottom dielectric layer, a gate dielectric layer, a channel structure and a metal nitride layer. The drain and the source are stacked in a vertical direction, and the gate is disposed between the drain and the source. The bottom dielectric layer is disposed between the source and the gate. The channel structure is arranged between the drain electrode and the source electrode and is electrically connected with the drain electrode and the source electrode, and the channel structure part is arranged in the gate electrode and comprises a channel layer and an insulating layer which are sequentially stacked in the horizontal direction. The gate dielectric layer is disposed between the channel structure and the gate. The metal nitride layer is disposed between the gate dielectric layer and the gate. Thus, the gate dielectric layer can be isolated from direct contact with the gate electrode, and the operation performance of the semiconductor device can be improved.

Description

Semiconductor device with a semiconductor layer having a plurality of semiconductor layers

Technical Field

The present utility model relates generally to a semiconductor device, and more particularly, to a semiconductor device having a vertical channel structure.

Background

The technology of semiconductor integrated circuits continues to advance over time, with each new generation of manufacturing process having smaller and more complex circuit designs than the previous generation. The number and density of functional components in each wafer area must be increased due to product innovation, which of course results in smaller and smaller component geometries. Because conventional planar-oxide-semiconductor (MOS) transistor fabrication processes are difficult to scale continuously, it has been proposed in the industry to replace conventional planar transistor elements with solid or non-planar transistor elements to reduce the geometry of the transistor elements and/or to improve the performance of the transistor elements.

Disclosure of Invention

The utility model aims to provide a semiconductor device, wherein a metal nitride layer is additionally formed between a channel structure and a gate electrode, so that the gate dielectric layer is prevented from directly contacting metal to easily generate a high-resistance product, and the operation performance of the semiconductor device is improved.

In order to achieve the above object, one embodiment of the present utility model provides a semiconductor device including a source electrode, a drain electrode, a gate electrode, a bottom dielectric layer, a gate dielectric layer, a channel structure, and a metal nitride layer. The drain electrode and the source electrode are stacked in a vertical direction. The gate is disposed between the drain and the source in the vertical direction. The bottom dielectric layer is disposed between the source and the gate in the vertical direction. The channel structure is arranged between the drain electrode and the source electrode in the vertical direction and electrically connects the drain electrode and the source electrode, wherein the channel structure part is arranged in the gate electrode and comprises a channel layer and an insulating layer which are sequentially stacked in the horizontal direction. The gate dielectric layer is disposed between the channel structure and the gate in the horizontal direction. The metal nitride layer is disposed between the gate dielectric layer and the gate, wherein a portion of the bottom dielectric layer is sandwiched between the metal nitride layer and the source.

Optionally, the top surface of the metal nitride layer is lower than the top surface of the channel structure.

Optionally, the top surface of the metal nitride layer is between the top surface of the channel structure and the top surface of the gate.

Optionally, the drain, the source and the gate comprise the same metal material.

Optionally, the gate further includes: a gate layer; and a gate barrier layer disposed under the gate layer, the gate barrier layer physically contacting the metal nitride layer.

Optionally, the metal nitride layer and the gate barrier layer comprise the same material.

Optionally, the metal nitride layer and the gate barrier layer together have an L-shaped cross section.

Optionally, the bottom surface of the metal nitride layer is lower than the bottom surface of the gate barrier layer and does not physically contact the source electrode.

Optionally, the bottom surface of the metal nitride layer is flush with the bottom surface of the gate barrier layer and does not physically contact the source.

Optionally, the channel layer further includes: a first semiconductor layer stacked on the gate dielectric layer and not physically contacting the source electrode; and a second semiconductor layer stacked between the first semiconductor layer and the insulating layer, the second semiconductor layer physically contacting the source electrode and the drain electrode.

Optionally, the first semiconductor layer includes an I-shaped cross section, and the second semiconductor layer includes a U-shaped cross section.

Optionally, the channel layer comprises indium zinc oxide, aluminum zinc oxide, or indium gallium zinc oxide.

In general, the semiconductor device of the present utility model is characterized in that a metal nitride layer is additionally formed between the channel structure and the gate electrode, so that the dielectric material of the gate electrode dielectric layer is prevented from directly contacting with the metal material of the gate electrode to easily generate a product with high resistance, thereby improving the operation performance of the semiconductor device.

Drawings

The accompanying drawings are included to provide a further understanding of embodiments of the utility model and are incorporated in and constitute a part of this specification. These drawings and description serve to illustrate principles of some embodiments. It should be noted that all illustrations are schematic, and relative dimensions and proportions are adjusted for ease of illustration and drawing. The same reference signs represent corresponding or similar features in different embodiments.

Fig. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present utility model.

Fig. 2 to 11 are schematic views illustrating a method for manufacturing a semiconductor device according to an embodiment of the utility model; wherein the method comprises the steps of

Fig. 2 is a schematic cross-sectional view of the semiconductor device after forming a metal nitride material layer;

FIG. 3 is a schematic cross-sectional view of a semiconductor device after performing an etch-back process;

fig. 4 is a schematic cross-sectional view of the semiconductor device after forming a metal nitride layer;

FIG. 5 is a schematic cross-sectional view of a semiconductor device after forming a gate dielectric material layer;

fig. 6 is a schematic cross-sectional view of the semiconductor device after forming a first semiconductor material layer;

fig. 7 is a schematic cross-sectional view of the semiconductor device after forming a first semiconductor layer;

fig. 8 is a schematic cross-sectional view of the semiconductor device after forming a second semiconductor material layer;

fig. 9 is a schematic cross-sectional view of the semiconductor device after forming a layer of insulating material;

fig. 10 is a schematic cross-sectional view of the semiconductor device after forming an insulating layer; and

fig. 11 is a schematic cross-sectional view of the semiconductor device after forming a channel structure.

Fig. 12 is a schematic cross-sectional view of a semiconductor device according to a second embodiment of the present utility model.

Wherein reference numerals are as follows:

10. 26, 38 dielectric layer

12. 16, 40 barrier layer

14. 42 conductive layer

18. Bottom semiconductor layer

20. Bottom dielectric layer

22. Gate barrier layer

24. Gate layer

28. Gate dielectric layer

28a, 28b gate dielectric material layer

28A first part

28B, 28C second part

30. First semiconductor layer

30a first semiconductor material layer

32. Second semiconductor layer

32a second semiconductor material layer

34. Insulating layer

34a insulating material layer

36. Third semiconductor layer

50. 51 Metal nitride layer

50a, 50b metal nitride material layer

52. 52a semiconductor material layer

54. Groove

101. 103 semiconductor device

D1 In the vertical direction

D2 In the horizontal direction

D3 Opposite direction of D2

DE drain electrode

GE gate

OP1, OP3 puncturing

OP2 open pore

SE source electrode

SS channel structure

Detailed Description

In order to enable those skilled in the art to which the utility model pertains, a few preferred embodiments of the utility model are described below in detail, together with the accompanying drawings, in order to further explain the principles of the utility model and its advantages. Those skilled in the art to which the utility model pertains will be able to replace, reorganize, and mix features in several different embodiments with reference to the following examples to complete other embodiments without departing from the spirit of the utility model.

Referring to fig. 1, fig. 1 is a schematic cross-sectional view of a semiconductor device 101 according to a first embodiment of the present utility model. As shown in fig. 1, semiconductor device 101 includes source SE, bottom dielectric layer 20, gate GE, gate dielectric layer 28, channel structure SS, drain DE, and metal nitride layer 50. The drain electrode DE and the source electrode SE are stacked in the vertical direction D1, and the gate electrode GE is disposed above the source electrode SE and between the drain electrode DE and the source electrode SE. The channel structure SS is partially disposed in the gate electrode GE in the vertical direction D1 and is also disposed between the drain electrode DE and the source electrode SE to electrically connect the drain electrode DE and the source electrode SE. The channel structure SS includes the channel layer 46 and the insulating layer 34 sequentially stacked in the horizontal direction D2 or the opposite direction D3, wherein the insulating layer 34 may be used to indirectly control the composition of the channel structure SS and/or support the channel structure SS. The metal nitride layer 50 is disposed between the channel structure SS and the gate electrode GE to isolate the gate dielectric layer 28 from direct contact with the gate electrode GE, so as to prevent the dielectric material of the gate dielectric layer 28 from reacting with the metal material of the gate electrode GE and producing a high-resistance product. Wherein, a portion of the bottom dielectric layer 20 is sandwiched between the metal nitride layer 50 and the source electrode SE, so that the metal nitride layer 50 does not physically contact the source electrode SE. On the other hand, the top surface of the metal nitride layer 50 is preferably lower than the top surface of the channel structure SS, for example, between the top surface of the channel structure SS and the top surface of the gate electrode GE, and is further covered by the gate dielectric layer 28 without physically contacting the drain electrode DE as such. In one embodiment, the metal nitride layer 50 includes, for example, but not limited to, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), or other suitable conductive barrier materials, preferably including titanium nitride. Thus, the device performance of the gate electrode GE and the channel structure SS is effectively improved by the metal nitride layer 50, thereby improving the operation performance of the semiconductor device 101.

As further shown in fig. 1, semiconductor device 101 further includes dielectric layer 10, bottom semiconductor layer 18, dielectric layer 26, dielectric layer 38, perforations OP1 and openings OP2. The source SE, the bottom dielectric layer 20, the gate GE, the gate dielectric layer 28, the channel structure SS, the drain DE and the metal nitride layer 50 are all disposed on the dielectric layer 10, and the dielectric layer 10 is disposed on a substrate (not shown), such as a silicon substrate (silicon substrate), a silicon-containing substrate (silicon-containing substrate), an epitaxial silicon substrate (epitaxial silicon substrate), a silicon-on-insulator substrate (silicon-on-insulator substrate) or other suitable materials. Those skilled in the art will readily appreciate that various desired active and/or passive components may be further formed on or in the substrate depending on the actual device requirements. In the vertical direction D1, the bottom semiconductor layer 18 is disposed between the bottom dielectric layer 20 and the source electrode SE, the dielectric layer 26 is disposed between the gate electrode GE and the drain electrode DE, and the dielectric layer 38 is disposed on the dielectric layer 26, and the drain electrode DE is disposed in the dielectric layer 38, but not limited thereto. It should be noted that the through hole OP1 penetrates the dielectric layer 26 and the gate electrode GE in the vertical direction D1, and the opening OP2 penetrates the bottom dielectric layer 20 in the vertical direction D1, so that the through hole OP1 and the opening OP2 are directly connected, wherein the through hole OP1 has a relatively larger aperture to completely cover the opening OP2, but not limited thereto. In this way, the metal nitride layer 50, the gate dielectric layer 28 and a portion of the channel structure SS are sequentially disposed in the via OP1 in the horizontal direction D2 or the opposite direction D3, and another portion of the channel structure SS is disposed in the via OP2, such that the channel structure SS further penetrates the bottom dielectric layer 20 in the vertical direction D1 to physically contact the bottom semiconductor layer 18. Those skilled in the art should readily understand that the arrangement of the vias OP1 and the openings OP2 in the present utility model is not limited to the foregoing, but may have other different arrangements or shapes depending on the actual device requirements.

In detail, the channel layer 46 further includes the first semiconductor layer 30, the second semiconductor layer 32, and the third semiconductor layer 36 sequentially disposed in the horizontal direction D2 or the opposite direction D3 thereof. The first semiconductor layer 30 is disposed in the through hole OP1, the second semiconductor layer 32 is partially disposed in the through hole OP1 and partially disposed in the opening OP2, and the third semiconductor layer 36 is also disposed in the through hole OP1 and is located between the insulating layer 34 and the drain electrode DE. In the present embodiment, the first semiconductor layer 30 surrounds the second semiconductor layer 32 in the horizontal direction D2 and/or the opposite direction D3, and the second semiconductor layer 32 surrounds the third semiconductor layer 36 and the insulating layer 34 in the horizontal direction D2 and/or the opposite direction D3, so that the second semiconductor layer 32 has a U-shaped cross section in the cross section shown in fig. 1 and is located between the drain electrode DE and the bottom semiconductor layer 18 in the vertical direction D1, and so that the first semiconductor layer 30 has an I-shaped cross section in the cross section shown in fig. 1 and is located between the drain electrode DE and the gate dielectric layer 28. Thus, the second semiconductor layer 32 of the channel layer 46 physically contacts the first semiconductor layer 30, the third semiconductor layer 36 and the bottom semiconductor layer 18 at the same time, so that the channel layer 46 is electrically connected to the drain electrode DE and the source electrode SE when the gate electrode GE is applied with a threshold voltage. In one embodiment, the bottom semiconductor layer 18 and the first semiconductor layer 30, the second semiconductor layer 32 and the third semiconductor layer 36 in the channel layer 46 each include a semiconductor material, such as doped polysilicon, doped amorphous silicon, indium zinc oxide (indium zinc oxide, IZO), aluminum zinc oxide (aluminum zinc oxide, AZO), or indium gallium zinc oxide (indium gallium zinc oxide, IGZO), but not limited thereto. Also, the materials of the first semiconductor layer 30, the second semiconductor layer 32, the third semiconductor layer 36, and the bottom semiconductor layer 18 may be the same or different from each other.

The gate dielectric layer 28 further includes a first portion 28A extending along the vertical direction D1, and second portions 28B and 28C extending along the horizontal direction D2 or the opposite direction D3, wherein the first portion 28A is sandwiched between the first semiconductor layer 30 and the gate electrode GE in the horizontal direction D2 or the opposite direction D3, and the second portions 28B and 28C are sandwiched between the first semiconductor layer 30 and the bottom dielectric layer 20 or between the drain electrode DE and the metal nitride layer 50 in the vertical direction D1, but not limited thereto. In one embodiment, the dielectric layer 10, the bottom dielectric layer 20, the dielectric layer 26, the dielectric layer 38 and the gate dielectric layer 28 each comprise a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride or silicon carbonitride, or a high-k dielectric material, preferably including but not limited to silicon oxide. In another embodiment, the gate dielectric layer 28 may optionally comprise a single film or a composite film, preferably comprising a silicon oxide layer (not shown) and a high-k dielectric layer (not shown) stacked in sequence.

Preferably, the source electrode SE, the gate electrode GE and the drain electrode DE each comprise a composite layer structure. For example, the source electrode SE includes the barrier layer 12, the conductive layer 14 and the barrier layer 16 sequentially stacked in the vertical direction D1, the gate electrode GE includes the gate barrier layer 22 and the gate layer 24 sequentially stacked in the vertical direction D1, and the drain electrode DE includes the barrier layer 40 and the conductive layer 42 sequentially stacked in the vertical direction D1, but is not limited thereto. In other embodiments, the barrier layer 12, the barrier layer 16, the gate barrier layer 22 and/or the barrier layer 40 may be omitted selectively according to the actual device requirements, or the barrier layer 12, the barrier layer 16, the gate barrier layer 22 and the barrier layer 40 may be provided with a composite layer, but not limited thereto. The barrier layers 12, 16, 22 and 40 may comprise, for example, titanium nitride, tantalum nitride, tungsten nitride, or other suitable conductive barrier materials, and the materials of the barrier layers 12, 16, 22 and 40 may be the same or different, and preferably comprise titanium nitride, but are not limited thereto. In one embodiment, the gate barrier layer 22 and the metal nitride layer 50 preferably comprise the same material, such as but not limited to titanium nitride, so that the gate barrier layer 22 may be considered as an extension of the metal nitride layer 50 in the horizontal direction D2 or the opposite direction D3 thereof. In the present embodiment, the gate barrier layer 22 and the bottom surface of the metal nitride layer 50 are flush with each other and have an L-shaped cross section, as shown in fig. 1, but not limited thereto. In addition, the conductive layer 14, the gate layer 24 and the conductive layer 42 all include copper, aluminum, tungsten or other suitable low-resistance metal materials, and the materials of the conductive layer 14, the gate layer 24 and the conductive layer 42 may be the same or different, preferably include tungsten, but not limited thereto.

It should be noted that, the first semiconductor layer 30, the second semiconductor layer 32 and the insulating layer 34 of the present embodiment together present a columnar structure extending along the vertical direction D1, and the central axes of the columnar structures in the vertical direction D1 may substantially overlap, while the gate dielectric layer 28 presents a ring structure surrounding the channel structure SS and interposed between the gate electrode GE and the channel structure SS. In this arrangement, the source electrode SE, the gate electrode GE, the gate dielectric layer 28, the channel structure SS and the drain electrode DE together form a three-dimensional transistor device, so that the channel structure SS serves as a vertical channel structure of the three-dimensional transistor device, and the gate electrode GE surrounding the outside of the channel structure SS achieves a gate-all-around (GAA) like effect. Therefore, the semiconductor device 101 of the present embodiment can be electrically connected to other active devices and/or passive devices downward and/or upward through other connection devices in the subsequent manufacturing process, and the device performance of the gate electrode GE and the channel structure SS therein is effectively improved through the arrangement of the metal nitride layer 50, so as to achieve more optimized operation performance.

In order to enable those skilled in the art to which the present utility model pertains to easily understand the semiconductor device of the present utility model and realize the same, a method for manufacturing the semiconductor device 101 of the present utility model will be further described below.

Fig. 2 to 11 are schematic views illustrating a method for manufacturing a semiconductor device 101 according to an embodiment of the utility model. First, as shown in fig. 2, a source SE, a bottom semiconductor layer 18, a bottom dielectric layer 20, a gate GE and a dielectric layer 26 are sequentially formed on a dielectric layer 10, and a via OP1 is formed to sequentially penetrate the dielectric layer 26 and the gate GE to partially expose the bottom dielectric layer 20. Then, as shown in fig. 2, a metal nitride material layer 50a and a semiconductor material layer 52 are sequentially formed, which conformally cover the top surface of the dielectric layer 26 and cover the bottom and the sidewalls of the via OP1. That is, the metal nitride material layer 50a and the semiconductor material layer 52 are partially formed in the through hole OP1 and partially formed outside the through hole OP1. In one embodiment, the metal nitride material layer 50a includes, for example, titanium nitride, tantalum nitride, tungsten nitride or other suitable conductive barrier material, preferably includes the same material as the gate barrier layer 22, such as titanium nitride, and the semiconductor material layer 52 includes, for example, but not limited to, a semiconductor material such as doped polysilicon or doped amorphous silicon.

Next, an etching back process is performed to remove the semiconductor material layer 52 and the metal nitride material layer 50a formed outside the through hole OP1, and simultaneously remove the semiconductor material layer 52 and the metal nitride material layer 50a covered on the bottom of the through hole OP1, so as to form a semiconductor material layer 52a and a metal nitride material layer 50b only on the sidewall of the through hole OP1, as shown in fig. 3. The metal nitride material layer 50b and the semiconductor material layer 52a are sequentially stacked on the sidewall of the through hole OP1 in the horizontal direction D2 or the opposite direction D3, and have an L-shaped cross section and an I-shaped cross section, respectively, wherein, for example, top surfaces of the metal nitride material layer 50b and the semiconductor material layer 52a are coplanar with the top surface of the dielectric layer 26, but not limited thereto.

Then, an etching process is performed to completely remove the semiconductor material layer 52a, and simultaneously partially remove the metal nitride material layer 50b and the underlying bottom dielectric layer 20, so as to form a metal nitride layer 50 with a lower top surface on the sidewall of the via OP1, and simultaneously form a recess 54 with a lower top surface on the bottom dielectric layer 20 exposed from the via OP1, as shown in fig. 4. Wherein the top surface of the metal nitride layer 50 is significantly lower than the top surface of the dielectric layer 26 and the sidewalls of the metal nitride layer 50 are aligned with the sidewalls of the recess 54.

As shown in fig. 5, a gate dielectric material layer 28a is formed conformally covering the top surface of dielectric layer 26 and the bottom surface and the sidewalls of via OP1 while completely covering metal nitride layer 50 and filling recess 54. That is, the gate dielectric material layer 28a is also partially formed within the via OP1 and partially formed outside the via OP1. In one embodiment, the gate dielectric material layer 28a includes a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or the like, or includes a high-k dielectric material, preferably including the same material as the dielectric layer 26, the bottom dielectric layer 20, such as silicon oxide, or the like, but is not limited thereto. Furthermore, the gate dielectric material layer 28a may be formed by a film forming process, such as a chemical vapor deposition process, a physical vapor deposition process, or other suitable methods, but is not limited thereto. In another embodiment, the gate dielectric material layer 28a may optionally include a single film or a composite film, for example, including a silicon oxide layer (not shown) and a high-k dielectric layer (not shown) stacked in sequence.

As shown in fig. 6, a first semiconductor material layer 30a is formed on the gate dielectric material layer 28a, and also conformally covers the gate dielectric material layer 28a, such that the first semiconductor material layer 30a may also be partially formed within the via OP1 and partially formed outside the via OP1. In one embodiment, the first semiconductor material layer 30a includes a semiconductor material, such as doped polysilicon, doped amorphous silicon, indium zinc oxide, aluminum zinc oxide, or indium gallium zinc oxide, preferably including indium zinc oxide or indium gallium zinc oxide, but not limited thereto. Moreover, the first semiconductor material layer 30a may be formed by a film forming process, such as a chemical vapor deposition process, a physical vapor deposition process, or other suitable methods, but is not limited thereto.

Thereafter, as shown in fig. 7, the first semiconductor material layer 30a and the gate dielectric material layer 28a located outside the via OP1 are removed, and the first semiconductor material layer 30a and the gate dielectric material layer 28a located on the bottom of the via OP1 are removed, while the bottom dielectric layer 20 exposed from the via OP1 is further removed downward to form an opening OP2 penetrating through the bottom dielectric layer 20 to expose a portion of the bottom semiconductor layer 18. In an embodiment, the aperture OP2 overlaps the aperture OP1 in the vertical direction D1, and the projection area of the aperture OP2 in the vertical direction D1 is smaller than the projection area of the aperture OP1 in the vertical direction D1, so that the aperture OP2 and the aperture OP1 can directly communicate with each other, but not limited thereto. On the other hand, by the foregoing removal process of the first semiconductor material layer 30a and the gate dielectric material layer 28A, after the formation of the opening OP2, i.e., simultaneously, the first semiconductor layer 30 and the gate dielectric layer 28 having the first portion 28A and the second portions 28B, 28C are formed on the sidewall of the opening OP1. The first semiconductor layer 30 and the gate dielectric layer 28 have top surfaces that are flush with each other and are coplanar with the top surface of the dielectric layer 26, and the gate dielectric layer 28 completely covers the metal nitride layer 50.

As shown in fig. 8, after the opening OP2 is formed, the second semiconductor material layer 32a is formed, partially within the opening OP1, partially within the opening OP2, and partially outside the openings OP1 and OP2. In detail, the second semiconductor material layer 32a is conformally formed on the bottom and the sidewall of the opening OP2, the sidewall of the gate dielectric layer 28 and the sidewall of the first semiconductor layer 30, and the second semiconductor material layer 32a outside the opening OP1 and the opening OP2 covers the top surfaces of the dielectric layer 26, the gate dielectric layer 28 and the first semiconductor layer 30. In this embodiment, the first semiconductor layer 30 surrounds the second semiconductor material layer 32a in the via OP1, and the second semiconductor material layer 32a formed in the opening OP2 physically contacts the exposed top surface of the bottom semiconductor layer 18. In one embodiment, the second semiconductor material layer 32a also includes a semiconductor material, such as doped polysilicon, doped amorphous silicon, indium zinc oxide, aluminum zinc oxide, or indium gallium zinc oxide, and preferably includes the same material as the first semiconductor layer 30, such as indium zinc oxide or indium gallium zinc oxide, but not limited thereto. Also, the second semiconductor material layer 32a is formed by, for example, a film forming process such as a chemical vapor deposition process, a physical vapor deposition process, or other suitable methods, but not limited thereto.

As shown in fig. 9, after the second semiconductor material layer 32a is formed, an insulating material layer 34a is formed to fill the openings OP2 and the vias OP1, and further covers the second semiconductor material layer 32a outside the vias OP1. That is, the second semiconductor material layer 32a is partially formed within the via OP1, partially formed within the opening OP2, and partially formed outside of the via OP1 and the opening OP2. In one embodiment, the insulating material layer 34a includes a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride, and preferably includes silicon oxide, but is not limited thereto. Also, the insulating material layer 34a may be formed by a film forming process, such as a chemical vapor deposition process, a physical vapor deposition process, or other suitable methods, but not limited thereto.

Then, another etching back process is performed to remove a portion of the insulating material layer 34a, for example, remove the insulating material layer 34a outside the through hole OP1 and the opening OP2, and simultaneously partially remove the insulating material layer 34a inside the through hole OP1, so as to form the insulating layer 34, as shown in fig. 10. As such, the topmost surface of insulating layer 34 is lower than the top surface of dielectric layer 26 in the vertical direction D1.

After the insulating layer 34 is formed, a third semiconductor material layer (not shown) is formed to fill the through hole OP1 and further cover the second semiconductor material layer 32a outside the through hole OP1, and then a further etching back process is performed to remove the third semiconductor material layer and the second semiconductor material layer 32a outside the through hole OP1, so as to form a third semiconductor layer 36 and a second semiconductor layer 32, as shown in fig. 11. In an embodiment, the third semiconductor material layer also includes a semiconductor material, such as doped polysilicon, doped amorphous silicon, indium zinc oxide, aluminum zinc oxide, or indium gallium zinc oxide, and preferably includes the same material as the first semiconductor layer 30 and/or the second semiconductor layer 32, such as indium zinc oxide or indium gallium zinc oxide, but not limited thereto. The top surfaces of the gate dielectric layer 28, the first semiconductor layer 30, the second semiconductor layer 32 and the third semiconductor layer 36 are flush with each other and substantially coplanar with the top surface of the dielectric layer 26, but not limited thereto. Thus, the first semiconductor layer 30, the second semiconductor layer 32 and the third semiconductor layer 36, which are sequentially stacked in the horizontal direction D2 or the opposite direction D3 in the through hole OP1, form a channel layer 46 together, and the channel layer 46 and the insulating layer 34 form a channel structure SS together. Those skilled in the art will readily understand that the fabrication of the channel structure SS is not limited to the above-described method, but may be formed by other suitable methods depending on the actual device requirements.

In addition, after forming the channel structure SS, the dielectric layer 38 and the drain electrode DE are continuously formed, so that the drain electrode DE is formed on the channel structure SS and the gate dielectric layer 28 and completely covers the via OP1. That is, the bottom surface of the drain electrode DE is coplanar with the top surface of the channel structure SS. In this operation, the semiconductor device 101 shown in fig. 1 is formed, wherein the second semiconductor layer 32 of the channel layer 46 is in physical contact with the first semiconductor layer 30, the third semiconductor layer 36 and the bottom semiconductor layer 18 at the same time, so as to electrically connect the drain electrode DE and the source electrode SE.

Thus, the fabrication of the semiconductor device 101 in this embodiment is completed. According to the manufacturing method of the present embodiment, a source electrode SE is formed on the dielectric layer 10, and then a gate electrode GE is formed on the source electrode SE. Then, a via OP1 penetrating the gate electrode GE in the vertical direction D1 is formed, and a metal nitride layer 50, a gate dielectric layer 28, a channel structure SS and an insulating layer 34 are sequentially formed in the via OP1. In this arrangement, at least a portion of the channel structure SS is located in the gate electrode GE, and is interposed between the drain electrode DE and the source electrode SE, and is electrically connected to the drain electrode DE and the source electrode SE through the second semiconductor layer 32. And, the metal nitride layer 50 is disposed between the channel structure SS and the gate electrode GE to isolate the gate dielectric layer 28 from directly contacting the gate electrode GE, so as to prevent the dielectric material of the gate dielectric layer 28 from reacting with the metal material of the gate electrode GE and producing a high-resistance product. Thus, the device performance of the gate electrode GE and the channel structure SS is effectively improved by the metal nitride layer 50, thereby improving the operation performance of the semiconductor device 101.

It should be readily understood by those skilled in the art that the semiconductor device and the method for manufacturing the same may have other aspects or may be achieved by other means, and are not limited to the foregoing, so as to meet the needs of actual products. Further embodiments or variations of the semiconductor device of the present utility model and its method of fabrication are described below. In order to simplify the description, the following description mainly aims at the differences of the embodiments, and the details of the differences will not be repeated. In addition, like elements in the various embodiments of the present utility model are labeled with like reference numerals to facilitate cross-reference between the various embodiments.

Referring to fig. 12, fig. 12 is a schematic cross-sectional view of a semiconductor device 103 according to a second embodiment of the present utility model. As shown in fig. 12, the structure of the semiconductor device 103 of the present embodiment is substantially the same as that of the semiconductor device 101 of the first embodiment, and includes a source SE, a bottom dielectric layer 20, a gate GE, a gate dielectric layer 28, a channel structure SS, a drain DE, and the like, which are not repeated herein. The main difference between the semiconductor device 103 of this embodiment and the first embodiment is that the bottom surface of the metal nitride layer 51 is lower than the bottom surface of the gate barrier layer 22, and the source SE is not physically contacted.

In detail, in this embodiment, the through hole OP3 is formed in the vertical direction D1 penetrating the dielectric layer 26, the gate electrode GE and part of the bottom dielectric layer 20, so that the metal nitride layer 51, the gate dielectric layer 28 and the first semiconductor layer 30 formed in the through hole OP3 have a lower bottom surface than the gate barrier layer 22, and the metal nitride layer 51 does not physically contact the source electrode SE. On the other hand, the top surface of the metal nitride layer 51 is also lower than the top surface of the channel structure SS, for example, between the top surface of the channel structure SS and the top surface of the gate electrode GE, and is further covered by the gate dielectric layer 28 without physically contacting the drain electrode DE as well. With this arrangement, the metal nitride layer 51 of the present embodiment also isolates the gate dielectric layer 28 from direct contact with the gate electrode GE, avoiding the reaction of the dielectric material of the gate dielectric layer 28 with the metal material of the gate electrode GE and producing a high-resistance product. Thus, the device performance of the gate electrode GE and the channel structure SS can be effectively improved by the metal nitride layer 51, so that the operation performance of the semiconductor device 103 can be improved.

In summary, the semiconductor device of the present utility model additionally forms a metal nitride layer between the channel structure and the gate, so as to avoid the direct contact between the dielectric material of the gate dielectric layer and the metal material of the gate, which is easy to generate high-resistance products, thereby improving the operation performance of the semiconductor device.

The above description is only of the preferred embodiments of the present utility model and is not intended to limit the present utility model, but various modifications and variations can be made to the present utility model by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present utility model should be included in the protection scope of the present utility model.

Claims (12)

1. A semiconductor device, comprising:

a source electrode;

a drain electrode stacked in a vertical direction with the source electrode;

a gate electrode disposed between the drain electrode and the source electrode in the vertical direction;

a bottom dielectric layer disposed between the source and the gate in the vertical direction;

a channel structure disposed between and electrically connecting the drain and the source in the vertical direction, the channel structure being partially disposed within the gate and including a channel layer and an insulating layer sequentially stacked in a horizontal direction;

a gate dielectric layer disposed between the channel structure and the gate in the horizontal direction; and

and a metal nitride layer disposed between the gate dielectric layer and the gate electrode, wherein a portion of the bottom dielectric layer is sandwiched between the metal nitride layer and the source electrode.

2. The semiconductor device of claim 1, wherein a top surface of the metal nitride layer is lower than a top surface of the channel structure.

3. The semiconductor device of claim 1, wherein a top surface of the metal nitride layer is between a top surface of the channel structure and a top surface of the gate.

4. The semiconductor device of claim 1, wherein the drain, the source, and the gate comprise the same metal material.

5. The semiconductor device of claim 1, wherein the gate further comprises:

a gate layer; and

a gate barrier layer disposed under the gate layer, the gate barrier layer physically contacting the metal nitride layer.

6. The semiconductor device of claim 5, wherein the metal nitride layer and the gate barrier layer comprise the same material.

7. The semiconductor device of claim 5, wherein the metal nitride layer and the gate barrier layer together have an L-shaped cross-section.

8. The semiconductor device of claim 5, wherein a bottom surface of the metal nitride layer is lower than a bottom surface of the gate barrier layer and does not physically contact the source.

9. The semiconductor device of claim 5, wherein a bottom surface of the metal nitride layer is flush with a bottom surface of the gate barrier layer and does not physically contact the source.

10. The semiconductor device of claim 1, wherein the channel layer further comprises:

a first semiconductor layer stacked on the gate dielectric layer and not physically contacting the source electrode; and

and a second semiconductor layer stacked between the first semiconductor layer and the insulating layer, the second semiconductor layer physically contacting the source electrode and the drain electrode.

11. The semiconductor device of claim 10, wherein the first semiconductor layer comprises an I-shaped cross-section and the second semiconductor layer comprises a U-shaped cross-section.

12. The semiconductor device of claim 1, wherein the channel layer comprises indium zinc oxide, aluminum zinc oxide, or indium gallium zinc oxide.