CN220693151U - Multi-wavelength optical signal peak value detection device - Google Patents
Multi-wavelength optical signal peak value detection device Download PDFInfo
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- CN220693151U CN220693151U CN202322386202.1U CN202322386202U CN220693151U CN 220693151 U CN220693151 U CN 220693151U CN 202322386202 U CN202322386202 U CN 202322386202U CN 220693151 U CN220693151 U CN 220693151U
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Abstract
The utility model provides a multi-wavelength optical signal peak value detection device, which comprises an optical filter, an optical filter driver, a photoelectric detector and a main controller, wherein the optical filter driver is connected with the photoelectric detector; the signal output end of the optical filter is connected with the signal input end of the photoelectric detector, and the photoelectric detector, the main controller, the optical filter driver and the optical filter are sequentially connected; the control of the optical filter and the photoelectric detector is combined, the detection and the peak identification process of the optical signal are simplified, the optical filter is driven by the driving voltage generated by the optical filter driver, the driving voltage of the optical filter is strictly controlled to filter out the optical signal with the target wavelength, meanwhile, the number of optical channels and the filtering speed can be increased according to the voltage derivative value of the driving voltage, the photoelectric detector can sample and detect the optical signal at a higher frequency, the signal acquisition range is large, and the device is simple in structure.
Description
Technical Field
The utility model relates to the technical field of spectrum signal detection, in particular to a multi-wavelength optical signal peak value detection device.
Background
In a WDM (Wavelength Division Multiplexing ) communication system, after a multi-wavelength optical signal is demultiplexed by an optical filter, the power of each wavelength signal needs to be detected to further analyze signal data, which needs to be fast and accurate. The optical filter is controlled to filter out the optical signal with the target wavelength, and the signal power at the moment is detected by the photoelectric detector, so that the process needs to be controlled by a fine and rapid control signal, and the optical filter and the optical detector are driven in a coordinated manner. In addition, the detected optical signal may be weak, and the control method of filtering out and detecting the signal is often complex, and a control device or system is needed to combine the two photoelectric devices to further simplify the signal processing, so that the subsequent optical path and the signal processing are facilitated.
The prior art discloses a test device for the frequency response of a photoelectric detector based on a wavelength coding technology, which comprises a light wavelength coding generator, an optical isolator, an optical fiber coupler, an optical delay line, an optical polarization controller, the photoelectric detector to be tested and a beat signal detector, wherein the frequency response of the photoelectric detector can be quickly and intuitively obtained, but the scheme does not completely realize the joint control of an optical filter device and the photoelectric detector.
Disclosure of Invention
In order to solve the problem that the signal processing process of the current spectrum signal detection is complex, the utility model provides a multi-wavelength optical signal peak value detection device, which combines the control of an optical filter and a photoelectric detector, simplifies the detection of the optical signal and the identification process of the peak value, and has a simple structure.
In order to achieve the technical effects, the technical scheme of the utility model is as follows:
a multi-wavelength optical signal peak detection apparatus comprising: the device comprises an optical filter, an optical filter driver, a photoelectric detector and a main controller; the signal output end of the optical filter is connected with the signal input end of the photoelectric detector, the signal output end of the photoelectric detector is connected with the voltage acquisition input end of the main controller, the voltage output end of the main controller is connected with the voltage input end of the optical filter driver, and the voltage output end of the optical filter driver is connected with the voltage driving input end of the optical filter.
In the technical scheme, the control of the optical filter and the photoelectric detector is combined, the detection and the peak identification process of the optical signal are simplified, the optical filter is driven by the driving voltage generated by the optical filter driver, and the voltage fraction value of the optical filter is controlled, so that the number of optical channels is in an ideal range; the photodetector can sample and detect the optical signal at a higher frequency.
Preferably, the main controller is a single chip microcomputer with data processing capability.
Preferably, the optical filter is a fabry-perot tunable filter.
Preferably, the optical filter driver comprises a DAC voltage output circuit and a voltage amplification circuit, wherein the output end of the DAC voltage output circuit is connected with the input end of the voltage amplification circuit, and the output end of the voltage amplification circuit is connected with the optical filter.
The driving voltage of the optical filter is effectively controlled, the driving voltage is ensured to be filtered out of the voltage range at the corresponding wavelength, the fineness of the driving voltage and the voltage output range are further controlled, and the filtering out of the optical channels with more wavelengths is facilitated.
Preferably, the DAC voltage output circuit comprises: the digital-to-analog conversion circuit comprises resistors R1, R2 and R3, capacitors C1, C2, C3 and C4, a digital-to-analog conversion chip DAC8531, a digital isolation chip CA-IS3741HW and a first wiring terminal XY340V-3.81-3P;
the 1 foot of DAC8531, the upper polar plate of C1 and the upper polar plate of C2 are connected with 5V input voltage, the 2 foot of DAC8531 is connected with 2.5V reference voltage, the 3 foot and the 4 foot of DAC8531 are connected with the input end of the voltage amplifying circuit, the 5 foot of DAC8531 is connected with one end of R1, the 6 foot of DAC8531 is connected with one end of R2, the 7 foot of DAC8531 is connected with one end of R3, and the 8 foot of DAC8531, the lower polar plate of C1 and the lower polar plate of C2 are grounded;
the lower polar plates of the pins 1, 7 and C3 of the CA-IS3741HW are connected with 5V input voltage, the upper polar plates of the pins 2, 8 and C3 of the CA-IS3741HW are grounded, the pin 3 of the CA-IS3741HW IS connected with the pin 3 of the XY340V-3.81-3P, the pin 4 of the CA-IS3741HW IS connected with the pin 2 of the XY340V-3.81-3P, the pin 5 of the CA-IS3741HW IS connected with the pin 1 of the XY340V-3.81-3P, the upper polar plates of the pins 9, 15 and C4 of the CA-IS3741HW are grounded, the pins 10, 16 and C4 of the CA-IS3741HW are connected with 5V input voltage, the pin 12 of the CA-IS3741HW IS connected with the other end of the R3, the pin 13 of the CA-IS3741HW IS connected with the other end of the R2, and the pin 14 of the CA-IS3741HW IS connected with the other end of the R1.
The digital-to-analog conversion chip DAC8531 is used for converting the voltage corresponding to the digital signal into analog voltage and outputting the analog voltage, and the output voltage can be in the range of 0-2.5V; meanwhile, the normal transmission of digital signals under electromagnetic interference during large-voltage output IS ensured through a digital isolation chip CA-IS3741 HW;
preferably, the voltage amplifying circuit includes: resistors R4, R5, R6, R7, R8, R9, R10, R11, R12 and R13, capacitors C5, C6, C7, C8, C9, C10 and C11, triodes Q1 and Q2, diodes D1 and D2, an operational amplifier OPA453TA and a second connecting terminal XY128V-B-7.5-2P;
the 1 pin of the OPA453TA is connected with the output end of the DAC voltage output circuit, the 2 pin of the OPA453TA is connected with one end of R4, one end of R5, one end of R8, one end of C9 and one end of C10, the other end of R4 is grounded, the 4 pin of the OPA453TA is connected with the lower polar plate of C5, the lower polar plate of C6 and the-30V power supply voltage, the upper polar plate of C5 and the upper polar plate of C6 are grounded, the 5 pin of the OPA453TA is connected with the upper polar plate of C7, the upper polar plate of C8 and the +30V power supply voltage, the lower polar plate of C7 and the lower polar plate of C8 are grounded, and the 6 pin of the OPA453TA is connected with the anode of D1 and the cathode of D2; the other end of R5 is connected with one end of R6, the other end of R6 is connected with one end of R7, the lower polar plate of C9 is connected with the other end of R7, the lower polar plate of C10, the other end of R8, one end of R9 and one end of R10, the cathode of D1 is connected with one end of R12 and the base of Q1, the other end of R12 and the collector of Q1 are connected with +30V power supply voltage, and the emitter of Q2 is connected with the other end of R9; the anode of the D2 is connected with the base electrode of the Q2 and one end of the R13, the other end of the R13 and the collector electrode of the Q2 are connected with-30V power supply voltage, and the emitter electrode of the Q2 is connected with the other end of the R10; the other end of R11 is connected with the upper pole plate of C11 and the 1 foot of XY128V-B-7.5-2P, the lower pole plate of C11 is connected with the 2 foot of XY128V-B-7.5-2P, and the 1 foot and the 2 foot of XY128V-B-7.5-2P are respectively connected with the anode and the cathode of the optical filter.
Here, the voltage of 0-2.5V of the front output is amplified to the voltage range of 0-30V, and two triodes are used to cooperate with two diodes to eliminate crossover distortion of the output voltage.
Preferably, the photoelectric detector comprises a photoelectric conversion diode, a logarithmic amplification circuit and a low-pass filter circuit, wherein the photoelectric conversion diode PD is connected with the input end of the logarithmic amplification circuit, the output end of the logarithmic amplification circuit is connected with the input end of the low-pass filter circuit, and the output end of the low-pass filter circuit is connected with the voltage acquisition input end of the main controller.
Preferably, the photodiode is a PIN photodiode PD, the dark current is small, and the responsivity is high.
Preferably, the logarithmic amplification circuit includes: resistors R14, R15, R16, R17, R18, capacitors C12, C13, C14, C15, C16, inductance L and logarithmic conversion amplifier ADL5304;
the pins 2, 3, 7 and 8 of the ADL5304 are connected with the pins 2 and R14 of PD, the pin 4 of the ADL5304 is connected with the pin 1 of PD, the pin 5 and 6 of the ADL5304 are connected with the pin 10 of C12, the pin 11 and 15 of the ADL5304 are connected with the analog AGND, the pin 12 of the ADL5304 is connected with the R15 end, the pin 14 of the ADL5304 is connected with the R16 end, the pin 13 of the ADL5304 and the C12 upper plate, the other end of R15 and the other end of R16 are connected with the analog AGND, the pin 16 of the ADL5304 is connected with the C13 lower plate, the pin 17 of the ADL5304 is connected with the C14 upper plate, the pin 18 of the ADL5304 and the C14 lower plate, the one end of R17 is connected with the analog AGND, the pins 20 and 23 of the ADL5304 are connected with the analog AGND, the other end 21 and 22 of the ADL5304 are connected with the other end of the ADL 17 and the other end of the analog AGND, the other end of the ADL5304 is connected with the input end of the analog AG26 of the ADL5304, the input end of the ADL5304 is connected with the input end of the analog AG26, the input end of the analog AG4 is connected with the input end 5303, the input end of the analog AG33 is connected with the input end of the analog AG16, the input end of the analog AG4 is connected with the input end 5305, the input end of the input end 5 is connected with the input end 5, and is connected with the input end 5 is connected with the input end is connected with input end is input.
The photocurrent converted in the PD is logarithmically amplified by the logarithmic-conversion amplifier ADL5304 and is output in the form of a voltage, which is convenient for subsequent processing and calculation.
Preferably, the low-pass filter circuit includes: resistors R19, R20, R21, R22, capacitors C17, C18, C19, C20, and a low noise operational amplifier including a pre-stage amplifier and a post-stage amplifier;
the output end of the logarithmic amplification circuit is connected with one end of R19, the other end of R19 is connected with an upper polar plate of C17 and one end of R20, a lower polar plate of C17 is connected with pins 1, 4 and one end of R21 of a pre-stage amplifier, pin 2 of the pre-stage amplifier is connected with an analog ground AGND, pin 3 of the pre-stage amplifier is connected with the other end of R20 and a lower polar plate of C18, an upper polar plate of C18 is connected with an analog ground AGND, and pin 5 of the pre-stage amplifier is connected with 5V input voltage;
the 1 foot and the 4 foot of the post-stage amplifier are connected with the lower polar plate of C19, the upper polar plate of C19 is connected with the other end of R21 and one end of R22, the 2 foot of the post-stage amplifier is connected with the analog ground AGND, the 3 foot of the post-stage amplifier is connected with the other end of R22, and the 5 foot of the post-stage amplifier is connected with 5V input voltage.
The majority of noise signals in the output voltage signals are filtered out through a low-pass filter circuit, and direct current signals and low-frequency noise which can be used for detection are left; because the noise does not have great influence on most of analog-to-digital conversion, the signal filtered by the filter represents the power value of the optical signal detected by the photoelectric detector at the moment, and the measured optical power value can be obtained after the signal is further calculated and calibrated by the main controller.
Compared with the prior art, the technical scheme of the utility model has the beneficial effects that:
the utility model provides a multi-wavelength optical signal peak value detection device, which comprises an optical filter, an optical filter driver, a photoelectric detector and a main controller, wherein the optical filter driver is connected with the photoelectric detector; the signal output end of the optical filter is connected with the signal input end of the photoelectric detector, and the photoelectric detector, the main controller, the optical filter driver and the optical filter are sequentially connected; the control of the optical filter and the photoelectric detector is combined, the detection and the peak identification process of the optical signal are simplified, the optical filter is driven by the driving voltage generated by the optical filter driver, the driving voltage of the optical filter is strictly controlled to filter out the optical signal with the target wavelength, meanwhile, the number of optical channels and the filtering speed can be increased according to the voltage derivative value of the driving voltage, the photoelectric detector can sample and detect the optical signal at a higher frequency, the signal acquisition range is large, and the device is simple in structure.
Drawings
Fig. 1 is a schematic diagram of an overall multi-wavelength optical signal peak detection device according to an embodiment of the present utility model;
FIG. 2 is a schematic diagram of a DAC voltage output circuit according to an embodiment of the present utility model;
FIG. 3 is a schematic diagram of a voltage amplifying circuit according to an embodiment of the present utility model;
FIG. 4 is a schematic diagram of a logarithmic amplifying circuit according to an embodiment of the present utility model;
fig. 5 is a schematic diagram of a low-pass filter circuit according to an embodiment of the utility model.
Detailed Description
The drawings are for illustrative purposes only and are not to be construed as limiting the present patent;
for better illustrating the present embodiment, some parts of the drawings may be omitted, enlarged or reduced, and do not represent actual dimensions, and the description of the directions of the parts such as "up" and "down" is not limiting of the present patent;
it will be appreciated by those skilled in the art that some well known descriptions in the figures may be omitted.
The technical scheme of the utility model is further described below with reference to the accompanying drawings and examples.
Example 1
As shown in fig. 1, the present embodiment provides a multi-wavelength optical signal peak detection apparatus, including: the device comprises an optical filter, an optical filter driver, a photoelectric detector and a main controller; the signal output end of the optical filter is connected with the signal input end of the photoelectric detector, the signal output end of the photoelectric detector is connected with the voltage acquisition input end of the main controller, the voltage output end of the main controller is connected with the voltage input end of the optical filter driver, and the voltage output end of the optical filter driver is connected with the voltage driving input end of the optical filter.
In the implementation process, the main controller can select any single chip with data processing capability, such as any chip of STMF407 series.
In this embodiment, the optical filter is a fabry-perot tunable filter (FFP-TF), an F-P cavity inside the fabry-perot tunable filter is connected by two half mirrors, one of which is connected to a piezoelectric ceramic, and a certain voltage is applied to the piezoelectric ceramic to change the position of a lens, so that the cavity length of the F-P cavity is changed, and light with different wavelengths is filtered out; therefore, the driving voltage of the optical filter is controlled by the optical filter driver, and the driving voltage is ensured to filter out the voltage range at the corresponding wavelength.
Example 2
Based on embodiment 1, in this embodiment, the optical filter driver includes a DAC voltage output circuit and a voltage amplification circuit, an output terminal of the DAC voltage output circuit is connected to an input terminal of the voltage amplification circuit, and an output terminal of the voltage amplification circuit is connected to the optical filter.
In this embodiment, as shown in fig. 2, the DAC voltage output circuit includes: the resistors R1, R2 and R3, the capacitors C1, C2, C3 and C4, the digital-to-analog conversion chip DAC8531, the digital isolation chip CA-IS3741HW and the connecting terminal XY340V-3.81-3P.
The 1 foot of DAC8531, the upper polar plate of C1 and the upper polar plate of C2 are connected with 5V input voltage, the 2 foot of DAC8531 is connected with 2.5V reference voltage, the 3 foot and the 4 foot of DAC8531 are connected with the input end of a voltage amplifying circuit, the 5 foot of DAC8531 is connected with one end of R1, the 6 foot of DAC8531 is connected with one end of R2, the 7 foot of DAC8531 is connected with one end of R3, and the 8 foot of DAC8531, the lower polar plate of C1 and the lower polar plate of C2 are grounded.
The lower polar plates of the pins 1, 7 and C3 of the CA-IS3741HW are connected with 5V input voltage, the upper polar plates of the pins 2, 8 and C3 of the CA-IS3741HW are grounded, the pin 3 of the CA-IS3741HW IS connected with the pin 3 of the XY340V-3.81-3P, the pin 4 of the CA-IS3741HW IS connected with the pin 2 of the XY340V-3.81-3P, the pin 5 of the CA-IS3741HW IS connected with the pin 1 of the XY340V-3.81-3P, the upper polar plates of the pins 9, 15 and C4 of the CA-IS3741HW are grounded, the pins 10, 16 and C4 of the CA-IS3741HW are connected with 5V input voltage, the pin 12 of the CA-IS3741HW IS connected with the other end of the R3, the pin 13 of the CA-IS3741HW IS connected with the other end of the R2, and the pin 14 of the CA-IS3741HW IS connected with the other end of the R1.
In this embodiment, as shown in fig. 3, the voltage amplifying circuit includes: resistors R4, R5, R6, R7, R8, R9, R10, R11, R12 and R13, capacitors C5, C6, C7, C8, C9, C10 and C11, triodes Q1 and Q2, diodes D1 and D2, an operational amplifier OPA453TA and a wiring terminal XY128V-B-7.5-2P.
The 1 pin of the OPA453TA is connected with the output end of the DAC voltage output circuit, the 2 pin of the OPA453TA is connected with one end of R4, one end of R5, one end of R8, one end of C9 and one end of C10, the other end of R4 is grounded, the 4 pin of the OPA453TA is connected with the lower polar plate of C5, the lower polar plate of C6 and the-30V power supply voltage, the upper polar plate of C5 and the upper polar plate of C6 are grounded, the 5 pin of the OPA453TA is connected with the upper polar plate of C7, the upper polar plate of C8 and the +30V power supply voltage, the lower polar plate of C7 and the lower polar plate of C8 are grounded, and the 6 pin of the OPA453TA is connected with the anode of D1 and the cathode of D2; the other end of R5 is connected with one end of R6, the other end of R6 is connected with one end of R7, the lower polar plate of C9 is connected with the other end of R7, the lower polar plate of C10, the other end of R8, one end of R9 and one end of R10, the cathode of D1 is connected with one end of R12 and the base of Q1, the other end of R12 and the collector of Q1 are connected with +30V power supply voltage, and the emitter of Q2 is connected with the other end of R9; the anode of the D2 is connected with the base electrode of the Q2 and one end of the R13, the other end of the R13 and the collector electrode of the Q2 are connected with-30V power supply voltage, and the emitter electrode of the Q2 is connected with the other end of the R10; the other end of R11 is connected with the upper pole plate of C11 and the 1 foot of XY128V-B-7.5-2P, the lower pole plate of C11 is connected with the 2 foot of XY128V-B-7.5-2P, and the 1 foot and the 2 foot of XY128V-B-7.5-2P are respectively connected with the anode and the cathode of the optical filter.
In the actual operation process, the driving voltage generated by the optical filter driver in this embodiment is used to drive the FFP-type optical filter to filter out the optical signal with the target wavelength, and adjust the voltage division value to control the filtering speed and increase the optical channel number.
Example 3
In this embodiment, the photodetector includes a photodiode, a logarithmic amplifying circuit, and a low-pass filter circuit, where the photodiode PD is connected to an input end of the logarithmic amplifying circuit, an output end of the logarithmic amplifying circuit is connected to an input end of the low-pass filter circuit, and an output end of the low-pass filter circuit is connected to a voltage acquisition input end of the main controller.
In this embodiment, the photoelectric conversion PD uses a PIN photodiode of sensitive light technology, and its spectrum range is 800-1700nm, dark current is small, and responsivity is high.
As shown in fig. 4, the logarithmic amplification circuit includes: resistors R14, R15, R16, R17, R18, capacitors C12, C13, C14, C15, C16, inductance L, and logarithmic conversion amplifier ADL5304.
The pins 2, 3, 7 and 8 of the ADL5304 are connected with the pins 2 and R14 of PD, the pin 4 of the ADL5304 is connected with the pin 1 of PD, the pin 5 and 6 of the ADL5304 are connected with the pin 10 of C12, the pin 11 and 15 of the ADL5304 are connected with the analog AGND, the pin 12 of the ADL5304 is connected with the R15 end, the pin 14 of the ADL5304 is connected with the R16 end, the pin 13 of the ADL5304 and the C12 upper plate, the other end of R15 and the other end of R16 are connected with the analog AGND, the pin 16 of the ADL5304 is connected with the C13 lower plate, the pin 17 of the ADL5304 is connected with the C14 upper plate, the pin 18 of the ADL5304 and the C14 lower plate, the one end of R17 is connected with the analog AGND, the pins 20 and 23 of the ADL5304 are connected with the analog AGND, the other end 21 and 22 of the ADL5304 are connected with the other end of the ADL 17 and the other end of the analog AGND, the other end of the ADL5304 is connected with the input end of the analog AG26 of the ADL5304, the input end of the ADL5304 is connected with the input end of the analog AG26, the input end of the analog AG4 is connected with the input end 5303, the input end of the analog AG33 is connected with the input end of the analog AG16, the input end of the analog AG4 is connected with the input end 5305, the input end of the input end 5 is connected with the input end 5, and is connected with the input end 5 is connected with the input end is connected with input end is input.
As shown in fig. 5, the low-pass filter circuit includes: resistors R19, R20, R21, R22, capacitors C17, C18, C19, C20, and low noise operational amplifier OPA325, the low noise operational amplifier OPA325 including a pre-stage amplifier and a post-stage amplifier.
The output end of the logarithmic amplification circuit is connected with one end of R19, the other end of R19 is connected with an upper polar plate of C17 and one end of R20, a lower polar plate of C17 is connected with 1 pin, 4 pin and one end of R21 of a pre-stage amplifier, 2 pin of the pre-stage amplifier is connected with an analog ground AGND, 3 pin of the pre-stage amplifier is connected with the other end of R20 and a lower polar plate of C18, the upper polar plate of C18 is connected with an analog ground AGND, and 5 pin of the pre-stage amplifier is connected with 5V input voltage.
The 1 foot and the 4 foot of the post-stage amplifier are connected with the lower polar plate of C19, the upper polar plate of C19 is connected with the other end of R21 and one end of R22, the 2 foot of the post-stage amplifier is connected with the analog ground AGND, the 3 foot of the post-stage amplifier is connected with the other end of R22, and the 5 foot of the post-stage amplifier is connected with 5V input voltage.
In the actual operation process, most of noise signals in the output voltage signals are filtered by the low-pass filter circuit, and direct current signals and low-frequency noise which can be used for detection are reserved. Because the noise does not have great influence on most of analog-to-digital conversion, the signal filtered by the filter represents the power value of the optical signal detected by the photoelectric detector at the moment, and the measured optical power value can be obtained after the signal is further calculated and calibrated by the main controller.
In the embodiment, the photoelectric detector can sample and detect the optical signal at a higher frequency, the signal acquisition range is large, and weak optical signals in the range of-60 to 0dBm can be detected.
The positional relationship described in the drawings is for illustrative purposes only and is not to be construed as limiting the present patent.
In addition, if there is a description of "first", "second", etc. in the embodiments of the present utility model, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", etc. may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present utility model.
It is to be understood that the above examples of the present utility model are provided by way of illustration only and are not intended to limit the scope of the utility model. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. Any modification, equivalent replacement, improvement, etc. which come within the spirit and principles of the utility model are desired to be protected by the following claims.
Claims (10)
1. A multi-wavelength optical signal peak detection apparatus, comprising: the device comprises an optical filter, an optical filter driver, a photoelectric detector and a main controller; the signal output end of the optical filter is connected with the signal input end of the photoelectric detector, the signal output end of the photoelectric detector is connected with the voltage acquisition input end of the main controller, the voltage output end of the main controller is connected with the voltage input end of the optical filter driver, and the voltage output end of the optical filter driver is connected with the voltage driving input end of the optical filter.
2. The peak detector of claim 1, wherein the master controller is a single-chip microcomputer.
3. The multi-wavelength optical signal peak detection device according to claim 1, wherein the optical filter is a fabry-perot tunable filter.
4. A multi-wavelength optical signal peak detection device according to claim 3, wherein the optical filter driver comprises a DAC voltage output circuit and a voltage amplification circuit, the output terminal of the DAC voltage output circuit is connected to the input terminal of the voltage amplification circuit, and the output terminal of the voltage amplification circuit is connected to the optical filter.
5. The multi-wavelength optical signal peak detection device according to claim 4, wherein the DAC voltage output circuit comprises: the resistor R1, R2 and R3, the capacitor C1, C2, C3 and C4, the digital-to-analog conversion chip, the digital isolation chip and the first wiring terminal;
the upper polar plate of the digital-to-analog conversion chip 1 and the upper polar plate of the digital-to-analog conversion chip C2 are connected with input voltage, the pin 2 of the digital-to-analog conversion chip 2 is connected with reference voltage, the pin 3 and the pin 4 of the digital-to-analog conversion chip are connected with the input end of the voltage amplifying circuit, the pin 5 of the digital-to-analog conversion chip is connected with one end of the digital-to-analog conversion chip R1, the pin 6 of the digital-to-analog conversion chip is connected with one end of the digital-to-analog conversion chip R2, the pin 7 of the digital-to-analog conversion chip is connected with one end of the digital-to-analog conversion chip R3, and the lower polar plate of the digital-to-analog conversion chip 8 and the lower polar plate of the digital-to-analog conversion chip C1 are grounded with the lower polar plate of the digital-to-analog conversion chip C2;
the input voltage is connected to the lower polar plate of 1 foot, 7 feet and C3 of digital isolation chip, and the upper polar plate of 2 feet, 8 feet and C3 of digital isolation chip is grounded, and the 3 feet of digital isolation chip are connected the 3 feet of first binding post, and the 2 feet of first binding post are connected to the 4 feet of digital isolation chip, and the 1 foot of first binding post is connected to the 5 feet of digital isolation chip, and the upper polar plate of 9 feet, 15 feet and C4 of digital isolation chip is grounded, and input voltage is connected to the lower polar plate of 10 feet, 16 feet and C4 of digital isolation chip, and the other end of R3 is connected to the 12 feet of digital isolation chip, and the other end of R2 is connected to the 13 feet of digital isolation chip, and the other end of R1 is connected to the 14 feet of digital isolation chip.
6. The multi-wavelength optical signal peak detection device according to claim 5, wherein the voltage amplifying circuit includes: resistors R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, capacitors C5, C6, C7, C8, C9, C10, C11, transistors Q1, Q2, diodes D1, D2, an operational amplifier, and a second connection terminal;
the 1 pin of the operational amplifier is connected with the output end of the DAC voltage output circuit, the 2 pin of the operational amplifier is connected with one end of R4, one end of R5, one end of R8, one end of C9 and one end of C10, the other end of R4 is grounded, the 4 pin of the operational amplifier is connected with the lower polar plate of C5, the lower polar plate of C6 and-30V power supply voltage, the upper polar plate of C5 and the upper polar plate of C6 are grounded, the 5 pin of the operational amplifier is connected with the upper polar plate of C7, the upper polar plate of C8 and +30V power supply voltage, the lower polar plate of C7 and the lower polar plate of C8 are grounded, and the 6 pin of the operational amplifier is connected with the anode of D1 and the cathode of D2; the other end of R5 is connected with one end of R6, the other end of R6 is connected with one end of R7, the lower polar plate of C9 is connected with the other end of R7, the lower polar plate of C10, the other end of R8, one end of R9 and one end of R10, the cathode of D1 is connected with one end of R12 and the base of Q1, the other end of R12 and the collector of Q1 are connected with +30V power supply voltage, and the emitter of Q2 is connected with the other end of R9; the anode of the D2 is connected with the base electrode of the Q2 and one end of the R13, the other end of the R13 and the collector electrode of the Q2 are connected with-30V power supply voltage, and the emitter electrode of the Q2 is connected with the other end of the R10; the other end of R11 is connected with the upper polar plate of C11 and the 1 pin of the second binding post, and the lower polar plate of C11 is connected with the 2 pin of the second binding post, the 1 pin and the 2 pin of the second binding post are connected with the positive pole and the negative pole of the optical filter respectively.
7. The peak detection device for multi-wavelength optical signals according to claim 1, wherein the photodetector comprises a photoelectric conversion diode, a logarithmic amplification circuit and a low-pass filter circuit, the photoelectric conversion diode PD is connected to an input end of the logarithmic amplification circuit, an output end of the logarithmic amplification circuit is connected to an input end of the low-pass filter circuit, and an output end of the low-pass filter circuit is connected to a voltage acquisition input end of the main controller.
8. The apparatus according to claim 7, wherein the photodiode is a PIN photodiode PD.
9. The peak detection unit of claim 8, wherein the logarithmic amplification circuit comprises: resistors R14, R15, R16, R17, R18, capacitors C12, C13, C14, C15, C16, inductance L and logarithmic conversion amplifier;
the 2, 3, 7 and 8 feet of the logarithmic conversion amplifier are connected with the 2 feet of PD and one end of R14, the 4 feet of the logarithmic conversion amplifier are connected with the 1 feet of PD, the 5 feet and 6 feet of the logarithmic conversion amplifier are connected with the lower polar plate of C12, the 11 feet and 15 feet of the logarithmic conversion amplifier and the upper polar plate of C13 are connected with the analog ground AGND, the 12 feet of the logarithmic conversion amplifier are connected with one end of R15, the 14 feet of the logarithmic conversion amplifier are connected with one end of R16, the 13 feet of the logarithmic conversion amplifier and the upper polar plate of C12, the other end of R15 and the other end of R16 are connected with the analog ground AGND, the 16 feet of the logarithmic conversion amplifier are connected with the lower polar plate of C13, the 17 feet of the logarithmic conversion amplifier are connected with the upper polar plate of C14, the input end of the low-pass filter circuit is connected with the other end of the R17, the 24 pin, the 26 pin and the 27 pin of the logarithmic conversion amplifier, the 28 pin of the logarithmic conversion amplifier is connected with one end of the R18, the other end of the R18 is connected with the upper polar plate of the C16, the lower polar plate of the C16 is connected with the analog ground AGND, the 29 pin of the logarithmic conversion amplifier is connected with one end of the L and the upper polar plate of the C15, the other end of the L is connected with the input voltage, the lower polar plate of the C15 is connected with the analog ground AGND, the 30 pin of the logarithmic conversion amplifier is connected with the other end of the R14, the 31 pin and the 32 pin of the logarithmic conversion amplifier are connected, and the 33 pin of the logarithmic conversion amplifier is connected with the analog ground AGND.
10. The multi-wavelength optical signal peak detection device according to claim 9, wherein the low-pass filter circuit includes: resistors R19, R20, R21, R22, capacitors C17, C18, C19, C20, and a low noise operational amplifier including a pre-stage amplifier and a post-stage amplifier;
the output end of the logarithmic amplification circuit is connected with one end of R19, the other end of R19 is connected with an upper polar plate of C17 and one end of R20, a lower polar plate of C17 is connected with pins 1, 4 and one end of R21 of a pre-stage amplifier, pin 2 of the pre-stage amplifier is connected with an analog ground AGND, pin 3 of the pre-stage amplifier is connected with the other end of R20 and a lower polar plate of C18, an upper polar plate of C18 is connected with an analog ground AGND, and pin 5 of the pre-stage amplifier is connected with an input voltage;
the 1 foot and the 4 foot of the post-stage amplifier are connected with the lower polar plate of C19, the upper polar plate of C19 is connected with the other end of R21 and one end of R22, the 2 foot of the post-stage amplifier is connected with the analog ground AGND, the 3 foot of the post-stage amplifier is connected with the other end of R22, and the 5 foot of the post-stage amplifier is connected with the input voltage.
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