CN220691685U

CN220691685U - Shift register, grid driving circuit and display panel

Info

Publication number: CN220691685U
Application number: CN202321348189.4U
Authority: CN
Inventors: 杨博; 赵中满
Original assignee: Yungu Guan Technology Co Ltd
Current assignee: Yungu Guan Technology Co Ltd
Priority date: 2023-05-30
Filing date: 2023-05-30
Publication date: 2024-03-29
Anticipated expiration: 2033-05-30

Abstract

The utility model discloses a shift register, a grid driving circuit and a display panel, wherein the shift register comprises a shift signal generating module, a driving control module and a voltage stabilizing module, the shift signal generating module is used for outputting a shift signal to the input end of the driving control module, the driving control module is used for sequentially outputting driving signals from the output end of the driving control module based on the shift signal and the control signal, and the voltage stabilizing module is used for stabilizing the level of the driving signals output by the driving control module. The driving control module comprises a plurality of signal output units, each signal output unit is controlled by two control signals, and the control signals corresponding to different signal output units are different. The technical scheme provided by the embodiment can enable one shift register to output multiple paths of driving signals so as to drive multiple grid lines. In the grid driving circuit applying the shift register, the number of the shift register can be greatly reduced, so that the wiring space is reduced, and the narrow frame of the panel is facilitated to be realized.

Description

Shift register, grid driving circuit and display panel

Technical Field

The present utility model relates to the field of display technologies, and in particular, to a shift register, a gate driving circuit, and a display panel.

Background

Along with the development trend of extremely comprehensive screens, the frames of the display panels are narrower, the screen occupation ratio is higher, and more extremely experience is brought to consumers.

The display panel generally includes a gate driving circuit for providing a gate driving signal to the pixel circuit. However, the existing gate driving circuit occupies more space, which hinders the development requirement of the display panel for narrow frame.

Disclosure of Invention

The utility model provides a shift register, a gate driving circuit and a display panel, which are used for reducing the occupied space of the gate driving circuit, thereby realizing the effect of narrow frame of the display panel applying the gate driving circuit.

According to an aspect of the present utility model, there is provided a shift register including a shift signal generating module and a driving control module;

the output end of the shift signal generating module is connected with the input end of the driving control module, and the shift signal generating module is used for generating a shift signal and transmitting the shift signal to the input end of the driving control module;

the driving control module comprises a plurality of signal output units, the input end of each signal output unit is connected with the input end of the driving control module, the output end of one signal output unit is connected with one output end of the driving control module, and the plurality of signal output units are used for sequentially outputting corresponding driving signals according to the shifting signals and the control signals; each signal output unit is controlled by two different control signals, the two control signals corresponding to different signal output units are different, and the signal output unit is configured to:

The signal output unit outputs the active level of the driving signal when one control signal is the active level and the other control signal is the inactive level in the period of the active level of the shift signal, and outputs the inactive level of the driving signal when the levels of both control signals are inverted;

the driving control device comprises a driving control module, a plurality of voltage stabilizing modules and a control module, wherein each output end of the driving control module is connected with one voltage stabilizing module, and the voltage stabilizing modules are used for stabilizing the level of the driving signal.

Optionally, the driving control module includes a first signal output unit and a second signal output unit;

the first input end of the first signal output unit is connected with the output end of the shift signal generation module, the second input end of the first signal output unit is connected with a first voltage signal wire, the first control end of the first signal output unit is connected with a first control signal wire, the second control end of the first signal output unit is connected with a second control signal wire, and the output end of the first signal output unit is used as an output end of the drive control module;

the first input end of the second signal output unit is connected with the output end of the shift signal generating module, the second input end of the second signal output unit is connected with the first voltage signal line, the first control end of the second signal output unit is connected with the third control signal line, the second control end of the second signal output unit is connected with the fourth control signal line, and the output end of the second signal output unit is used as the other output end of the driving control module.

Optionally, the first signal output unit includes a first transistor and a second transistor, where a first pole of the first transistor is a first input end of the first signal output unit, a second pole of the first transistor is an output end of the first signal output unit, and a gate of the first transistor is a first control end of the first signal output unit; the first electrode of the second transistor is a second input end of the first signal output unit, the second electrode of the second transistor is connected with the second electrode of the first transistor, and the gate of the second transistor is a second control end of the first signal output unit;

and/or the number of the groups of groups,

the second signal output unit comprises a third transistor and a fourth transistor, a first electrode of the third transistor is a first input end of the second signal output unit, a second electrode of the third transistor is an output end of the second signal output unit, and a gate of the third transistor is a second control end of the first signal output unit; the first electrode of the fourth transistor is a second input end of the second signal output unit, the second electrode of the fourth transistor is connected with the second electrode of the third transistor, and the gate of the fourth transistor is a second control end of the second signal output unit.

Optionally, in the period of the active level of the shift signal, the active level of the third control signal on the third control signal line is subsequent to the active level of the first control signal on the first control signal line, and the active level of the third control signal does not overlap with the active level of the first control signal;

the active level of the second control signal on the second control signal line is subsequent to the active level of the first control signal and prior to the active level of the third control signal, the active level of the second control signal overlapping the active level of the third control signal.

Optionally, the first voltage signal on the first voltage signal line is a direct current voltage signal.

Optionally, the shift signal generating module includes a first input module, a second input module, a first output module, and a second output module; the output end of the first input module is connected with the control end of the first output module, and the first input module is used for responding to a first clock signal on a first clock signal line and transmitting a second voltage signal on a second voltage signal line of the input end of the first input module to the control end of the first output module;

The input end of the second input module is used as a trigger signal input end of the shift signal generating module and used for controlling the potential of the control end of the second output module;

the output end of the first output module and the output end of the second output module are both connected to the output end of the shift signal generating module, the first output module is used for outputting a first signal according to the electric potential of the control end of the first output module, and the second output module is used for outputting a second signal according to the electric potential of the control end of the second output module;

preferably, the first input module includes a fifth transistor, the second input module includes a sixth transistor, the first output module includes a seventh transistor and a first capacitor, and the second output module includes an eighth transistor and a second capacitor;

the gate of the fifth transistor is connected to the first clock signal line, the first pole of the fifth transistor is used as the input end of the first input module, the second pole of the fifth transistor is connected to the gate of the seventh transistor, the first pole of the seventh transistor is connected to the first voltage signal line, the second pole of the seventh transistor is used as the output end of the first output module, and the first capacitor is connected between the first pole and the gate of the seventh transistor;

The gate of the sixth transistor is connected to the first clock signal line, the first pole of the sixth transistor is used as the input end of the second input module, the second pole of the sixth transistor is connected to the gate of the eighth transistor, the first pole of the eighth transistor is connected to the second clock signal line, the second pole of the eighth transistor is connected to the second pole of the seventh transistor, and the second capacitor is connected between the gate of the eighth transistor and the second pole.

Optionally, the shift signal generating module further includes a first output control module and a second output control module, an output end of the first output control module is connected with a control end of the first output module, and an output end of the second output control module is connected with a control end of the second output module;

preferably, the first output control module includes a ninth transistor, a gate of the ninth transistor is connected to the output end of the second input module, a first pole of the ninth transistor is connected to the first clock signal line, and a second pole of the ninth transistor is the output end of the first output control module;

the second output control module comprises a tenth transistor and an eleventh transistor, wherein a grid electrode of the tenth transistor is connected with the control end of the first output module, a first electrode of the tenth transistor is connected with the first voltage signal line, a second electrode of the tenth transistor is connected with the first electrode of the eleventh transistor, a second electrode of the eleventh transistor is an output end of the second output control module, and a grid electrode of the eleventh transistor is connected with the second clock signal line.

The voltage stabilizing module comprises a first voltage stabilizing unit and a second voltage stabilizing unit, wherein the first voltage stabilizing unit comprises a first sub-transistor and a second sub-transistor, and the second voltage stabilizing unit comprises a third sub-transistor and a fourth sub-transistor;

the grid electrode of the first sub-transistor and the grid electrode of the second sub-transistor are connected together to serve as the control end of the first voltage stabilizing unit to be connected with the output end corresponding to the driving control module, the first pole of the first sub-transistor serves as the first input end of the first voltage stabilizing unit to be connected with the first voltage signal line, the second pole of the first sub-transistor and the second pole of the second sub-transistor are connected together to serve as the output end of the first voltage stabilizing unit, and the first pole of the second sub-transistor serves as the second input end of the first voltage stabilizing unit to be connected with the second voltage signal line;

the grid electrode of the third sub-transistor and the grid electrode of the fourth sub-transistor are connected together to serve as the control end of the second voltage stabilizing unit to be connected with the output end of the first voltage stabilizing unit, the first electrode of the third sub-transistor serves as the first input end of the second voltage stabilizing unit to be connected with the first voltage signal line, the second electrode of the third sub-transistor and the second electrode of the fourth sub-transistor are connected together to serve as the output end of the second voltage stabilizing unit to output a stabilized driving signal, and the first electrode of the fourth sub-transistor is connected with the second voltage signal line.

According to another aspect of the present utility model, there is provided a gate driving circuit including a plurality of shift registers provided in any of the embodiments of the present utility model, the plurality of shift registers being cascade-connected; in the plurality of cascaded shift registers, the trigger signal accessed by the shift register at the next stage is provided by the output end of the shift signal generating module in the shift register at the previous stage.

According to another aspect of the present utility model, there is provided a display panel including the gate driving circuit provided by any of the embodiments of the present utility model.

Optionally, the device further comprises a plurality of scanning lines extending along a first direction, wherein the scanning lines are sequentially arranged along a second direction, and the first direction and the second direction are intersected; the gate driving circuit is used for sequentially transmitting driving signals to the scanning lines.

According to the technical scheme, the shift register comprises a shift signal generation module and a drive control module, wherein the output end of the shift signal generation module is connected with the input end of the drive control module, and the shift signal generation module is used for generating a shift signal and transmitting the shift signal to the input end of the drive control module. The driving control module comprises a plurality of output ends, and the driving control module is used for sequentially outputting driving signals from the output ends based on the shifting signals and the control signals. The driving control module comprises a plurality of signal output units, each signal output unit is controlled by two different control signals, and the two control signals corresponding to the different signal output units are different. According to the technical scheme provided by the embodiment, one driving control module is additionally arranged for each shift register, so that one shift register can output multiple paths of driving signals so as to drive multiple grid lines (scanning lines). In the grid driving circuit applying the shift register, the number of the shift register can be greatly reduced, so that the wiring space of the grid driving circuit can be reduced, and the narrow frame of the panel can be realized. Meanwhile, the driving signals output by each signal output unit are amplified by the voltage stabilizing module, so that stable output of the shift register is realized, driving capability of the grid driving circuit under high load is improved, and display effect of a display panel applying the grid driving circuit is improved.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the utility model or to delineate the scope of the utility model. Other features of the present utility model will become apparent from the description that follows.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present utility model, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a shift register according to an embodiment of the present utility model;

FIG. 2 is a schematic diagram of another shift register according to an embodiment of the present utility model;

FIG. 3 is a schematic diagram of another shift register according to an embodiment of the present utility model;

FIG. 4 is a timing control waveform diagram of a driving control module according to an embodiment of the present utility model;

fig. 5 is a schematic structural diagram of a shift signal generating module according to an embodiment of the present utility model;

Fig. 6 is a schematic structural diagram of another shift signal generating module according to an embodiment of the present utility model;

FIG. 7 is a schematic diagram of another shift register according to an embodiment of the present utility model;

FIG. 8 is a timing control waveform diagram of a shift register according to an embodiment of the present utility model;

fig. 9 is a schematic structural diagram of another shift signal generating module according to an embodiment of the utility model;

fig. 10 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present utility model;

fig. 11 is a schematic structural diagram of a display panel according to an embodiment of the utility model.

Detailed Description

In order that those skilled in the art will better understand the present utility model, a technical solution in the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present utility model, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present utility model without making any inventive effort, shall fall within the scope of the present utility model.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present utility model and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the utility model described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion.

Fig. 1 is a schematic structural diagram of a shift register according to an embodiment of the present utility model, and referring to fig. 1, the shift register 100 includes a shift signal generating module 10 and a driving control module 20; the output end OUT of the shift signal generating module 10 is connected with the input end of the driving control module 20, and the shift signal generating module 10 is used for generating a shift signal Sout and transmitting the shift signal Sout to the input end of the driving control module 20; the driving control module 20 includes a plurality of output terminals, and the driving control module 20 is configured to sequentially output the driving signal Gout from the output terminals thereof based on the shift signal Sout and the control signal (Mux 1, mux2 … … Mux (m)).

The driving control module 20 includes a plurality of signal output units 21, each signal output unit 21 is controlled by two different control signals, and the control signals corresponding to the different signal output units 21 are different.

Specifically, the output terminal OUT of the shift signal generating module 10 is connected to the input terminal of the driving control module 20 so as to transmit the same shift signal Sout to the plurality of signal output units 21 in the driving control module 20. The driving control module 20 outputs corresponding driving signals from its output terminal in a time-sharing manner under the action of the shift signal Sout and the corresponding control signal. For example, the first signal output unit 21 outputs a first driving signal G1 from a first output terminal thereof based on the shift signal Sout by the first control signal Mux1 and the second control signal Mux2, the first driving signal G1 being for driving the first row of pixel circuits. The second signal output unit 21 outputs a second driving signal G2 from a second output terminal thereof based on the shift signal Sout by the third control signal Mux3 and the fourth control signal Mux4, the second driving signal G2 being used to drive the second row of pixel circuits … ….

Each driving signal is sequentially output from the corresponding output end in a time-sharing manner, so that the shift register 100 can sequentially transmit the driving signals to the corresponding pixel rows, and thus progressive scanning of the pixel circuits is realized.

In the present embodiment, the signal output unit 21 is configured to: in a period of shifting the active level of the signal Sout, when one control signal is an active level and the other control signal is an inactive level, the signal output unit 21 outputs the active level of the driving signal Gout, and when the levels of both control signals are inverted, the signal output unit 21 outputs the inactive level of the driving signal Gout.

The effective level of the shift signal Sout refers to an effective phase of the shift signal Sout, in which the driving signals output by the signal output units 21 are also effective signals, and the respective signal output units 21 sequentially output the corresponding driving signals (G1, G2 … … Gn). Here, each signal output unit 21 is controlled by two different control signals, taking the first signal output unit 21 as an example, in the active level of the shift signal Sout, when the level of the first control signal Mux1 is the active level and the level of the second control signal Mux2 is the inactive level, the first signal output unit 21 is turned on in response to the first control signal Mux1, and the low level of the shift signal Sout is output from the output terminal of the signal output unit 21 as the active level of the first driving signal G1; when the level of the first control signal Mux1 transitions to the inactive level and the level of the second control signal Mux2 transitions to the inactive level, the first signal output unit 21 is turned on in response to the second control signal Mux2 and outputs a high level signal as the inactive level of the first driving signal G1.

Further, after outputting the low level of the first driving signal G1 and when the high level of the first driving signal G1 is on the fly, the second signal output unit 21 can output the effective level of the second driving signal G2, so as to realize that the driving control module 20 splits the shift signal Sout into multiple groups of driving signals to be sequentially output.

In this embodiment, the shift register 100 further includes a voltage stabilizing module 40, and each output end of the driving control module 20 is connected to the voltage stabilizing module 40, that is, each output end of the signal output unit 21 is connected to the voltage stabilizing module 40. The voltage stabilizing module 40 is configured to amplify the current of the driving signal Gn output by the signal output unit 21, further stabilize the level of the driving signal Gn, and output the stabilized driving signal Gn', so as to prevent the driving signal Gn from being attenuated and affecting the driving capability, thereby improving the driving capability of the shift register 100.

The shift register provided by the embodiment comprises a shift signal generating module and a driving control module, wherein the output end of the shift signal generating module is connected with the input end of the driving control module, and the shift signal generating module is used for generating a shift signal and transmitting the shift signal to the input end of the driving control module. The driving control module comprises a plurality of output ends, and the driving control module is used for sequentially outputting driving signals from the output ends based on the shifting signals and the control signals. The driving control module comprises a plurality of signal output units, each signal output unit is controlled by two different control signals, and the two control signals corresponding to the different signal output units are different. According to the technical scheme provided by the embodiment, one driving control module is additionally arranged for each shift register, so that one shift register can output multiple paths of driving signals so as to drive multiple grid lines (scanning lines). In the grid driving circuit applying the shift register, the number of the shift register can be greatly reduced, so that the wiring space of the grid driving circuit can be reduced, and the narrow frame of the panel can be realized. Meanwhile, the driving signals output by each signal output unit are amplified by the voltage stabilizing module, so that stable output of the shift register is realized, driving capability of the grid driving circuit under high load is improved, and display effect of a display panel applying the grid driving circuit is improved.

One driving period of the shift register 100 is a period of an active level of the shift signal Sout, and the driving control module 20 outputs a multi-path driving signal during one driving period of the shift register 100. The duration of the effective level of each driving signal is related to the duration of the driving period and the number of the driving signals, and under the condition that the driving period is fixed, the duration of the effective level of each driving signal is correspondingly reduced when one driving signal is output. In order to ensure the validity of each driving signal, it is preferable to output two driving signals.

Fig. 2 is a schematic structural diagram of another shift register according to an embodiment of the present utility model, and referring to fig. 2, based on the above technical solution, optionally, the driving control module 20 includes a first signal output unit 210 and a second signal output unit 220. Here, the drive control module 20 includes two outputs. A first input end of the first signal output unit 210 is connected with an output end OUT of the shift signal generating module 10, a second input end of the first signal output unit 210 is connected with a first voltage signal V1, a first control end of the first signal output unit 210 is connected with a first control signal Mux1, namely, a first control end of the first signal output unit 210 is connected with a first control signal line, and a second control end of the first signal output unit 210 is connected with a second control signal Mux2, namely, a second control end of the first signal output unit 210 is connected with a second control signal line; the output end of the first signal output unit 210 is used as an output end of the driving control module 20; the first input end of the second signal output unit 220 is connected with the output end OUT of the shift signal generating module 10, the second input end of the second signal output unit 220 is connected with the first voltage signal V1, the first control end of the second signal output unit 220 is connected with the third control signal Mux3, the second control end of the second signal output unit 220 is connected with the fourth control signal Mux4, namely, the first control end of the second signal output unit 220 is connected with the third control signal line, the second control end of the second signal output unit 220 is connected with the fourth control signal line, and the output end of the second signal output unit 220 serves as the other output end of the driving control module 20.

In this embodiment, the first input end of the first signal output unit 210 and the first input end of the second signal output unit 220 are both connected to the shift signal Sout output by the shift signal generating module 10, and the second input end of the first signal output unit 210 and the second input end of the second signal output unit 220 are both connected to the first voltage signal V1, where the first voltage signal V1 is a dc voltage signal and may be provided by the first voltage signal line L1. If the effective level of the shift signal Sout is low, the first voltage signal V1 is a high level signal; if the active level of the shift signal Sout is high, the first voltage signal V1 is low.

As an alternative implementation of the present embodiment, the first signal output unit 210 and the second signal output unit 220 may include transistors. Fig. 3 is a schematic structural diagram of another shift register according to an embodiment of the present utility model, referring to fig. 2 and 3, based on the above technical solution, the first signal output unit 210 includes a first transistor M1 and a second transistor M2, a first input terminal of the first signal output unit 210 is a first terminal of the first transistor M1, a second terminal of the first transistor M1 is an output terminal of the first signal output unit 210, and a gate of the first transistor M1 is connected to the first control signal Mux1; the first transistor M2 is a second input terminal of the first signal output unit 210, the second pole of the second transistor M2 is connected to the second pole of the first transistor M1, and the gate of the second transistor M2 is connected to the second control signal Mux2.

The second signal output unit 220 includes a third transistor M3 and a fourth transistor M4, where a first end of the third transistor M3 is a first input end of the second signal output unit 220, a second end of the third transistor M3 is an output end of the second signal output unit 220, and a gate of the third transistor M3 is connected to a third control signal Mux3; the first electrode of the fourth transistor M4 is a second input terminal of the second signal output unit 220, the second electrode of the fourth transistor M4 is connected to the second electrode of the third transistor M3, and the gate of the fourth transistor M4 is connected to the fourth control signal Mux4.

The first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 are P-type transistors. The active level of the shift signal Sout is low, and the first voltage signal V1 is the high level signal VGH.

It should be understood that the above scheme is only an alternative implementation of the present embodiment, and in other embodiments, other structures or signals may be used.

Fig. 4 is a timing control waveform diagram of a driving control module according to an embodiment of the present utility model, which can be used to control the driving control module shown in fig. 3 to work. Referring to fig. 4, within the active level of the shift signal Sout, the active level of the third control signal Mux3 is after the active level of the first control signal Mux1, and the active level of the third control signal Mux3 is not overlapped with the active level of the first control signal Mux 1; the active level of the second control signal Mux2 is after the active level of the first control signal Mux1 and before the active level of the third control signal Mux3, and the active level of the second control signal Mux2 overlaps with the active level of the third control signal Mux 3. The purpose of this is to prevent the active levels of the first and second driving signals G1 and G2 from overlapping, causing a disorder in driving timing.

Referring to fig. 2 to 4, the operation of the driving control module 20 includes a phase, b phase, c phase and d phase within the active level of the shift signal Sout.

In the a phase, the first control signal Mux1 is at a low level, the second control signal Mux2 is at a high level, the third control signal Mux3 is at a high level, and the fourth control signal Mux4 is at a low level, so that the first transistor M1 and the fourth transistor M4 are turned on, and the second transistor M2 and the third transistor M3 are turned off. The low level of the shift signal Sout is output to the output terminal of the first signal output unit 210 through the first transistor M1, and the first driving signal G1 is low level. Meanwhile, the first voltage signal V1 is transmitted to the output terminal of the second signal output unit 220 through the fourth transistor M4, and the second driving signal G2 is at a high level.

In the b phase, the first control signal Mux1 is at a high level, the second control signal Mux2 is at a low level, the third control signal Mux3 is at a high level, and the fourth control signal Mux4 is at a high level, so that the second transistor M2 is turned on, and the first transistor M1, the third transistor M3, and the fourth transistor M4 are all turned off. The first voltage signal V1 is transmitted to the output terminal of the first signal output unit 210 through the second transistor M2, and the first driving signal G1 is at a high level. The second driving signal G2 maintains a high level.

In the c-stage, the first control signal Mux1 is at a high level, the second control signal Mux2 is at a low level, then transitions to a high level, the third control signal Mux3 is at a low level, and the fourth control signal Mux4 is at a high level, so that the third transistor M3 is turned on. The low level of the shift signal Sout is transmitted to the output terminal of the second signal output unit 220 via the third transistor M3, and the second driving signal G2 is low level. The first driving signal G1 maintains a high level.

In the d stage, the first control signal Mux1 is at a high level, the second control signal Mux2 is at a high level, the third control signal Mux3 is at a high level, and the fourth control signal Mux4 is at a low level, so that the fourth transistor M4 is turned on. The first voltage signal V1 is transmitted to the output terminal of the second signal output unit 220 through the fourth transistor M4, and the second driving signal G2 is at a high level.

In this embodiment, the effective level of the shift signal Sout is split into two paths of driving signals for output through the a phase, the b phase, the c phase and the d phase, so that one shift register 100 can drive two gate lines simultaneously.

Fig. 5 is a schematic structural diagram of a shift signal generating module according to an embodiment of the present utility model, referring to fig. 3 and 5, based on the above technical solutions, optionally, the shift signal generating module 10 includes a first input module 101, a second input module 102, a first output module 103 and a second output module 104, where an output end of the first input module 101 is connected to a control end of the first output module 103, and the first input module 101 is configured to transmit a second voltage signal V2 of an input end of the first input module 101 to the control end of the first output module 103 in response to a first clock signal SCK 1; the input end of the second input module 102 is used as a trigger signal input end of the shift signal generating module 10 for controlling the electric potential of the control end of the second output module 104; the output terminal of the first output module 103 and the output terminal of the second output module 104 are both connected to the output terminal OUT of the shift signal generating module 10, the first output module 103 is configured to output a first signal VC1 according to the potential of the control terminal thereof, and the second output module 104 is configured to output a second signal VC2 according to the potential of the control terminal thereof.

Specifically, the first input module 101 is capable of being turned on in response to the first clock signal SCK1, and transmitting an input signal of an input terminal thereof to the control terminal of the first output module 103, so as to control the potential of the control terminal of the first output module 103, that is, to control the potential at the first node N1. The second input module 102 may be turned on according to a signal at a control terminal (not shown in the figure), and transmit a signal at an input terminal (for example, may be an output signal of the previous stage shift signal generating module 10, and if the shift register 100 is the first stage, the input signal is a start signal SIN. The start signal SIN is a panel signal on the display panel) to a control terminal of the second output module 104, so as to control a potential at the control terminal of the second output module 104, that is, control a potential at the second node N2.

An output terminal of the first output module 103 is connected to an output terminal OUT of the shift signal generating module 10 for outputting a first level signal VC1 when turned on according to a potential of the first node N1. The output terminal of the second output module 104 is also connected to the output terminal OUT of the shift signal generating module 10 for outputting the second level signal VC2 when turned on according to the potential of the second node N2. Wherein the first level signal is different from the second level signal, for example, the first level signal VC1 is a low level signal VGL, and the second level signal VC2 is a high level signal VGH; or the first level signal VC1 is a high level signal VGH, and the second level signal VC2 is a low level signal VGL.

Fig. 6 is a schematic structural diagram of another shift signal generating module according to an embodiment of the present utility model, referring to fig. 6, based on the above technical solution, optionally, the first input module 101 includes a fifth transistor M5, the second input module 102 includes a sixth transistor M6, the first output module 103 includes a seventh transistor M7 and a first capacitor C1, and the second output module 104 includes an eighth transistor M8 and a second capacitor C2; the gate of the fifth transistor M5 is connected to the first clock signal SCK1, the first pole of the fifth transistor M5 is used as the input end of the first input module 101, the second pole of the fifth transistor M5 is connected to the gate of the seventh transistor M7, the first pole of the seventh transistor M7 is connected to the first voltage signal V1, the second pole of the seventh transistor M7 is used as the output end of the first output module 103, and the first capacitor C1 is connected between the first pole and the gate of the seventh transistor M7. The gate of the sixth transistor M6 is connected to the first clock signal SCK1, the first pole of the sixth transistor M6 is used as the input terminal IN of the second input module 102, the second pole of the sixth transistor M6 is connected to the gate of the eighth transistor M8, the first pole of the eighth transistor M8 is connected to the second clock signal SCK2, the second pole of the eighth transistor M8 is connected to the second pole of the seventh transistor M7, and the second capacitor C2 is connected between the gate and the second pole of the eighth transistor M8.

With continued reference to fig. 6, the shift signal generating module 10 further includes a first output control module 105 and a second output control module 106, where an output terminal of the first output control module 105 is connected to a control terminal of the first output module 103, and the first output control module 105 is configured to maintain the potential of the first node N1 when the first output control module is turned on. The output terminal of the second output control module 106 is connected to the control terminal of the second output module 104, and the second output control module 106 is configured to maintain the potential of the second node N2 when the second output control module is turned on. The control end of the first output control module 105 and the output end of the second input module 102 are connected to the third node N3.

Fig. 7 is a schematic diagram of another shift register according to an embodiment of the present utility model, referring to fig. 7, the first output control module 105 includes a ninth transistor M9, a gate of the ninth transistor M9 is connected to the output end of the second input module 102, a first pole of the ninth transistor M9 is connected to the first clock signal SCK1, and a second pole of the ninth transistor M9 is connected to the output end of the first output control module 105. The second output control module 106 includes a tenth transistor M10 and an eleventh transistor M11, where a gate of the tenth transistor M10 is connected to the control terminal of the first output module 103, a first pole of the tenth transistor M10 is connected to the first voltage signal V1, a second pole of the tenth transistor M10 is connected to the first pole of the eleventh transistor M11, a second pole of the eleventh transistor M11 is an output terminal of the second output control module 106, and a gate of the eleventh transistor M11 is connected to the second clock signal SCK2.

Fig. 8 is a timing control waveform diagram of a shift register according to an embodiment of the present utility model, which is suitable for the shift register shown in fig. 7, and the working process of the shift register according to the present embodiment includes a first stage t1, a second stage t2, a third stage t3, a fourth stage t4, a fifth stage t5, a sixth stage t6, a seventh stage t7 and an eighth stage t8 in combination with fig. 7 and 8. The start signal SIN may be provided by a start signal line, and the first clock signal SCK1 and the second clock signal SCK2 may be provided by corresponding clock signal lines, respectively.

In the first stage t1, the start signal SIN is at a high level, the first clock signal SCK1 is at a low level, the second clock signal SCK2 is at a high level, and therefore, the fifth transistor M5 and the sixth transistor M6 are turned on, the second voltage signal V2 (low level signal VGL) is transmitted to the gate of the seventh transistor M7 through the fifth transistor M5, the seventh transistor M7 is turned on, the first voltage signal V1 (high level signal VGH) is transmitted to the output terminal OUT of the shift signal generating module 10 through the seventh transistor M7, and the output terminal OUT outputs a high level. The signal input IN the second input module 102 is transmitted to the gate of the eighth transistor M8 through the sixth transistor M6, and when the shift register 100 is the first stage shift register, the input IN of the second input module 102 is connected to the start signal SIN, and the eighth transistor M8 is turned off. The shift signal generating module 10 outputs the high level signal VGH in the first stage t 1. When the shift register 100 is a shift register of a stage other than the first stage, the input terminal IN of the second input module 102 is the output signal of the shift signal generating module 10 IN the shift register 100 of the previous stage, and the first clock signal SCK1 is at a low level, so that the fifth transistor M5 is IN a conducting state, the output terminal OUT of the shift register 11 is at a high level, and the eighth transistor M8 is turned off, so that the output terminal OUT of the shift signal generating module 10 still outputs the high level signal VGH.

The following stages are described by taking the first stage shift register 100 as an example.

In the second phase t2, the start signal SIN is high, the first clock signal SCK1 is high, and the second clock signal SCK2 is low, so the fifth transistor M5 and the sixth transistor M6 are turned off, and the eleventh transistor M11 is turned on. The low level signal VGL stored on the first capacitor C1 keeps the seventh transistor M7 and the tenth transistor M10 turned on, and the high level signal VGH is transmitted to the second node N2 through the tenth transistor M10 and the eleventh transistor M11, and the eighth transistor M8 maintains the off state. Meanwhile, the high level signal VGH is transmitted to the output terminal OUT of the shift signal generating module 10 through the seventh transistor M7, and the output terminal OUT outputs the high level signal VGH.

In the third stage t3, the start signal SIN is low, the first clock signal SCK1 is low, the second clock signal SCK2 is high, so that the fifth transistor M5 and the sixth transistor M6 are turned on, the first node N1 is at a potential corresponding to the low level signal VGL, the seventh transistor M7 is turned on, and the high level signal VGH is transmitted to the output terminal OUT of the shift signal generating module 10. Since the start signal SIN is low, the potentials of the second node N2 and the third node N3 are also low, the eighth transistor M8 and the ninth transistor M9 are turned on, the low level of the first clock signal SCK1 is transmitted to the first node N1, and the on state of the seventh transistor M7 is maintained. Meanwhile, the high level of the second clock signal SCK2 is transmitted to the output terminal OUT of the shift signal generating module 10 through the eighth transistor M8. Therefore, in the third stage t3, the seventh transistor M7 and the eighth transistor M8 are simultaneously turned on, so that the output terminal OUT of the shift signal generating module 10 outputs the high level signal VGH.

In the fourth stage t4, the start signal SIN is at a low level, the first clock signal SCK1 is at a high level, the second clock signal SCK2 is at a high level, and therefore, the fifth transistor M5 and the sixth transistor M6 are turned off, the voltage stored in the second capacitor C2 (the low level signal VGL in the previous stage) turns on the ninth transistor M9 and the eighth transistor M8, the high level of the first clock signal SCK1 turns off the seventh transistor M7, the high level of the second clock signal SCK2 is transmitted to the output terminal OUT of the shift signal generating module 10 via the eighth transistor M8, and the output terminal OUT outputs the high level signal VGH.

In the fifth stage t5, the start signal SIN is high, the first clock signal SCK1 is high, and the second clock signal SCK2 is low. The voltage stored in the first capacitor C1 (corresponding to the high level signal VGH of the previous stage) keeps the seventh transistor M7 in the off state, the voltage stored in the second capacitor C2 (corresponding to the low level signal VGL of the previous stage) keeps the eighth transistor M8 on, the low level of the second clock signal SCK2 is transmitted to the output terminal OUT of the shift signal generating module 10, and the output terminal OUT outputs the low level signal VGL. Since the second clock signal SCK2 jumps from high level to low level, the potential of the gate (i.e. the second node N2) of the eighth transistor M8 is pulled lower under the bootstrap action of the second capacitor C2, and the eighth transistor M8 is continuously turned on, so that the signal output by the output terminal OUT is the low level signal VGL.

Note that, in each of the stages except the fifth stage t5, the output terminal OUT of the moving signal generating module 10 outputs the high level signal VGH, and thus the first signal output unit 210 and the second signal output unit 220 both output the high level signal VGH. In the fifth stage t5, the shift signal generating module 10 outputs the active level, and the specific operation of the first signal output unit 210 and the second signal output unit 220 can be referred to the related description in the above embodiment, which is not repeated.

In the sixth stage t6, the start signal SIN is high, the first clock signal SCK1 is high, and the second clock signal SCK2 is high. The voltage stored in the second capacitor C2 (the low level signal VGL in the previous stage) causes the eighth transistor M8 to be turned on continuously, the high level of the second clock signal SCK2 is transmitted to the output terminal OUT of the shift signal generating module 10, and the output terminal OUT outputs the high level signal VGH.

The working processes of the seventh stage t7 and the second stage t2 are the same, and the working processes of the eighth stage t8 and the first stage t1 are the same, and are not described herein.

With continued reference to fig. 7, the voltage stabilizing module 40 includes a first voltage stabilizing unit 401 and a second voltage stabilizing unit 402, the first voltage stabilizing unit 401 includes a first sub-transistor M01 and a second sub-transistor M02, and the second voltage stabilizing unit 402 includes a third sub-transistor M03 and a fourth sub-transistor M04; the gate of the first sub-transistor M01 and the gate of the second sub-transistor M02 are connected together as a control end of the first voltage stabilizing unit 401 and connected with the corresponding output end of the driving control module 20, the first pole of the first sub-transistor M01 is connected with the first voltage signal line as a first input end of the first voltage stabilizing unit 401, the second pole of the first sub-transistor M01 and the second pole of the second sub-transistor M02 are connected together as an output end of the first voltage stabilizing unit 401, and the first pole of the second sub-transistor M02 is connected with the second voltage signal line as a second input end of the first voltage stabilizing unit 401; the gate of the third sub-transistor M03 and the gate of the fourth sub-transistor M04 are connected together as the control terminal of the second voltage stabilizing unit 402 and connected to the output terminal of the first voltage stabilizing unit 401, the first pole of the third sub-transistor M03 is connected to the first voltage signal line as the first input terminal of the second voltage stabilizing unit 402, the second pole of the third sub-transistor M03 and the second pole of the fourth sub-transistor M04 are connected together as the output terminal of the second voltage stabilizing unit 402 to output the stabilized driving signals (G1 ', G2'), and the first pole of the fourth sub-transistor M04 is connected to the second voltage signal line. The first voltage signal V1 transmitted on the first voltage signal line is at a high level and is the same as the high level signal accessed by the seventh transistor M7; the second voltage signal V2 transmitted on the second voltage signal line is low level and the same as the low level of the second clock signal SCK 2.

In the present embodiment, the channel type of the first sub-transistor M01 is different from that of the second sub-transistor M02, so that the high-level signal VGH and the low-level signal VGL cannot be simultaneously output from the output terminal of the first voltage stabilizing unit 401. Similarly, the channel type of the third sub-transistor M03 and the channel type of the fourth sub-transistor M04 are also different.

Taking the first driving signal G1 as an example, when the first driving signal G1 is at a low level, the second sub-transistor M02 is turned off, and the first sub-transistor M01 is turned on, and the first sub-transistor M01 outputs the high level signal VGH to the control terminal of the second voltage stabilizing unit 402. Under the action of the high level signal VGH, the third sub-transistor M03 is turned off, and the fourth sub-transistor M04 is turned on, and the fourth sub-transistor M04 outputs the low level signal VGL. Therefore, when the signal output unit 21 outputs the low level signal, the voltage stabilizing module 40 also outputs the low level signal, wherein the voltage amplitude of the low level signal VGL is the same as the voltage amplitude of the low level shift signal Sout that the shift signal generating module 10 wants to output, that is, the output signal of the shift signal generating module 10 is stabilized by the voltage stabilizing module 40, so that the stability of the output signal of the shift register 100 can be ensured. The voltage stabilizing process of other driving signals is the same as that of the first driving signal G1, and will not be described again.

Fig. 9 is a schematic structural diagram of another shift signal generating module according to an embodiment of the present utility model, referring to fig. 9, based on the above technical solutions, optionally, the shift signal generating module 10 further includes a protection module 107, where the protection module 107 is connected between an output end of the second input module 102 and a control end of the second output module 104.

Specifically, the protection module 107 includes a twelfth transistor M12, a gate of the twelfth transistor M12 is connected to the second voltage signal V2 (the low level signal VGL), a first pole of the twelfth transistor M12 is connected to the output terminal of the second input module 102, and a second pole of the twelfth transistor M12 is connected to the control terminal of the second output module 104. That is, the twelfth transistor M12 is connected between the second node N2 and the third node N3, and the twelfth transistor M12 may be in a normally-on state in response to the second voltage signal V2 (low level signal VGL). By providing the twelfth transistor M12, the transmission of the extremely low potential at the gate of the eighth transistor M8 to the third node N3 in the fifth stage t5 can be avoided, which affects the normal operation of the shift signal generating module 10.

It should be noted that the structure of the shift signal generating module 10 in the above-mentioned technical solution is only an alternative structure provided in this embodiment, and in other embodiments, other structures may be further included. The output signals of the shift signal generating module 10 can all realize shunt output through the driving control module 20 provided by the embodiment, so as to realize one-drive multi-function of the shift register 100.

Optionally, an embodiment of the present utility model further provides a gate driving circuit, and fig. 10 is a schematic structural diagram of the gate driving circuit provided by the embodiment of the present utility model, and referring to fig. 10, the gate driving circuit includes a plurality of shift registers 100 provided by any embodiment of the present utility model, and the plurality of shift registers 100 are cascaded together. In the plurality of cascaded shift registers 100, the trigger signal accessed by the shift register 100 at the next stage is provided by the output terminal OUT of the shift signal generating module 10 in the shift register 100 at the previous stage.

Specifically, the gate driving circuit may be used in conjunction with a pixel circuit in a display panel, and the gate driving circuit provides a gate driving signal to the pixel circuit. The shift signal Sout output from the output terminal OUT of the shift signal generating module 10 may be used for the driving signal Gout (G1, G2 … … Gn) of the gate of the pixel circuit, while the shift signal Sout is also used for the input signal of the next stage shift signal generating module 10 itself.

The SC1 end of the shift signal generating module 10 is a first clock signal input end, and is used for accessing a first clock signal SCK1; the SC2 terminal is a second clock signal input terminal, and is configured to access a second clock signal SCK2.

According to the technical scheme provided by the embodiment, one driving control module is additionally arranged for each shift register, so that one shift register can output multiple paths of driving signals so as to drive multiple grid lines (scanning lines). In the grid driving circuit applying the shift register, the number of the shift register can be greatly reduced, so that the wiring space of the grid driving circuit can be reduced, and the narrow frame of the panel can be realized.

Optionally, the embodiment of the present utility model further provides a display panel, where the display panel includes the gate driving circuit provided by any embodiment of the present utility model, so that the display panel also has the beneficial effects described in any embodiment above.

Fig. 11 is a schematic structural diagram of a display panel according to an embodiment of the present utility model, referring to fig. 1 to 11, the display panel 30 includes a plurality of scan lines 301 extending along a first direction X, the scan lines 301 are sequentially arranged along a second direction Y, and the first direction X and the second direction Y intersect; the gate driving circuit is used for sequentially transmitting the stabilized driving signal Gn' to the scanning line 301. The gate driving circuit including a plurality of cascaded shift registers 100 is disposed in the left frame and/or the right frame of the display panel 30, and each shift register 100 includes a shift signal generating module 10 and a driving control module 20 connected in series. Each shift register 100 in the gate driving circuit can drive two scan lines 301, so that the number of shift registers 100 can be greatly reduced, and thus the wiring space of the gate driving circuit can be reduced, which is beneficial to realizing a narrow frame of the display panel 30.

In the present embodiment, the display panel 30 can be applied to a mobile phone, and can also be applied to any electronic product having a display function, including but not limited to the following categories: television, notebook computer, desktop display, tablet computer, digital camera, smart bracelet, smart glasses, vehicle-mounted display, medical equipment, industrial control equipment, touch interactive terminal, etc., which are not particularly limited in this embodiment of the utility model.

The above embodiments do not limit the scope of the present utility model. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present utility model should be included in the scope of the present utility model.

Claims

1. The shift register is characterized by comprising a shift signal generation module and a drive control module;

the shift register further comprises a plurality of voltage stabilizing modules, each output end of the driving control module is connected with one voltage stabilizing module, and the voltage stabilizing modules are used for stabilizing the level of the driving signals.

2. The shift register according to claim 1, wherein the driving control module includes a first signal output unit and a second signal output unit;

3. The shift register according to claim 2, wherein the first signal output unit includes a first transistor and a second transistor, a first pole of the first transistor being a first input terminal of the first signal output unit, a second pole of the first transistor being an output terminal of the first signal output unit, a gate of the first transistor being a first control terminal of the first signal output unit; the first electrode of the second transistor is a second input end of the first signal output unit, the second electrode of the second transistor is connected with the second electrode of the first transistor, and the gate of the second transistor is a second control end of the first signal output unit;

And/or the number of the groups of groups,

the second signal output unit comprises a third transistor and a fourth transistor, a first electrode of the third transistor is a first input end of the second signal output unit, a second electrode of the third transistor is an output end of the second signal output unit, and a gate of the third transistor is a first control end of the second signal output unit; the first electrode of the fourth transistor is a second input end of the second signal output unit, the second electrode of the fourth transistor is connected with the second electrode of the third transistor, and the gate of the fourth transistor is a second control end of the second signal output unit.

4. The shift register according to claim 2, wherein an active level of a third control signal on the third control signal line is subsequent to an active level of a first control signal on the first control signal line and the active level of the third control signal does not overlap with the active level of the first control signal during a period of the active level of the shift signal;

5. The shift register of claim 2, wherein the first voltage signal on the first voltage signal line is a direct current voltage signal.

6. The shift register of claim 1, wherein the shift signal generation module comprises a first input module, a second input module, a first output module, and a second output module;

the output end of the first input module is connected with the control end of the first output module, and the first input module is used for responding to a first clock signal on a first clock signal line and transmitting a second voltage signal on a second voltage signal line of the input end of the first input module to the control end of the first output module;

the output end of the first output module and the output end of the second output module are both connected to the output end of the shift signal generating module, the first output module is used for outputting a first signal according to the electric potential of the control end of the first output module, and the second output module is used for outputting a second signal according to the electric potential of the control end of the second output module.

7. The shift register as claimed in claim 6, wherein,

the first input module comprises a fifth transistor, the second input module comprises a sixth transistor, the first output module comprises a seventh transistor and a first capacitor, and the second output module comprises an eighth transistor and a second capacitor;

8. The shift register of claim 7, wherein the shift signal generation module further comprises a first output control module and a second output control module, wherein an output terminal of the first output control module is connected to a control terminal of the first output module, and an output terminal of the second output control module is connected to a control terminal of the second output module.

9. The shift register of claim 8, wherein the first output control module comprises a ninth transistor, a gate of the ninth transistor being connected to the output of the second input module, a first pole of the ninth transistor being connected to the first clock signal line, a second pole of the ninth transistor being the output of the first output control module;

10. The shift register of claim 9, wherein the voltage regulator module comprises a first voltage regulator unit and a second voltage regulator unit, the first voltage regulator unit comprising a first sub-transistor and a second sub-transistor, the second voltage regulator unit comprising a third sub-transistor and a fourth sub-transistor;

the grid electrode of the third sub-transistor and the grid electrode of the fourth sub-transistor are connected together to serve as the input end of the second voltage stabilizing unit to be connected with the output end of the first voltage stabilizing unit, the first electrode of the third sub-transistor serves as the first input end of the second voltage stabilizing unit to be connected with the first voltage signal line, the second electrode of the third sub-transistor and the second electrode of the fourth sub-transistor are connected together to serve as the output end of the second voltage stabilizing unit to output a stabilized driving signal, and the first electrode of the fourth sub-transistor is connected with the second voltage signal line.

11. A gate drive circuit comprising a plurality of cascaded shift registers according to any one of claims 1-10; in the plurality of cascaded shift registers, the trigger signal accessed by the shift register at the next stage is provided by the output end of the shift signal generating module in the shift register at the previous stage.

12. A display panel comprising the gate driving circuit according to claim 11; the display panel further comprises a plurality of scanning lines extending along a first direction, the scanning lines are sequentially arranged along a second direction, and the first direction and the second direction are intersected; the gate driving circuit is used for sequentially transmitting driving signals to the scanning lines.