CN220691047U

CN220691047U - Test circuit and test apparatus for semiconductor device

Info

Publication number: CN220691047U
Application number: CN202322051639.XU
Authority: CN
Inventors: 吴海涛; 吴志盛
Original assignee: Shenzhen Cztek Co ltd
Current assignee: Shenzhen Cztek Co ltd
Priority date: 2023-07-31
Filing date: 2023-07-31
Publication date: 2024-03-29
Anticipated expiration: 2033-07-31

Abstract

A test circuit and test equipment for semiconductor devices belong to the technical field of testing, and a constant current source circuit outputs constant current; the constant voltage source circuit outputs constant voltage; the selection circuit selects and outputs constant current or constant voltage to the chip to be tested; when constant voltage is loaded to the chip to be detected, the detection circuit detects leakage current of the chip to be detected so as to output a leakage current detection signal; the main control circuit, the constant current source circuit and the selection circuit are connected to the first node together, an open-short circuit test result is obtained according to the voltage of the first node, and a leakage current test result is obtained according to a leakage current detection signal, so that the test circuit for the semiconductor device is provided, a special chip is not needed, and the cost is reduced; and each part of circuit is independently built, can flexibly expand, has wider application range, and can be used in high-power and high-current scenes.

Description

Test circuit and test apparatus for semiconductor device

Technical Field

The application belongs to the technical field of testing, and particularly relates to a testing circuit and testing equipment for a semiconductor device.

Background

Open-Short Test (Open-Short Test), also known as Continuity Test (Continuity Test) or Contact Test (Contact Test), is used to confirm that all signal pins are electrically connected to the corresponding channels of the Test system during device testing and that no signal pins are shorted to other signal pins, power supply or ground.

The Leakage Test (Leakage Test) is used for performing Leakage Test on the input/output pins of the chip, so as to find out the structural problem of the input/output pins of the chip as soon as possible, and prepare for the following function Test.

At present, in the semiconductor industry, related testing of semiconductor devices is generally performed by adopting a customized application specific integrated circuit or a universal power management unit chip, related chip technologies are mastered in the hands of chip manufacturers such as Europe and America, and a large number of related testing equipment is difficult to acquire in China, and the cost is relatively high. In addition, the bottom layer functions of the integrated test chip are relatively fixed, the expansion is inflexible, and the integrated test chip cannot be used in high-power and high-current scenes.

Disclosure of Invention

The purpose of the application is to provide a test circuit and test equipment for a semiconductor device, and aims to solve the problems that the cost is relatively high, the functions of related equipment are relatively fixed, the expansion is inflexible, and the semiconductor device cannot be used in high-power and high-current scenes.

The embodiment of the application provides a test circuit for a semiconductor device, which comprises the following components:

a constant current source circuit configured to output a constant current;

a constant voltage source circuit configured to output a constant voltage;

a selection circuit connected to the constant current source circuit and the constant voltage source circuit and configured to selectively output the constant current or the constant voltage to a chip to be tested;

the detection circuit is connected between the constant voltage source circuit and the selection circuit and is configured to detect leakage current of the chip to be detected when the constant voltage is loaded to the chip to be detected so as to output a leakage current detection signal;

the main control circuit is connected with the detection circuit, is connected with the constant current source circuit and the selection circuit in a common mode and is configured to obtain an open-short circuit test result according to the voltage of the first node and obtain a leakage current test result according to the leakage current detection signal.

In one embodiment, the method further comprises:

and a follower circuit connected between the constant voltage source circuit and the detection circuit and commonly connected to a second node with the selection circuit and the sampling circuit, and configured to make the voltage of the second node follow the constant voltage so as to output a stable constant voltage at the second node.

In one embodiment, the method further comprises:

and the current limiting circuit is connected between the following circuit and the detection circuit and is configured to limit the constant voltage.

In one embodiment, the method further comprises:

and the clamping circuit is connected with the selection circuit and is configured to clamp the voltage of the first node when the selection circuit selects and outputs the constant current to the chip to be tested.

In one embodiment, the constant current source circuit includes:

the digital-to-analog conversion circuit is configured to be connected with a first digital signal and convert the first digital signal into a first analog signal;

and the conversion circuit is connected with the first digital-to-analog conversion circuit, the first node, the main control circuit and the selection circuit and is configured to convert the first analog signal into the constant current.

In one embodiment, the detection circuit includes:

the sampling circuit is connected between the constant voltage source circuit and the selection circuit and is configured to sample leakage current of the chip to be tested when the constant voltage is loaded to the chip to be tested, and the voltages at two ends of the sampling circuit are used as sampling signals;

a reference circuit configured to output a reference voltage;

and the differential amplifying circuit is connected with the main control circuit, the sampling circuit and the reference circuit and is configured to differentially amplify the sampling signal based on the reference voltage so as to output a leakage current detection signal.

In one embodiment, the sampling circuit includes a regulation amplifying circuit and a resistor assembly;

and the adjusting and amplifying circuit is configured to be connected with the adjusting signal, amplify the adjusting signal and output an adjusting and amplifying signal so as to adjust the resistance value of the resistor assembly.

In one embodiment, the constant voltage source circuit includes a second digital-to-analog conversion circuit.

In one embodiment, the master circuit includes:

the first analog-to-digital conversion circuit is connected with the detection circuit and is configured to perform analog-to-digital conversion on the leakage current detection signal so as to output a leakage current digital signal;

the second analog-to-digital conversion circuit is connected with the first node and is configured to perform analog-to-digital conversion on the voltage of the first node so as to output an open-circuit and short-circuit digital signal;

the control module is connected with the first analog-to-digital conversion circuit and the second analog-to-digital conversion circuit and is configured to obtain the open-short circuit test result according to the open-short circuit digital signal and obtain the leakage current test result according to the leakage current digital signal.

The embodiment of the application also provides test equipment, which comprises the test circuit for the semiconductor device.

Compared with the prior art, the embodiment of the application has the beneficial effects that: the constant current source circuit outputs constant current; the constant voltage source circuit outputs constant voltage; the selection circuit selects and outputs constant current or constant voltage to the chip to be tested; when constant voltage is loaded to the chip to be detected, the detection circuit detects leakage current of the chip to be detected so as to output a leakage current detection signal; the main control circuit, the constant current source circuit and the selection circuit are connected to the first node together, an open-short circuit test result is obtained according to the voltage of the first node, and a leakage current test result is obtained according to a leakage current detection signal, so that the test circuit for the semiconductor device is provided, a special chip is not needed, and the cost is reduced; and each part of circuit is independently built, can flexibly expand, has wider application range, and can be used in high-power and high-current scenes.

Drawings

For a clearer description of the technical application in the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.

Fig. 1 is a schematic diagram of a test circuit for a semiconductor device according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of another configuration of a test circuit for a semiconductor device according to an embodiment of the present application;

FIG. 3 is a schematic diagram of another configuration of a test circuit for a semiconductor device according to an embodiment of the present application;

FIG. 4 is a schematic diagram of another configuration of a test circuit for a semiconductor device according to an embodiment of the present application;

FIG. 5 is a schematic diagram of another configuration of a test circuit for a semiconductor device according to an embodiment of the present application;

fig. 6 is a schematic diagram of another structure of a test circuit for a semiconductor device according to an embodiment of the present application;

fig. 7 is a schematic diagram of another structure of a test circuit for a semiconductor device according to an embodiment of the present application;

fig. 8 is a schematic diagram of another structure of a test circuit for a semiconductor device according to an embodiment of the present application;

fig. 9 is a schematic diagram of another structure of a test circuit for a semiconductor device according to an embodiment of the present application;

fig. 10 is a schematic circuit diagram of a portion of an exemplary test circuit for a semiconductor device according to an embodiment of the present application.

Detailed Description

In order to make the technical problems, technical schemes and beneficial effects to be solved by the present application more clear, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

Fig. 1 shows a schematic structural diagram of a test circuit for a semiconductor device according to an embodiment of the present application, and for convenience of explanation, only a portion related to the embodiment is shown, which is described in detail below:

the above-described test circuit for a semiconductor device includes the constant current source circuit 100, the constant voltage source circuit 200, the selection circuit 300, the detection circuit 400, and the main control circuit 500.

The constant current source circuit 100 is configured to output a constant current.

The constant voltage source circuit 200 is configured to output a constant voltage.

The selection circuit 300, connected to the constant current source circuit 100 and the constant voltage source circuit 200, is configured to selectively output a constant current or a constant voltage to the chip to be tested.

The detection circuit 400, connected between the constant voltage source circuit 200 and the selection circuit 300, is configured to detect a leakage current of the chip to be tested when a constant voltage is applied to the chip to be tested, so as to output a leakage current detection signal.

The main control circuit 500 is connected to the detection circuit 400, and is commonly connected to the constant current source circuit 100 and the selection circuit 300 at the first node a, and is configured to obtain an open-short circuit test result according to the voltage of the first node a, and obtain a leakage current test result according to the leakage current detection signal.

Specifically, when the chip to be tested is subjected to the open-short circuit test, the constant current source circuit 100 outputs a constant current to the selection circuit 300, and the selection circuit 300 selectively outputs the constant current to the chip to be tested. It can be understood that, when the chip to be tested is normal, the voltage of the first node a is in the preset voltage range, and when the port of the chip to be tested is open or short-circuited, the voltage of the first node a is not in the preset voltage range, so that the main control circuit 500 can obtain the short-circuit test result according to the voltage of the first node a.

When the leakage current test is performed on the chip to be tested, the constant voltage source circuit 200 outputs a constant voltage to the selection circuit 300, the selection circuit 300 selectively outputs the constant voltage to the chip to be tested, the detection circuit 400 detects the leakage current of the chip to be tested and outputs a leakage current detection signal to the main control circuit 500, and therefore the main control circuit 500 can obtain the leakage current according to the leakage current detection signal to obtain a leakage current test result.

The adoption of the main control circuit 500 can obtain the open-short circuit test result according to the voltage of the first node A and the leakage current test result according to the detection signal of the leakage current, thereby simplifying the circuit and reducing the cost.

As shown in fig. 2, the test circuit for a semiconductor device further includes a follower circuit 600 connected between the constant voltage source circuit 200 and the detection circuit 400 and commonly connected to the second node B with the selection circuit 300 and the sampling circuit 410, configured to cause the voltage of the second node B to follow the constant voltage to output a stable constant voltage at the second node B.

The follower circuit 600 ensures that the voltage of the second node B follows the constant voltage, thereby outputting a stable constant voltage to the chip to be tested and improving the reliability of the leakage current test result.

As shown in fig. 3, the test circuit for a semiconductor device further includes a current limiting circuit 700 connected between the follower circuit 600 and the detection circuit 400, configured to limit a constant voltage.

The constant voltage is limited by the current limiting circuit 700, so that the chip to be tested is prevented from being damaged due to overhigh constant voltage, and the safety of testing is improved.

As shown in fig. 4, the test circuit for a semiconductor device further includes a clamp circuit 800 connected to the selection circuit 300 and configured to clamp the voltage of the first node a when the selection circuit 300 selects to output a constant current to the chip under test.

The clamp circuit 800 avoids the damage to the main control circuit due to the overlarge voltage of the ground first node A caused by the fault of the chip to be tested when the open-short circuit test is performed, and improves the reliability and safety of the test.

As shown in fig. 5, the constant current source circuit 100 includes a first digital-to-analog conversion circuit 110 and a conversion circuit 120.

The first digital-to-analog conversion circuit 110 is configured to access the first digital signal and convert the first digital signal into a first analog signal.

The conversion circuit 120, connected to the first digital-to-analog conversion circuit 110, the first node a, the master circuit 500, and the selection circuit 300, is configured to convert the first analog signal into a constant current.

The first digital-to-analog conversion circuit 110 and the conversion circuit 120 convert the first digital signal into a constant current, and the constant current converted by the first digital-to-analog conversion circuit 110 and the conversion circuit 120 is variable because the first digital signal is variable, so that the circuit can adapt to chips to be tested with different specifications, the application range of the test circuit is enlarged, and the flexibility of the test circuit is improved.

As shown in fig. 6, the detection circuit 400 includes a sampling circuit 410, a reference circuit 420, and a differential amplification circuit 430.

A sampling circuit 410 connected between the constant voltage source circuit 200 and the selection circuit 300, configured to sample a leakage current of the chip to be tested when a constant voltage is applied to the chip to be tested, and to use voltages at both ends of the sampling circuit 410 as sampling signals;

a reference circuit 420 configured to output a reference voltage;

the differential amplifying circuit 430, connected to the main control circuit 500, the sampling circuit 410, and the reference circuit 420, is configured to differentially amplify the sampling signal based on the reference voltage to output a leakage current detection signal.

The differential amplifying circuit 430 differentially amplifies the sampling signal and outputs a leakage current detection signal, thereby improving the sensitivity of the test.

As shown in fig. 7, the sampling circuit 410 includes a regulation amplifying circuit 411 and a resistance component 412.

The adjusting amplifying circuit 411 is configured to switch in the adjusting signal, amplify the adjusting signal, and output the adjusting amplifying signal to adjust the resistance of the resistor assembly 412.

Different chips to be tested have different leakage currents, the resistance value of the resistor assembly 412 can be adjusted through the adjusting amplifying circuit 411, for example, when the leakage current of microampere level is tested, the resistance value of the resistor assembly 412 is adjusted to be small through the adjusting amplifying circuit 411, and when the leakage current of nanoamp level is tested, the resistance value of the resistor assembly 412 is adjusted to be large through the adjusting amplifying circuit 411, so that the application range of the testing circuit is enlarged, and the practicability of the testing circuit is improved.

As shown in fig. 8, the constant voltage source circuit 200 includes a second digital-to-analog conversion circuit 210.

The second digital-to-analog conversion circuit 210 converts the accessed digital signal into a constant voltage, and the converted constant voltage is variable because the accessed digital signal is variable, so that the circuit can adapt to chips to be tested with different specifications, the application range of the test circuit is enlarged, and the flexibility of the test circuit is improved.

As shown in fig. 9, the master circuit 500 includes a first analog-to-digital conversion circuit 510, a second analog-to-digital conversion circuit 520, and a control module 530.

A first analog-to-digital conversion circuit 510, coupled to the detection circuit 400, configured to perform an analog-to-digital conversion on the leakage current detection signal to output a leakage current digital signal;

the second analog-to-digital conversion circuit 520 is connected to the first node a and configured to perform analog-to-digital conversion on the voltage of the first node a to output an open-short circuit digital signal;

the control module 530, connected to the first analog-to-digital conversion circuit 510 and the second analog-to-digital conversion circuit 520, is configured to obtain an open-short circuit test result according to the open-short circuit digital signal, and obtain a leakage current test result according to the leakage current digital signal.

Only one control module 530 can obtain an open-short circuit test result according to the open-short circuit digital signal and can obtain a leakage current test result according to the leakage current digital signal, so that the circuit is simplified, and the cost is reduced; by providing the first analog-to-digital conversion circuit 510 and the second analog-to-digital conversion circuit 520, detection accuracy is improved.

Fig. 10 shows a part of an exemplary circuit structure of a test circuit for a semiconductor device according to an embodiment of the present application, which is described in detail below:

the reference circuit 420 includes a first operational amplifier M1, a first resistor R1, a second resistor R2, and a third resistor R3.

The positive input end of the first operational amplifier M1 is connected to the first end of the first resistor R1 and the first end of the second resistor R2, the second end of the first resistor R1 is connected to the first power source VAA, the second end of the second resistor R2 is connected to the power ground, the negative input end of the first operational amplifier M1 is connected to the first end of the third resistor R3, and the output end of the first operational amplifier M1 and the second end of the third resistor R3 are used together as the reference voltage output end of the reference circuit 420 and are connected to the differential amplifying circuit 430 to output the reference voltage.

The differential amplifying circuit 430 includes a differential amplifier U1.

The reference voltage input terminal REF of the differential amplifier U1 is used as a reference voltage input terminal of the differential amplifying circuit 430, and is connected to the reference circuit 420 to input a reference voltage; the sampling signal positive input end of the differential amplification circuit 430 and the sampling signal negative input end of the differential amplification circuit 430 are used as the sampling signal input end of the differential amplification circuit 430 together and are connected with the sampling circuit 410 to input a sampling signal; the output terminal OUT of the differential amplifier U1 is connected to the main control circuit 500 as a leakage current detection signal output terminal of the differential amplifier circuit 430 to output a leakage current detection signal.

The resistor assembly 412 includes a second switching tube Q2, a third switching tube Q3, a ninth resistor R9, a tenth resistor R10, and a first capacitor C1.

The first end of the ninth resistor R9, the first end of the first capacitor C1 and the first end of the tenth resistor R10 are connected, the second end of the ninth resistor R9 is connected with the second end of the first capacitor C1 and the first end of the third switching tube Q3, and the first end of the ninth resistor R9, the first end of the first capacitor C1, the first end of the tenth resistor R10, the second end of the ninth resistor R9, the second end of the first capacitor C1 and the first end of the third switching tube Q3 are commonly used as sampling signal output ends of the sampling circuit 410 and are connected with the differential amplifying circuit 430 to output sampling signals; the second end of the tenth resistor R10 is connected to the first end of the second switching tube Q2, the second end of the second switching tube Q2 is connected to the second end of the third switching tube Q3, and the control end of the second switching tube Q2 and the control end of the third switching tube Q3 are used together as the adjustment amplifying signal input end of the resistor assembly 412 and connected to the adjustment amplifying circuit 411 to input the adjustment amplifying signal.

The regulation amplifying circuit 411 includes a first switching transistor Q1 and an eleventh resistor R11, a twelfth resistor R12, and a thirteenth resistor R13.

The first end of the first switching tube Q1 and the first end of the thirteenth resistor R13 are used as the adjusting amplifying signal output end of the adjusting amplifying circuit 411 together and are connected with the resistor assembly 412 to output an adjusting amplifying signal; the control end of the first switching tube Q1 is connected to the first end of the eleventh resistor R11 and the first end of the twelfth resistor R12, the second end of the twelfth resistor R12 is connected to the second power supply VBB, the second end of the eleventh resistor R11 is used as the adjusting signal input end of the adjusting amplifying circuit 411 to input the adjusting signal, the second end of the thirteenth resistor R13 is connected to the third power supply VCC, and the first end of the first switching tube Q1 is connected to the power supply ground.

It should be noted that the switching transistor in the present application may be a field effect transistor, a triode, an IGBT, or the like, which is not limited in this application.

The conversion circuit 120 includes a third operational amplifier M3, a fourth operational amplifier M4, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and an eighth resistor R8.

The first end of the fifth resistor R5 and the first end of the sixth resistor R6 are used together as a first analog signal input end of the conversion circuit 120 to input a first analog signal; the second end of the fifth resistor R5 is connected to the first end of the fourth resistor R4 and the non-inverting input end of the third operational amplifier M3, the second end of the sixth resistor R6 is connected to the first end of the eighth resistor R8 and the inverting input end of the third operational amplifier M3, the second end of the fourth resistor R4 is connected to the output end of the third operational amplifier M3 and the first end of the seventh resistor R7, and the second end of the seventh resistor R7 and the non-inverting input end of the fourth operational amplifier M4 are used together as a constant current output end of the conversion circuit 120 and are connected to the selection circuit 300 and the first node a to output a constant current; the second terminal of the eighth resistor R8 is connected to the inverting input terminal of the fourth operational amplifier M4 and the output terminal of the fourth operational amplifier M4.

The selection circuit 300 includes a multiplexer U2.

The first selection terminal SEL1 of the multiplexer U2 is used as the leakage current test control signal input terminal of the selection circuit 300 to input the leakage current test control signal; the second selection terminal SEL2 of the multiplexer U2 is used as an open-short test control signal input terminal of the selection circuit 300 to input an open-short test control signal; the third selection terminal SEL3 of the multiplexer U2 serves as a configuration signal input terminal of the selection circuit 300 to input a configuration signal; the first input terminal S1 of the multiplexer U2 is connected to the detection circuit 400 as a constant voltage input terminal of the selection circuit 300, and is connected to the second node B to input a constant voltage; the second input terminal S2 of the multiplexer U2 and the third input terminal S3 of the multiplexer U2 are commonly used as constant current input terminals of the selection circuit 300, and are connected to the constant current source circuit 100 and the first node a to input a constant current; the first output terminal D1 of the multiplexer U2 and the second output terminal D2 of the multiplexer U2 are used together as a constant current output terminal and a constant voltage output terminal of the selection circuit 300 to output a constant current or a constant voltage; the third output D3 of the multiplexer U2 is connected to the clamp 800.

The clamp circuit 800 includes a first zener diode Z1 and a second zener diode Z2.

The positive electrode of the first zener diode Z1 and the negative electrode of the second zener diode Z2 are commonly connected with the selection circuit 300 to clamp the voltage of the first node a, and the negative electrode of the first zener diode Z1 is connected with the positive power supply v+ to be connected with a positive voltage; the anode of the second zener diode Z2 is connected to the negative power supply V-to be connected to a negative voltage.

When the selection circuit 300 selects to output a constant current to the chip to be tested, the first output terminal D1 of the multiplexer U2 and the second output terminal D2 of the multiplexer U2 are connected to the third output terminal D3 of the multiplexer U2 by the configuration signal, so that the first zener diode Z1 and the second zener diode Z2 clamp the voltage of the first node a.

The follower circuit 600 includes a second operational amplifier M2.

The non-inverting input terminal of the second operational amplifier M2 is connected to the constant voltage source circuit 200 as a constant voltage input terminal of the follower circuit 600 to input a constant voltage; the inverting input terminal of the second operational amplifier M2 is connected to the second node B so that the second node B follows the constant voltage, and the output terminal of the second operational amplifier M2 is connected to the current limiting circuit 700.

The current limiting circuit 700 includes a fourteenth resistor R14.

A first terminal of the fourteenth resistor R14 is connected to the follower circuit 600 as a constant voltage input terminal of the current limiting circuit 700 to input a constant voltage; the second terminal of the fourteenth resistor R14 is used as a constant voltage output terminal after current limiting of the current limiting circuit 700, and is connected to the detection circuit 400 to output a constant voltage after current limiting.

The following further describes the operation of fig. 10 in conjunction with the principles of operation:

when the chip to be tested is subjected to open-short circuit test, the first digital-to-analog conversion circuit 110 converts the first analog signal according to the first digital signal and outputs the first analog signal to the positive input end of the third operational amplifier M3 and the negative input end of the third operational amplifier M3, the third operational amplifier M3 converts the constant current to the seventh resistor R7 according to the first analog signal and outputs the first feedback voltage value to the positive input end of the third operational amplifier M3 through the first end of the seventh resistor R7, and outputs the second feedback voltage value to the negative input end of the third operational amplifier M3 through the second end of the seventh resistor R7, and the voltage difference is the difference between the first feedback voltage and the second feedback voltage, so that the voltage difference divided by the resistance value of the seventh resistor R7 is the constant current, the output terminal of the third operational amplifier M3 outputs a stable constant current to the second input terminal S2 of the multiplexer U2 and the third input terminal S3 of the multiplexer U2 through the first and second feedback voltages, and the multiplexer U2 outputs the constant current from the first output terminal D1 of the multiplexer U2 and the second output terminal D2 of the multiplexer U2 to the chip under test according to the open-short test control signal inputted from the second selection terminal SEL2 of the multiplexer U2, at this time, the multiplexer U2 also communicates the second input terminal S2 of the multiplexer U2 and the third input terminal S3 of the multiplexer U2, the first output terminal D1 of the multiplexer U2 and the second output terminal D2 of the multiplexer U2 through the configuration signal inputted from the third selection terminal SEL3 of the multiplexer U2, so that when the chip under test is normal, the first node a voltage is normal, when the chip under test is open-circuited, the first node a voltage may be too large or too small; the third output end D3 of the multiplexer U2 is connected with the first node A by the multiplexer U2, so that the voltage of the first node A is clamped by the first zener diode Z1 and the second zener diode Z2, and the damage to the control module caused by the overlarge voltage of the first node A is avoided. The second analog-to-digital conversion circuit 520 performs analog-to-digital conversion on the voltage of the first node a, and outputs an open-circuit digital signal to the control module 530, where the control module 530 obtains an open-circuit test result according to the open-circuit digital signal.

When the chip to be tested is tested for leakage current, the second digital-to-analog conversion circuit 210 converts the connected digital signal into a constant voltage and outputs the constant voltage to the normal phase input end of the second operational amplifier M2, the second operational amplifier M2 outputs the constant voltage from the output end of the second operational amplifier M2 to the first end of the fourteenth resistor R14, the fourteenth resistor R14 limits the constant voltage and outputs the limited constant voltage from the second end of the fourteenth resistor R14, meanwhile, the inverting input end of the second operational amplifier M2 is connected with the second node B, so that the voltage of the second node B can follow the constant voltage, the first input end S1 of the multiplexer U2 is connected with the constant voltage, and the constant voltage is outputted to the chip to be tested from the first output end D1 of the multiplexer U2 and the second output end D2 of the multiplexer U2 according to the leakage current test control signal inputted from the first selection end SEL1 of the multiplexer U2, and the first input end S1 of the multiplexer U2 is connected with the second node B of the multiplexer U2. When the leakage current of the microampere level is tested, an adjusting signal is input through the second end of the eleventh resistor R11, and the first switching tube Q1 outputs an adjusting amplifying signal according to the adjusting signal to control the second switching tube Q2 and the third switching tube Q3 to be closed, at the moment, the passage of the tenth resistor R10 is disconnected, the resistance value of the ninth resistor R9 is used as the resistance value of the two ends of the resistor assembly 412, so that the resistance values of the two ends of the resistor assembly 412 are smaller, and the leakage current of the microampere level can be tested; when the leakage current of the nanoampere level is tested, an adjusting signal is input through the second end of the eleventh resistor R11, the first switching tube Q1 outputs an adjusting amplifying signal according to the adjusting signal to control the second switching tube Q2 and the third switching tube Q3 to be conducted, at the moment, the passage where the tenth resistor R10 is located is conducted, the resistance value of the ninth resistor R9 and the tenth resistor R10 after being connected in parallel is used as the resistance value of the two ends of the resistor assembly 412, and therefore the resistance value of the two ends of the resistor assembly 412 is smaller, and the leakage current of the nanoampere level can be tested.

The positive input terminal in+ of the differential amplifier U1 and the negative input terminal IN-of the differential amplifier U1 commonly input a sampling signal, the differential amplifier U1 differentially amplifies the sampling signal according to a reference voltage input by a reference voltage input terminal REF of the differential amplifier U1 to output a leakage current detection signal to the first analog-to-digital conversion circuit 510, the first analog-to-digital conversion circuit 510 performs analog-to-digital conversion on the leakage current detection signal to output a leakage current digital signal to the control module 530, and the control module 530 obtains a leakage current test result according to the leakage current digital signal.

The constant current source circuit outputs constant current; the constant voltage source circuit outputs constant voltage; the selection circuit selects and outputs constant current or constant voltage to the chip to be tested; when constant voltage is loaded to the chip to be detected, the detection circuit detects leakage current of the chip to be detected so as to output a leakage current detection signal; the main control circuit, the constant current source circuit and the selection circuit are connected to the first node together, a short circuit test result is obtained according to the voltage of the first node, and a leakage current test result is obtained according to a leakage current detection signal, so that the test circuit for the semiconductor device is provided, a special chip is not needed, and the cost is reduced; and each part of circuit is independently built, can flexibly expand, has wider application range, and can be used in high-power and high-current scenes.

It should be understood that the sequence number of each step in the foregoing embodiment does not mean that the execution sequence of each process should be determined by the function and the internal logic of each process, and should not limit the implementation process of the embodiment of the present application in any way.

The above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.

Claims

1. A test circuit for a semiconductor device, the test circuit for a semiconductor device comprising:

a constant current source circuit configured to output a constant current;

a constant voltage source circuit configured to output a constant voltage;

2. The test circuit for a semiconductor device according to claim 1, further comprising:

3. The test circuit for a semiconductor device according to claim 2, further comprising:

4. The test circuit for a semiconductor device according to claim 1, further comprising:

5. The test circuit for a semiconductor device according to claim 1, wherein the constant current source circuit includes:

6. The test circuit for a semiconductor device according to claim 1, wherein the detection circuit includes:

a reference circuit configured to output a reference voltage;

7. The test circuit for a semiconductor device according to claim 6, wherein the sampling circuit includes a regulation amplifying circuit and a resistance component;

8. The test circuit for a semiconductor device according to claim 1, wherein the constant voltage source circuit includes a second digital-to-analog conversion circuit.

9. The test circuit for a semiconductor device according to claim 1, wherein the main control circuit comprises:

10. A test apparatus, characterized in that the test apparatus comprises a test circuit for a semiconductor device as claimed in any one of claims 1 to 9.