CN220651617U

CN220651617U - Display device

Info

Publication number: CN220651617U
Application number: CN202322001888.8U
Authority: CN
Inventors: 李相贤; 李大植; 姜根午; 成始德; 韩颂伊
Original assignee: Samsung Display Co Ltd
Current assignee: Samsung Display Co Ltd
Priority date: 2022-08-05
Filing date: 2023-07-28
Publication date: 2024-03-22
Anticipated expiration: 2033-07-28
Also published as: KR20240020364A; US20240046868A1

Abstract

The application provides a display device. The display device includes a pixel unit including a plurality of pixels, a sensing unit connected to the plurality of pixels through a plurality of sensing lines, a first power supply voltage generator connected to the plurality of pixels through a first power supply line and generating a first power supply voltage for driving the plurality of pixels, a second power supply voltage generator connected to the plurality of pixels through the first power supply line and generating a second power supply voltage for sensing the plurality of pixels, and a timing controller selectively controlling operations of the first power supply voltage generator and the second power supply voltage generator according to a driving mode of the pixel unit.

Description

Display device

The present application claims priority and benefit from korean patent application No. 10-2022-0098197 filed in the korean intellectual property office on day 8 and 5 of 2022, the entire contents of which are incorporated herein by reference.

Technical Field

The present technology relates to a display device and a method of driving the same.

Background

With the development of information technology, display devices as communication media between users and information have become increasingly popular. Accordingly, display devices such as liquid crystal display devices or organic light emitting display devices are widely used.

The display device displays an image using a plurality of pixels. The plurality of pixels may receive a driving current from a commonly connected power source. In this case, when the current paths of some pixels are in a short-circuited state, an overcurrent may flow from the power supply, thereby causing a burn-out phenomenon.

Meanwhile, each of the plurality of pixels includes a driving transistor. In this case, process variations, degradation, and the like may cause deviation in electrical characteristics between the driving transistors of the pixels, and thus it may be difficult to achieve desired gradation. In order to solve such a problem, an external compensation method of compensating for the deviation of the electrical characteristics between the driving transistors outside the pixel is used.

Further, the display device includes a direct current converter (DC-DC converter) that converts input power supplied from the outside to generate a voltage required to drive the pixels. In this case, the voltage output from the DC-DC converter includes a ripple voltage due to the switch, which may reduce stability and quality of the external compensation method.

Disclosure of Invention

Embodiments of the present application provide a display device capable of improving stability and quality of an external compensation method and suppressing a burn-out phenomenon, and a method of driving the display device.

However, the object of the present application is not limited to the above object, and various extensions can be made without departing from the spirit and scope of the present application.

A display device according to an embodiment of the present application includes a pixel unit including a plurality of pixels, a sensing unit connected to the plurality of pixels through a plurality of sensing lines, a first power supply voltage generator connected to the plurality of pixels through a first power supply line and generating a first power supply voltage for driving the plurality of pixels, a second power supply voltage generator connected to the plurality of pixels through the first power supply line and generating a second power supply voltage for sensing the plurality of pixels, and a timing controller selectively controlling operations of the first power supply voltage generator and the second power supply voltage generator according to a driving mode of the pixel unit.

In one embodiment, when the pixel unit is driven in the display mode, the timing controller may supply the first control signal to the first power supply voltage generator, and the first power supply voltage generator may supply the first power supply voltage to the first power supply line in response to the first control signal.

In one embodiment, when the pixel unit is driven in the sensing mode, the timing controller may supply the second control signal to the second power supply voltage generator, and the second power supply voltage generator may supply the second power supply voltage to the first power supply line in response to the second control signal.

In one embodiment, the second power supply voltage generator may further include an overcurrent protection circuit operating in the sensing mode, and the overcurrent protection circuit may include a current detector detecting a driving current flowing through the driving transistor included in each of the plurality of pixels to generate a driving current value, and a current limiter limiting the driving current to a current limit value during a current limit period when the driving current value is greater than or equal to the current limit value.

In one embodiment, after the current limiting period, the current limiter may supply a shutdown signal to the timing controller, the timing controller may supply a third control signal to each of the first and second power supply voltage generators in response to the shutdown signal, and each of the first and second power supply voltage generators may be turned off in response to the third control signal.

In one embodiment, the current limiting period may correspond to a period for sensing a threshold voltage of the driving transistor and/or a period for sensing mobility of the driving transistor.

In one embodiment, the over-current protection circuit may further include a filter unit that stops an operation of the current limiter when the driving current is at a peak value (spike).

In one embodiment, the timing controller may use an integrated circuit bus (inter integrated circuit, I ² C) The communication controls the second supply voltage, the current limit value and/or the current limit period.

In one embodiment, the magnitude of the ripple voltage included in the second power supply voltage may be smaller than the magnitude of the ripple voltage included in the first power supply voltage.

In one embodiment, the display device may further include an input voltage generator that supplies an input voltage to the first power voltage generator, and the first power voltage generator may convert the input voltage to supply the first power voltage.

In one embodiment, the first supply voltage may be the same as or similar to the input voltage.

Drawings

Fig. 1 is a diagram for describing a display device according to an embodiment of the present application.

Fig. 2 is a diagram for describing a display device according to another embodiment of the present application.

Fig. 3 is a view for describing a pixel according to an embodiment of the present application.

Fig. 4A and 4B show graphs for describing ripple voltages according to types of power supply voltages.

Fig. 5 is a diagram for describing a high potential power supply voltage and a driving current according to an operation of the timing controller according to an embodiment of the present application.

Fig. 6 is a diagram for describing an overcurrent protection circuit according to an embodiment of the present application.

Fig. 7 is a diagram for describing an operation of the overcurrent protection circuit according to one embodiment of the present application.

Detailed Description

While the application is open to various modifications and alternative embodiments, specific embodiments thereof will be described and illustrated by way of example in the drawings. It is not intended to limit the application to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the application.

Like reference numerals refer to like elements throughout the description of the drawings. In the drawings, the size of the structures may be exaggerated to clarify the described technology. Although terms such as "first," "second," etc. may be used to describe various elements, these elements should not necessarily be construed as limited by the above terms. These terms are only used for distinguishing one element from another. For example, a first component may be termed a second component, and, similarly, a second component may be termed a first component, without departing from the scope of the present application. Unless the context clearly indicates otherwise, singular expressions include plural expressions.

In this application, it should be understood that terms such as "comprises" or "comprising" are intended to mean that there is a feature, number, step, operation, component, section, or combination thereof described in the specification, and that they do not exclude the presence or addition of one or more other features, numbers, steps, operations, components, sections, or combinations thereof.

In the description, when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or be indirectly connected or coupled to the other element through one or more intervening elements therebetween.

Hereinafter, embodiments of the present application will be described in more detail with reference to the accompanying drawings.

Fig. 1 is a diagram for describing a display device according to an embodiment of the present application. Fig. 2 is a diagram for describing a display device according to another embodiment of the present application. Fig. 4A and 4B show graphs for describing ripple voltages according to types of power supply voltages.

Referring to fig. 1, the display device DD may include a pixel unit 10, a timing controller 20, a data driver 30, a scan driver 40, a sensing unit 50, a first power supply voltage generator 60, a second power supply voltage generator 70, and an input voltage generator 80.

Referring to fig. 2, the display device DD 'may include a pixel unit 10, a timing controller 20, a data driver 30, a scan driver 40, a sensing unit 50, a first power supply voltage generator 60', and a second power supply voltage generator 70.

The pixel unit 10 may be an area in which an image is displayed. The pixel unit 10 may include a plurality of pixels PXij connected to a plurality of scan lines SL11, SL12, … …, SL1m and SL21, SL22, … …, SL2m, a plurality of data lines DL1, DL2, … …, DLs, a plurality of sensing lines SEL1, SEL2, … …, SELn, and a plurality of power lines (e.g., the first power line PL1 and the second power line PL2 of fig. 3) (where m, n, and s are integers greater than 1). Each pixel PXij may refer to a pixel in which a scan transistor is connected to an ith scan line and a jth data line, where i is a positive integer less than or equal to m, and j is a positive integer less than or equal to s.

The pixel cell 10 may be driven in a display mode for displaying an input image or in a sensing mode for detecting an electrical characteristic of the pixel PXij.

For example, when the pixel unit 10 is driven in the display mode, the first power supply voltage ELVDD1 generated from the first power supply voltage generator 60 may be supplied to the first power supply line PL1 connected to each pixel PXij. Accordingly, each pixel PXij may emit light having a brightness corresponding to the driving current i_elvdd1 (shown in fig. 5) generated based on the first power supply voltage ELVDD1.

On the other hand, when the pixel unit 10 is driven in the sensing mode, the second power supply voltage ELVDD2 generated from the second power supply voltage generator 70 may be supplied to the first power supply line PL1 connected to each pixel PXij. Accordingly, the driving current i_elvdd2 (shown in fig. 5) generated based on the second power supply voltage ELVDD2 may flow in the driving transistor included in each pixel PXij.

Although not shown, the display devices DD and DD' may also include emission drivers. The transmission driver may receive a clock signal, a transmission stop signal, etc. from the timing controller 20 to generate a plurality of transmission signals to be supplied to a plurality of transmission lines. For example, the emission driver may include a plurality of light emitting stages connected to a plurality of emission lines. The plurality of light emitting stages may be provided in the form of a shift register. For example, the first light emitting stage generates the emission signal having the off level based on the emission stop signal having the off level, and the remaining plurality of light emitting stages may sequentially generate the plurality of emission signals having the off level based on the emission signal having the off level of the previous light emitting stage.

When the display devices DD and DD' include the emission driver described above, each pixel PXij further includes a transistor connected to an emission line. Such a transistor may be turned off during a data writing period of each pixel PXij to prevent the pixel PXij from emitting light. Hereinafter, a hypothetical case where the emission driver is not provided will be described.

The timing controller 20 may receive input gray RGB and a timing control signal TCS from a host system (e.g., an Application Processor (AP)) through an interface. The timing control signal TCS may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and the like. The timing controller 20 may convert the input gray RGB into the output gray and provide the output gray to the data driver 30.

Based on the timing control signal TCS, the timing controller 20 may supply a plurality of control signals according to specifications of the data driver 30, the scan driver 40, the sensing unit 50, the first power supply voltage generator 60, and the second power supply voltage generator 70, respectively.

The timing controller 20 may selectively control the operations of the first and second power supply voltage generators 60 and 70 according to the driving mode of the pixel unit 10.

For example, when the pixel unit 10 is driven in the display mode, the timing controller 20 may supply the first control signal CS1 having an on level (e.g., a high level) to the first power voltage generator 60 to turn on the first power voltage generator 60. Meanwhile, the timing controller 20 may supply the second control signal CS2 having an off level (e.g., a low level) to the second power voltage generator 70 to turn off the second power voltage generator 70.

On the other hand, when the pixel unit 10 is driven in the sensing mode, the timing controller 20 may supply the second control signal CS2 having an on level (e.g., a high level) to the second power voltage generator 70 to turn on the second power voltage generator 70. Meanwhile, the timing controller 20 may supply the first control signal CS1 having an off level (e.g., a low level) to the first power voltage generator 60 to turn off the first power voltage generator 60.

The timing controller 20 may supply the third control signal CS3 to each of the first and second power supply voltage generators 60 and 70 in response to the off signal OS supplied from the overcurrent protection circuit 71. For example, in response to the off signal OS supplied from the overcurrent protection circuit 71, the timing controller 20 may supply the third control signal CS3 having an off level (e.g., a low level) to each of the first and second power supply voltage generators 60 and 70 to synchronously turn off the first and second power supply voltage generators 60 and 70.

Timing controller 20 may use an integrated circuit bus (I ² C) The communication is performed to control the second power supply voltage ELVDD2 generated by the second power supply voltage generator 70, the current limit value CLV (shown in fig. 7) set in the overcurrent protection circuit 71, and/or the current limit period CLP (shown in fig. 7) set in the overcurrent protection circuit 71. That is, the timing controller 20 may change the second power supply voltage ELVDD2, the current limit value CLV, and/or the current limit period CLP according to the specification of the display device.

The timing controller 20 may include a compensator (not shown) for compensating for an electrical characteristic (e.g., a threshold voltage Vth and/or mobility μ) of the driving transistor based on the sensing data supplied from the sensing unit 50.

The data driver 30 may generate a plurality of data voltages to be supplied to the plurality of data lines DL1, DL2, … …, DLs based on the output gray scale and the control signal supplied from the timing controller 20. For example, the data driver 30 may sample the output gray scale using a clock signal, and may supply a plurality of data voltages corresponding to the output gray scale to the plurality of data lines DL1, DL2, … …, DLs in pixel row units. A pixel row may refer to a plurality of pixels connected to the same scan line.

The scan driver 40 may receive a clock signal, a scan start signal, etc. from the timing controller 20 to generate a plurality of scan signals to be supplied to the plurality of scan lines SL11, SL12, … …, SL1m, and SL21, SL22, … …, SL2m.

The scan driver 40 may sequentially supply a plurality of scan signals having on-level pulses to the plurality of scan lines SL11, SL12, … …, SL1m and SL21, SL22, … …, SL2m. The scan driver 40 may include a plurality of scan stages provided in the form of shift registers. The scan driver 40 may generate a plurality of scan signals by sequentially transmitting a plurality of scan start signals in the form of on-level pulses to a subsequent plurality of scan stages according to control of a clock signal.

The plurality of scan lines SL11, SL12, … …, SL1m and SL21, SL22, … …, SL2m are illustrated in fig. 1 and 2 as being connected to one scan driver 40, but the present application is not limited thereto. For example, each of the plurality of scan lines SL11, SL12, … …, SL1m, and SL21, SL22, … …, SL2m may be connected to a scan driver formed as a separate module.

The sensing unit 50 may detect an electrical characteristic of a driving transistor included in at least one pixel PXij in a sensing mode. For example, in the sensing mode, the sensing unit 50 may sense a voltage or a current on the sensing line SELn connected to the at least one pixel PXij, and may perform analog-to-digital conversion on the sensed value to generate sensing data. The sensing data may include electrical characteristics (e.g., threshold voltage Vth and/or mobility μ) of the drive transistor. The sensing unit 50 may supply sensing data to the timing controller 20.

The first power supply voltage generator 60 may be connected to the plurality of pixels PXij through a first power supply line PL1 (shown in fig. 3), and may generate a first power supply voltage ELVDD1 for driving the plurality of pixels PXij.

Referring to fig. 1, the first power supply voltage generator 60 may convert the input voltage VDD supplied from the input voltage generator 80 to generate a first power supply voltage ELVDD1. For example, the first power supply voltage generator 60 may be provided as a Direct Current (DC) converter converting a DC source from one voltage level to another voltage level, and may step down the input voltage VDD supplied from the input voltage generator 80 to generate the first power supply voltage ELVDD1. The first power supply voltage generator 60 may supply the first power supply voltage ELVDD1 to the pixel unit 10.

Referring to fig. 2, the first power supply voltage generator 60' may generate the first power supply voltage ELVDD1 identical or similar to the input voltage VDD. For example, the first power supply voltage generator 60' may be an Alternating Current (AC) to DC converter that converts an AC input voltage into a DC output voltage, and the first power supply voltage ELVDD1 may be generated by converting an AC voltage ACV supplied from the outside into a DC voltage identical or similar to the input voltage VDD.

Meanwhile, in the process in which the first power supply voltage generator 60 or 60' performs DC-DC conversion on the input voltage VDD or AC-DC conversion on the AC voltage ACV to generate the first power supply voltage ELVDD1, a ripple phenomenon may occur due to residual AC voltage characteristics and switching noise of the transistor when performing the AC-DC conversion. Accordingly, a ripple voltage corresponding to noise may be included in the first power supply voltage ELVDD1, and the magnitude of the ripple voltage may be 50mV or more (see fig. 4A). When the first power supply voltage ELVDD1 is supplied to the pixel unit 10 in the sensing mode, a compensation deviation according to coupling between the first power supply line PL1 and the plurality of sensing lines SEL1, SEL2, … …, SELn and/or the plurality of data lines DL1, DL2, … …, DLs may occur, and thus an artifact phenomenon in which a horizontal line is visible may occur.

Accordingly, when the pixel unit 10 is in the sensing mode, the first power supply voltage generators 60 and 60' may be turned off in response to the first control signal CS1 having an off level (e.g., a low level) supplied from the timing controller 20. That is, the first power supply voltage generators 60 and 60' may not supply the first power supply voltage ELVDD1 to the pixel unit 10 when the pixel unit 10 is in the sensing mode. On the other hand, when the pixel unit 10 is in the display mode, the first power supply voltage generators 60 and 60' may supply the first power supply voltage ELVDD1 to the pixel unit 10 in response to the first control signal CS1 having an on level (e.g., a high level) supplied from the timing controller 20.

The second power supply voltage generator 70 may be connected to the plurality of pixels PXij through a first power supply line PL1 (shown in fig. 3), and may generate a second power supply voltage ELVDD2 for sensing the plurality of pixels PXij. For example, the second power supply voltage generator 70 may be provided as a Low Dropout Output (LDO) regulator, and may convert an input voltage (not shown) supplied from the outside to generate the second power supply voltage ELVDD2. The second power supply voltage generator 70 may supply the second power supply voltage ELVDD2 to the pixel unit 10. Can use I ² The C communication controls the second power supply voltage ELVDD2 through the timing controller 20.

The magnitude of the ripple voltage included in the second power supply voltage ELVDD2 may be smaller than the magnitude of the ripple voltage included in the first power supply voltage ELVDD1. This is because the voltage drop generated in the process in which the second power supply voltage generator 70 generates the second power supply voltage ELVDD2 is smaller than the voltage drop generated in the process in which the first power supply voltage generator 60 generates the first power supply voltage ELVDD1. In other words, in the second power supply voltage generator 70, the voltage difference between the input signal and the output signal may be small.

For example, the magnitude of the ripple voltage included in the second power supply voltage ELVDD2 may be less than or equal to 10mV, which is less than the magnitude (50 mV or more) of the ripple voltage included in the first power supply voltage ELVDD1 (see fig. 4B). Accordingly, even when the second power supply voltage ELVDD2 is supplied to the pixel unit 10 in the sensing mode, compensation deviation according to coupling between the first power supply line PL1 and the plurality of sensing lines SEL1, SEL2, … …, SELn and/or the plurality of data lines DL1, DL2, … …, DLs may be insignificant, and thus the horizontal line may be invisible.

The voltage level of the first power voltage ELVDD1 supplied to the pixel unit 10 in the display mode and the voltage level of the second power voltage ELVDD2 supplied to the pixel unit 10 in the sensing mode may each be changed according to the specification of the display device. That is, the first power supply voltage ELVDD1 may be set to a voltage level suitable for displaying an image in consideration of the specification of the display device, and the second power supply voltage ELVDD2 may be set to a voltage level suitable for sensing the electrical characteristics of the driving transistor in consideration of the specification of the display device. Accordingly, the voltage level of the first power supply voltage ELVDD1 may be the same as or different from the voltage level of the second power supply voltage ELVDD2.

The second power supply voltage generator 70 may include an overcurrent protection circuit 71 that operates in a sensing mode.

The overcurrent protection circuit 71 suppresses or prevents overcurrent from flowing in the pixel unit 10 during a sensing period in which the pixel unit 10 operates in the sensing mode, thereby reducing occurrence of burn-out due to the overcurrent. For example, when the driving current i_elvdd flowing in the driving transistor included in each pixel PXij is detected and the detected driving current i_elvdd reaches the current limit CLV, the overcurrent protection circuit 71 may limit the driving current i_elvdd to the current limit CLV (see fig. 7).

The input voltage generator 80 may generate an input voltage VDD to supply the input voltage VDD to the first power voltage generator 60. For example, the input voltage generator 80 may be implemented as a group Integrated Circuit (IC), and may generate the input voltage VDD through a Main Power Management Circuit (MPMC) included therein to supply the input voltage VDD to the first power voltage generator 60.

Referring to fig. 3, the pixel PXij may include first, second and third transistors T1, T2 and T3, a storage capacitor Cst, and a light emitting diode LD.

Hereinafter, a circuit including an N-type transistor will be described as an example. However, those skilled in the art will be able to design a circuit including a P-type transistor by changing the polarity of the voltage applied to the gate terminal. Similarly, one skilled in the art will be able to design a circuit that includes a combination of P-type transistors and N-type transistors. The P-type transistor refers to a transistor in which the amount of conduction current increases when the voltage difference between the gate electrode and the source electrode increases in a negative direction. An N-type transistor refers to a transistor in which the amount of conduction current increases when the voltage difference between the gate electrode and the source electrode increases in the positive direction. The transistor may be provided in various types such as a Thin Film Transistor (TFT), a Field Effect Transistor (FET), a Bipolar Junction Transistor (BJT), and the like.

In the first transistor T1, a gate electrode of the first transistor T1 may be connected to a first electrode of the storage capacitor Cst, a first electrode of the first transistor T1 may be connected to the first power line PL1, and a second electrode of the first transistor T1 may be connected to a second electrode of the storage capacitor Cst. The first transistor T1 may be referred to as a driving transistor.

In the second transistor T2, a gate electrode of the second transistor T2 may be connected to the first scan line SL1i, a first electrode of the second transistor T2 may be connected to the data line DLj, and a second electrode of the second transistor T2 may be connected to a gate electrode of the first transistor T1. The second transistor T2 may be referred to as a scan transistor.

In the third transistor T3, a gate electrode of the third transistor T3 may be connected to the second scan line SL2i, a first electrode of the third transistor T3 may be connected to the sensing line SELk (where k is a positive integer less than or equal to n), and a second electrode of the third transistor T3 may be connected to a second electrode of the storage capacitor Cst. The third transistor T3 may be referred to as a sense transistor.

In the storage capacitor Cst, a first electrode of the storage capacitor Cst may be connected to a gate electrode of the first transistor T1, and a second electrode of the storage capacitor Cst may be connected to a second electrode of the first transistor T1.

In the light emitting diode LD, an anode of the light emitting diode LD may be connected to the second electrode of the first transistor T1, and a cathode of the light emitting diode LD may be connected to the second power line PL2. The light emitting diode LD may be provided as an organic light emitting diode, an inorganic light emitting diode, a quantum dot/well light emitting diode, or the like. Meanwhile, although the pixel PXij of fig. 3 is exemplarily shown to include one light emitting diode LD, in another embodiment, the pixel PXij may include a plurality of light emitting diodes connected in series, parallel, or series-parallel.

The high potential power supply voltage ELVDD may be applied to the first power supply line PL1, and the low potential power supply voltage ELVSS may be applied to the second power supply line PL2. The high potential power supply voltage ELVDD may include a first power supply voltage ELVDD1 supplied from the first power supply voltage generator 60 or 60' in the display mode and a second power supply voltage ELVDD2 supplied from the second power supply voltage generator 70 in the sensing mode. For example, the first power supply voltage ELVDD1 may be applied to the first power supply line PL1 during the image display period, and the second power supply voltage ELVDD2 may be applied to the first power supply line PL1 during the sensing period.

In the display mode, when a scan signal having an on level (e.g., a high level) is applied to the gate electrode of the second transistor T2 through the first scan line SL1i, the second transistor T2 is turned on. In this case, the data voltage corresponding to the input image supplied from the data line DLj is stored in the storage capacitor Cst. The data voltage of the input image may be a voltage corresponding to the input gray RGB supplied in the display mode. A positive driving current i_elvdd1 having an amount corresponding to a voltage difference between the first electrode and the second electrode of the storage capacitor Cst flows between the first electrode and the second electrode of the first transistor T1. Accordingly, the light emitting diode LD emits light having a brightness corresponding to the data voltage of the input image.

Next, when a scan signal having an off level (e.g., a low level) is applied through the first scan line SL1i, the second transistor T2 is turned off, and the data line DLj is electrically disconnected from the first electrode of the storage capacitor Cst. Therefore, even when the data voltage of the data line DLj changes, the voltage stored in the storage capacitor Cst does not change. Meanwhile, even when the second transistor T2 is turned off, the positive driving current i_elvdd1 may be supplied to the light emitting diode LD through the data voltage stored in the storage capacitor Cst during one frame period. In the sensing mode, when a scan signal having an on level (e.g., a high level) is applied through the second scan line SL2i, the third transistor T3 is turned on. In this case, the reference voltage supplied from the sensing line SELk may be applied to the second electrode of the first transistor T1. The reference voltage may be a voltage having a level at which the first transistor T1 is turned on but the light emitting diode LD does not emit light.

Subsequently, when a scan signal having an on level (e.g., a high level) is applied through the first scan line SL1i, the second transistor T2 is turned on. In this case, the sensing data voltage supplied from the data line DLj is stored in the storage capacitor Cst. The sensing data voltage may be a specific voltage set irrespective of the input gray RGB in the sensing mode, and may be a voltage having a level capable of turning on the driving transistor. A positive driving current i_elvdd2 having an amount corresponding to a voltage difference between the first electrode and the second electrode of the storage capacitor Cst flows between the first electrode and the second electrode of the first transistor T1. Accordingly, the sensing unit 50 may sense the driving current i_elvdd2 flowing through the sensing line SELk or the voltage of the second electrode of the first transistor T1, and may perform analog-to-digital conversion on the sensed value to generate sensing data.

Next, when a scan signal having an off level (e.g., a low level) is applied through the first and second scan lines SL1i and SL2i, the second and third transistors T2 and T3 are turned off, and the data line DLj is electrically disconnected from the first electrode of the storage capacitor Cst. Therefore, even when the data voltage of the data line DLj changes, the voltage stored in the storage capacitor Cst does not change.

The embodiment is applicable not only to the pixel PXij of fig. 3 but also to pixels of other pixel circuits. For example, when the display devices DD and DD' further include an emission driver, the pixel PXij may further include a transistor connected to an emission line.

Referring to fig. 1, 2 and 5, during a sensing period SP in which the pixel unit 10 is driven in the sensing mode, the timing controller 20 may supply a second control signal CS2 having an on level (e.g., a high level) to the second power supply voltage generator 70 and may supply a first control signal CS1 having an off level (e.g., a low level) to the first power supply voltage generators 60 and 60'. The second power supply voltage generator 70 may supply the second power supply voltage ELVDD2 to the pixel unit 10 in response to the second control signal CS2, and the first power supply voltage generators 60 and 60' may be turned off in response to the first control signal CS 1.

Accordingly, during the sensing period SP, the high potential power supply voltage ELVDD may gradually increase and remain at the second power supply voltage ELVDD2. During the sensing period SP, the driving current i_elvdd may be a driving current i_elvdd2 flowing in the driving transistor based on the second power supply voltage ELVDD2. During the sensing period SP, the sensing data voltage may be set to a minimum level capable of turning on the driving transistor, and thus the driving current i_elvdd2 may be maintained at a level close to zero.

Next, during the display period DP in which the pixel unit 10 is driven in the display mode, the timing controller 20 may supply the first control signal CS1 having an on level (e.g., a high level) to the first power supply voltage generators 60 and 60', and may supply the second control signal CS2 having an off level (e.g., a low level) to the second power supply voltage generator 70. The first power voltage generators 60 and 60' may supply the first power voltage ELVDD1 to the pixel unit 10 in response to the first control signal CS1, and the second power voltage generator 70 may be turned off in response to the second control signal CS 2.

Accordingly, during the display period DP, the high potential power supply voltage ELVDD may gradually increase and remain at the first power supply voltage ELVDD1. Meanwhile, during the display period DP, the driving current i_elvdd may be the driving current i_elvdd1 flowing in the driving transistor based on the first power supply voltage ELVDD1. During the display period DP, the driving current i_elvdd1 may rise to a level corresponding to the data voltage of the input image.

Fig. 7 is a diagram for describing an operation of the overcurrent protection circuit according to one embodiment of the present application. In fig. 7, it is assumed that burnout occurs when the driving current i_elvdd flowing in the pixel unit 10 increases during the sensing period SP due to manufacturing process variations, generation of foreign substances, and the like.

Referring to fig. 6, an overcurrent protection circuit 71 according to one embodiment of the present application may operate in a sensing mode and may include a current detector 711 and a current limiter 712.

The current detector 711 may generate a driving current value by detecting a driving current i_elvdd2 flowing in a driving transistor included in each pixel PXij (see fig. 1) of the pixel cell 10. As described above, in the sensing mode, the driving current i_elvdd2 based on the second power supply voltage ELVDD2 supplied from the second power supply voltage generator 70 may flow in the driving transistor. The current detector 711 may supply a driving current value to the current limiter 712.

The current limiter 712 may determine whether to limit the current by comparing the driving current value supplied from the current detector 711 with the current limit value CLV.

The current limit CLV may be a set value for suppressing occurrence of burnout due to overcurrent, and I may be used ² The C communication is controlled by the timing controller 20. Further, the current limit CLV may be set to several tens to several hundreds of milliamperes, and may be subjected to analog-to-digital conversion and stored in the current limiter 712.

Referring to fig. 6 and 7, when the driving current value is less than the current limit CLV, the current limiter 712 may not limit the driving current i_elvdd. This is because, when the drive current value is smaller than the current limit CLV, the occurrence of burn-out is insignificant, and thus the influence of the overcurrent on the display device is insignificant.

On the other hand, when the driving current value is greater than or equal to the current limit CLV, the current limiter 712 may limit the driving current i_elvdd to the current limit CLV during the current limit period CLP. This is because burnout occurs when the drive current value is greater than or equal to the current limit CLV, and thus the influence of the overcurrent on the display device is significant.

The current limit period CLP may be an operation time of the overcurrent protection circuit 71, and I may be used ² The C communication is controlled by the timing controller 20. For example, the current limit period CLP may correspond to a period in which the driver is sensedA period of the threshold voltage Vth of the dynamic transistor and/or a period in which the mobility μ of the driving transistor is sensed. Therefore, the occurrence of burn-out in the sensing period SP is suppressed, thereby improving sensing accuracy and compensating for power with respect to the threshold voltage Vth and/or mobility μ of the driving transistor. Further, the current limit period CLP may be subjected to analog-to-digital conversion and stored in the current limiter 712.

Referring to fig. 6 and 7, after the current limit period CLP, the current limiter 712 may supply the off signal OS to the timing controller 20. The off signal OS refers to a signal for turning off the operation of the pixel unit 10. The timing controller 20 may supply the third control signal CS3 to each of the first and second power supply voltage generators 60 and 60 'and 70 in response to the off signal OS, and each of the first and second power supply voltage generators 60 and 60' and 70 may be turned off in response to the third control signal CS 3. Accordingly, after the current limit period CLP, the supply of the high-potential power supply voltage ELVDD to the pixel unit 10 may be stopped. That is, after the current limit period CLP, the voltage level of the high-potential power supply voltage ELVDD may be zero.

In one embodiment, the overcurrent protection circuit 71 may further include a filter unit (not shown) that stops the operation of the current limiter 712 when the driving current i_elvdd is at a peak value. The case in which the driving current i_elvdd is at a peak value may refer to a case in which the driving current i_elvdd is rapidly increased and then returned in a very short time, and may mean a phenomenon in which the driving current i_elvdd instantaneously jumps. That is, when the driving current i_elvdd is at a peak value, the filter unit (not shown) may stop the operation of the current limiter 712 to prevent the malfunction of the overcurrent protection circuit 71.

According to the embodiment of the present application, the stability and quality of the external compensation method can be improved, and the burn-out phenomenon can be suppressed.

However, the effects of the present application are not limited to the above-described effects, and various extensions can be made without departing from the spirit and scope of the present application.

Although the present application has been specifically described in terms of the above embodiments, it should be noted that the above embodiments are intended to illustrate the present application and not to limit the scope of the present application. Those skilled in the art to which the present application pertains will appreciate that various modifications can be made within the scope of the technical spirit of the present application.

The scope of the present application should not be limited to what is described in the detailed description of the specification, but rather by the claims. It is intended that all modifications and variations contemplated as within the scope of this application, by the meaning and scope of the claims and their equivalents.

Claims

1. A display device, characterized in that the display device comprises:

a pixel unit including a plurality of pixels;

a sensing unit connected to the plurality of pixels through a plurality of sensing lines;

a first power supply voltage generator connected to the plurality of pixels through a first power supply line and generating a first power supply voltage for driving the plurality of pixels;

a second power supply voltage generator connected to the plurality of pixels through the first power supply line and generating a second power supply voltage for sensing the plurality of pixels; and

and a timing controller selectively controlling operations of the first and second power supply voltage generators according to a driving mode of the pixel unit.

2. The display device according to claim 1, wherein when the pixel unit is driven in a display mode, the timing controller supplies a first control signal to the first power supply voltage generator, and the first power supply voltage generator supplies the first power supply voltage to the first power supply line in response to the first control signal.

3. The display device according to claim 1, wherein when the pixel unit is driven in the sensing mode, the timing controller supplies a second control signal to the second power supply voltage generator, and the second power supply voltage generator supplies the second power supply voltage to the first power supply line in response to the second control signal.

4. A display device according to claim 3, wherein,

the second supply voltage generator further includes an over-current protection circuit operating in the sense mode; and is also provided with

The overcurrent protection circuit includes a current detector that detects a driving current flowing through a driving transistor included in each of the plurality of pixels to generate a driving current value, and a current limiter that limits the driving current to a current limit value during a current limit period when the driving current value is greater than or equal to the current limit value.

5. The display device of claim 4, wherein the display device comprises a display panel,

after the current limiting period, the current limiter supplies a turn-off signal to the timing controller;

the timing controller supplies a third control signal to each of the first and second power supply voltage generators in response to the off signal; and is also provided with

Each of the first and second power supply voltage generators is turned off in response to the third control signal.

6. The display device according to claim 4, wherein the current limiting period corresponds to a period for sensing a threshold voltage of the driving transistor and/or a period for sensing mobility of the driving transistor.

7. The display device according to claim 4, wherein the overcurrent protection circuit further includes a filter unit that stops an operation of the current limiter when the drive current is at a peak value.

8. The display device according to claim 1, wherein a magnitude of the ripple voltage included in the second power supply voltage is smaller than a magnitude of the ripple voltage included in the first power supply voltage.

9. The display device according to claim 1, further comprising an input voltage generator that supplies an input voltage to the first power supply voltage generator,

wherein the first power supply voltage generator converts the input voltage to supply the first power supply voltage.

10. The display device according to claim 1, wherein the first power supply voltage is the same as or similar to an input voltage.