CN2206454Y

CN2206454Y - Car breakdown diagnosing analyser

Info

Publication number: CN2206454Y
Application number: CN 94201885
Authority: CN
Inventors: 孙桂华; 张小茜; 孙福山
Original assignee: COMPUTER INST TIANJIN
Current assignee: COMPUTER INST TIANJIN
Priority date: 1994-01-27
Filing date: 1994-01-27
Publication date: 1995-08-30
Anticipated expiration: 2004-01-27

Abstract

The utility model relates to a car fault diagnosing analyzer which is composed of a power switch, a housing, a control circuit board, etc. A clock in the circuit and a signal generated by the general restoration are connected with a CPU circuit, the CPU and a data processing circuit are provided with a plurality of data lines which mutually convey and are mutually connected with a decoding circuit through a plurality of address lines and data lines. The decoding circuit generates signals for separately controlling a keyboard, a ringing and a liquid crystal display. Various fault models which possibly appears in cars and rules for processing the faults are solidified in the chip by software program and Chinese language word stock and are selected and displayed by Chinese characters or signs. The car fault diagnosing analyser with small volume can be put in the pocket for carrying about, and the operation is very convenient.

Description

Car breakdown diagnosing analyser

The utility model relates to a kind of pocket automobile failure diagnosis analyser that is used for various gasoline cars of diagnostic analysis and diesel vehicle fault.

At present vehicle failure being judged mostly adopts the artificial experience that relies on oneself to judge and keep in repair, do like this for the driver who lacks experience, the accuracy of judging is relatively poor, thereby it is longer to be directed at the time of fixing a breakdown, even can not find failure cause sometimes at all.Especially in long-distance operation, the driver drives to be out of order can not find to seem more outstanding.At present domestic also have a vehicle failure program of utilizing the mainframe computer establishment, vehicle failure is judged and seek advice from, but mainframe computer is not easy to carry, and must be provided with the personal management, and use is subjected to great limitation.

The purpose of this utility model be to provide a kind of volume little, in light weight, be easy to carry, Chinese character shows the fault menu, fault takes place position is to the instrument that fault is provided corresponding solution.

The utility model be achieved in that its structure be by post on power supply, power switch, shell, the shell membrane keyboard, and control circuit board etc. constitute.It is characterized in that control circuit board; Claim CPU, data processing, decoding and keyboard, ring, liquid crystal display circuit by total clear, clock, main control, use chip (integrated circuit), Resistor-Capacitor Unit and printed circuit board to assemble.The various fault models that automobile may occur and the rule of handling failure all are solidificated in the software program Chinese word library and claim ROM in the relevant chip, by governor circuit CPU according to deposit position, rule, provide the control of data and address and read or write, with hanzi form by the liquid crystal display content, numeral or symbol by touch keyboard, the data that select to need, with the ring sound differentiate select to mistake.

Because this instrument all is solidificated in various faults and method for removing that automobile institute might occur among the corresponding EPRAM, and with Chinese demonstration.So anyone can use rapid failure judgement of this instrument and selection to solve the concrete grammar of fault according to explanation, the volume I is placed in the pocket to be carried, easy to use.

How further specify the purpose of this utility model below in conjunction with drawings and the specific embodiments realizes.

Fig. 1: automobile failure diagnosis analyser entire block diagram

Wherein: 1. total clear circuit 2. clocks 3. governor circuits 4. data processing circuits 5. decoding schemes 6. keyboard circuits 7. ringing circuits 8. liquid crystal display circuits 9. power supplys

Fig. 2: the total clear reset circuit of automobile failure diagnosis analyser

Fig. 3: automobile failure diagnosis analyser clock circuit

Fig. 4: automobile failure diagnosis analyser governor circuit

Fig. 5: automobile failure diagnosis analyser data processing circuit

Fig. 6: automobile failure diagnosis analyser decoding scheme

Fig. 7: automobile failure diagnosis analyser keyboard circuit

Fig. 8: automobile failure diagnosis analyser ringing circuit

Fig. 9: automobile failure diagnosis analyser liquid crystal display circuit

Shown in Fig. 1: after the energized (9), clock circuit (2) produces signal as CPU(3) major clock, simultaneously total clear reset circuit (1) postpones to treat that the stable back of power supply starts CPU(3) determining program in the reading of data treatment circuit (4), and with the assigned address start-up routine, reading of data in the fault model from decoding scheme (5), liquid crystal display Chinese character in liquid crystal display circuit (8), driver or maintenance personal can press keyboard correspondent button position sequential search vehicle failure reason place in the keyboard circuit (6) according to content displayed, and the sound decision operation in the ringing circuit (7) just or mistake.

Shown in Figure 2: total clear reset circuit (1) is made up of diode Q1, resistance R 1, capacitor C 1 or door H1.Resistance R 1, diode Q1, back in parallel is connected with power supply, and the other end is connected with the input end of capacitor C 1 or door H1, the other end ground connection of capacitor C 1, or the output terminal of door H1 is connected with cpu reset terminal RESET.

Diode selects for use IN4148, R1=100K Ω, C1=4.7 μ or door H2 to get 74HC32.

This reset circuit also can be made of 555 monostables, resistor-capacitor unit.Its effect is to power up the total clear negative pulse that the back produces 100～200s, begins excitation after stable to guarantee CPU powering up.

Shown in Figure 3: clock circuit (2), it is made up of phase inverter a1～a3, resistance R 2～R3, capacitor C 2 and crystal B.Two resistance are connected by capacitor C 2 respectively with after the input/output terminal parallel connection of phase inverter a1, a2, crystal B two ends are connected to the input end of phase inverter a1, a3, the output terminal of phase inverter a2 is connected with the input end of a3, and the output terminal of a3 is received CPU(3) CLK end be major clock.

Phase inverter is hex inverter 74HCO4, and a4-a6 handles to guarantee the power consumption minimum for Buddhism ground connection, and R2=R3 is that 10K Ω, C2=103p, crystal B are 4MHZ.

As shown in Figure 4: cpu circuit (3), form by chip D1, resistance R 4, capacitor C 3 or door H2～H4.Clock circuit (2) outputs to CPU(3) CLK end back produces two signal psi 1, φ 2 as system clock, the R/W end of signal and CPU through or door H3 receive the WR end of the SRAM static random memory of data processing circuit (4), make write operation, the R/W end of another signal and CPU arrives the RD end of the SRAM static random memory of data processing (4) equally through Sheffer stroke gate, do read operation.CPU shown in Fig. 4,5, the high address A15 of (3) receive the sheet choosing end EX of data processing circuit (4) program area EPROM through Sheffer stroke gate H4.RDY is ready to, IRQ interrupt request, NIQ not maskable interrupt, after the power Vcc parallel connection through capacitor C 3 to ground, the other end links to each other with power supply by resistance R 4.

Chip D1 selects for use 65CO2, R4=200 Ω, C3=103p or door H2, H4 and H3 to select 74HC00 and 74HC32 for use.

CPU(3) D1 also can adopt microprocessors such as 8031 series, 51 series, 96 series monolithics 6809 in.

As shown in Figure 5: data processing circuit (4), D2～D5 forms by chip, and D2 is program area EPROM1, EPROM2 for keeping in SRAM, D3 and D4, and D5 is that character library MASKROM forms.The sheet choosing end of D2～D5 is connected with the address that translates of decoding scheme (5) respectively.

D2-D5 selects 62C64,27C512,27C256 and 5199B respectively for use

As shown in Figure 7: keyboard circuit (6) is become by chip D6, resistance R 5～R8.The data of chip and address are transformed on the keyboard through overdriving, and keyboard is represented with " 0～9 ,-, " numbers and symbols.The data-driven output terminal of D6 arrives ground through resistance R 5-R8 respectively.The control end of D6 is connected with the output of decoding scheme (5).

Chip D6 selects 74HC244, R5-R8=33K Ω for use, and keyboard is selected the film touch keyboard for use

As shown in Figure 6: decoding scheme (5) is made up of chip D7 and Sheffer stroke gate H5.Decoder chip D7 is that SRAM, EPROM, the sheet choosing end of MASKROM, the CLK end of ringing circuit (7), another end points that the scope of its decoding of address decoding: 0000～7FFF receives data processing (4) respectively is connected on the control end of display circuit (8) by Sheffer stroke gate H5.

Coding chip D7 selects two-24 code translators of 74HC139 for use, and 74HC00 is a NAND gate circuit.

Decoding scheme (5) can also be realized by gate circuit or gate-array circuit.

As shown in Figure 9: display circuit (8) is made up of liquid crystal E2 and potentiometer W.The Vee of another termination liquid crystal of the power Vcc of one termination liquid crystal of potentiometer E2, the Vo reference point of a termination liquid crystal E2 again.Receive the control end of E2 through Sheffer stroke gate H5 by decoding scheme (5).

E2 selects DG-12864, W=20K for use

The control line of E2 also can be by address wire or code translator control.

As shown in Figure 8: ringing circuit (7) is made up of chip D8, resistance R 9, R10, triode Q2, buzzer E1.Chip D8 drives output and is connected to demonstration (8) CS1, CS2 control end, and another exports the base stage of termination R9 to triode, grounded emitter, and collector connects the negative terminal of buzzer, and the positive terminating resistor R10 of buzzer is connected with power supply, the total clear signal of CLEAR termination.

It is that C945, buzzer E1 are TMB-05 that D8 selects 74HC273, R9=6.2K Ω, R10=200 Ω, triode Q2 for use.

Fig. 1 to the circuit diagram shown in Figure 9, its address wire and data line all successively correspondence interconnect, the CPU access program all is through address wire and data line exchange.

Selected chip and components and parts are welded in and claim control circuit board in the printed board according to Fig. 1～9 circuit diagrams dress.The 128*64 lattice lcd shows and the 3*4 membrane keyboard is contained in plastic casing surface (deserving to be called lid or panel) by screw, loam cake has liquid crystal display and power switch window, lower house is provided with little bottom and concealed installation battery case, handle covers to indicate pushes direction open, the battery dress within it, by rim of the mouth and raised tooth and lower house locking, the interface of lower house and loam cake is also used the rim of the mouth and the concavo-convex locking of general normal use.

Claims

1, automobile failure diagnosis analyser, constitute by power switch, shell, control circuit board etc., it is characterized in that the circuit in the control circuit board: clock is connected with cpu circuit with the signal of total clear reset generation, CPU and data processing circuit have many data lines to transmit mutually, interconnect by many address wires, data line and decoding scheme again, decoding scheme produces signal supervisory keyboard, ring, liquid crystal display respectively, and the various fault models that automobile may occur and the rule of handling failure are solidificated in the chip with software program, Chinese word library.

2, according to the described automobile failure diagnosis analyser of claim 1, it is characterized in that shell is made up of two parts up and down, membrane keyboard is attached to cap surface, and be provided with liquid crystal display and power switch window, lower house is provided with bottom and concealed installation battery case, handle covers to indicate pushes direction open, and by rim of the mouth and projection and lower house locking, the interface of lower house and loam cake is by rim of the mouth and concavo-convex locking.

3, according to the described automobile failure diagnosis analyser of claim 1, it is characterized in that total clear circuit (1) is made up of diode Q1, resistance R 1, capacitor C 1 or a door H1, resistance R 1, be connected with power supply after the diode Q1 parallel connection, the other end is connected with the input end of capacitor C 1 or door H1, the other end ground connection of capacitor C 1, or the output terminal of door H1 is connected with the cpu reset terminal.

4, according to the described automobile failure diagnosis analyser of claim 1, it is characterized in that clock circuit (2) is made up of phase inverter a1～a3, resistance R 2～R3, capacitor C 2 and crystal B, two resistance R, 2～R3 is connected by capacitor C 2 respectively with after the input/output terminal parallel connection of phase inverter a1, a2, crystal B two ends are connected to the input end of phase inverter a1, a3, the output terminal of phase inverter a2 is connected with the input end of a3, and the output terminal of a3 is received CPU(3) CLK end be major clock.

5, according to the described automobile failure diagnosis analyser of claim 1, it is characterized in that cpu circuit (3), form by chip D1 resistance R 4 capacitor C 3 or door H2 to H4, clock circuit (2) outputs to CPU(3) behind the CLK end, produce two signals as clock signal of system, the R/W end of signal and CPU through or door H3 receive the WR end of the SRAM of data processing (4), the R/W end of another signal and CPU is received the RD end of the SRAM of data processing (4) through Sheffer stroke gate H2, the sheet choosing end of data processing circuit (4) program area EPROM is received in the high address through Sheffer stroke gate H4, RDY is ready to, the IRQ interrupt request, NIQ not maskable interrupts, arrive ground through capacitor C 3 after the power Vcc parallel connection, the other end links to each other with power supply by resistance R 4.

6, according to the described automobile failure diagnosis analyser of claim 5, it is characterized in that CPU(3) can also adopt 8031 series or 51 series or 96 series or single-chip microcomputer or 6809 microprocessors.

7, according to the described automobile failure diagnosis analyser of claim 1, it is characterized in that data place circuit (4) is made up of chip D2～D5, D2 is temporary SRAM, D3, D4 are process simulation EPRAM1, EPRAM2, D5 is character library MASKROM, all be connected with power supply by power end, the sheet choosing end of D2～D5 is connected with the high address of decoding (5) respectively.

8, according to the described automobile failure diagnosis analyser of claim 1, it is characterized in that keyboard circuit (6) is by chip D6, resistance R 5 to R8 is formed, data and address are transformed on the keyboard through driver, keyboard represents with " 0～9 ,-,, " numbers and symbols, the data-driven output of D6 respectively connecting resistance R5～R8 to ground.The control end of D6 is connected with the output terminal of decoding scheme (5).

9, according to the described automobile failure diagnosis analyser of claim 1, it is characterized in that decoding scheme (5) is made up of chip D7 Sheffer stroke gate H5, decoder chip D7 is an address decoding, its high address translates scope: 0000～77FF receives SRAM, the EPROM of data processing circuit (4) respectively, the sheet of MASKROM selects on the CLK end of end and ringing circuit (7), and the other end is received on the control end of display circuit (8) through Sheffer stroke gate H5.

10,, it is characterized in that decoding scheme (5) can also be by gate circuit or gate-array circuit realization according to the described automobile failure diagnosis analyser of claim 1.

11, according to the described automobile failure diagnosis analyser of claim 1, it is characterized in that display circuit (8) is made up of liquid crystal E2, potentiometer W, the power Vcc of one termination liquid crystal E2 of potentiometer, the Vee of another termination liquid crystal E2, intermediate ends is connected with the Vo of liquid crystal E2.

12, according to the described automobile failure diagnosis analyser of claim 1, it is characterized in that liquid crystal display circuit (8), the control line of E2 also can be by the control of address wire or decoding.

13, according to the described automobile failure diagnosis analyser of claim 1, it is characterized in that ringing circuit (7) is made up of chip D8, resistance R 9, R10, triode Q2, buzzer E1, the drive output of chip D8 connects demonstration (8) CS1, CS2 control end, another output terminal connecting resistance R9 is to the base stage of triode Q2, grounded emitter, collector connects buzzer E1 negative terminal, and the anode of buzzer is contacted a resistance R 10 to Vcc, the total clear signal of CLEAR termination.