CN220629177U - Overcurrent protection circuit of transistor - Google Patents
Overcurrent protection circuit of transistor Download PDFInfo
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- CN220629177U CN220629177U CN202321853558.5U CN202321853558U CN220629177U CN 220629177 U CN220629177 U CN 220629177U CN 202321853558 U CN202321853558 U CN 202321853558U CN 220629177 U CN220629177 U CN 220629177U
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Abstract
The utility model discloses an overcurrent protection circuit of a transistor, which has two protection mechanisms: inverter peak current limit and starting capability limit. The peak current limit of the inverter ensures that the inverter does not directly stop working when a plurality of devices or devices accompanied with large current at the moment of starting are driven, but continuously circulates again to wait for the complete starting of the devices; the starting capability limitation is a further measure of protection of the aerodynamic capability of the inverter on the basis of the peak current limitation of the inverter.
Description
Technical Field
The utility model relates to the technical field of overcurrent protection, in particular to an overcurrent protection circuit of a transistor.
Background
The inverter is used as a common direct current-to-alternating current converter, a plurality of transistors are used for direct current-to-alternating current energy conversion, and an overcurrent protection circuit is required to be designed on the transistors so as to ensure that irreversible damage can not be caused to the inverter when the connected equipment breaks down or is in short circuit. However, for devices that require a large current at the moment of starting, such as connecting a plurality of devices or connecting some motors, such a protection circuit may cause the devices to fail to start normally.
Most of the current common inverters do not have transistor hardware protection, and the transistor control signals are fed back and regulated based on software monitoring of output currents. In addition, in the case of connecting a plurality of devices, the triggering of the overcurrent protection can be avoided by a one-by-one starting method at present, but the control is required to be manually participated.
The mode of detecting the output current feedback control signal based on the software has a certain risk, and when the monitoring signal is abnormal or disturbed, the software can run away to the transistor to generate explosion. In order to meet the normal starting of a plurality of devices, the devices are manually participated in one by one power-on. When the equipment is a single motor and other loads, the starting cannot be realized by adopting a one-by-one power-on method.
Disclosure of Invention
The utility model aims at overcoming the technical defects in the prior art and discloses an overcurrent protection circuit of a transistor.
In order to achieve the purpose of the utility model, the technical scheme adopted by the utility model is as follows:
the over-current protection circuit of the transistor comprises an inverter peak current limiting circuit, wherein one end of the inverter peak current limiting circuit is electrically connected with one end of a first resistor, one end of an equipment initialization protection circuit and one end of the inverter starting capability limiting circuit, one end of the inverter peak current limiting circuit is provided with a first interface, the first interface is electrically connected with a logic gate circuit, the other end of the inverter peak current limiting circuit is electrically connected with the other end of the inverter starting capability limiting circuit, and the other end of the inverter peak current limiting circuit is provided with a second interface; the other end of the first resistor is electrically connected with an inverter peak current limiting circuit, an equipment initialization protection circuit and an inverter starting capability limiting circuit; the inverter starting capability limiting circuit comprises a capacitor charging and discharging circuit and a D trigger triggering circuit.
Further, the peak current limiting circuit of the inverter comprises a first optocoupler, a first pin of the first optocoupler is electrically connected with one end of a fourth resistor, the other end of the fourth resistor is electrically connected with one end of a second resistor, one end of a third capacitor, one end of the third resistor, an eighth pin of a first comparator and an inverter starting capability limiting circuit, the other end of the third resistor is electrically connected with a second pin of the first optocoupler and a first pin of the first comparator, the third pin of the first optocoupler is electrically connected with one end of the first capacitor and a ground signal, the other end of the first capacitor is electrically connected with one end of a fifth resistor, a second diode cathode and a fourth pin of the first optocoupler, the other end of the fifth resistor is electrically connected with the other end of the first resistor and an inverter starting capability limiting circuit, an anode of the second diode is electrically connected with one end of the first resistor and an equipment starting capability limiting circuit, the fourth pin of the first comparator is grounded, the third pin of the first comparator is electrically connected with the other end of the second resistor and one end of the ninth resistor, the other end of the ninth resistor is grounded, the second pin of the first comparator is electrically connected with the other end of the seventh resistor, and the other end of the seventh resistor is grounded.
Further, a second interface is arranged at the other end of the seventh resistor, and a first interface is arranged at the anode of the second diode.
Further, the ninth resistor is a varistor.
Further, the capacitor charge-discharge circuit comprises a second optocoupler, a first pin of the second optocoupler is electrically connected with one end of a thirteenth resistor, the other end of the thirteenth resistor is electrically connected with one end of an eighteenth resistor, one end of a twelfth resistor and an inverter peak current limiting circuit, the other end of the eighteenth resistor is electrically connected with a second pin of the second optocoupler and a seventh pin of a second comparator, a third pin of the second optocoupler is electrically connected with one end of a fifth capacitor and a ground signal, the other end of the fifth capacitor is electrically connected with one end of a fourteenth resistor, a fourth pin of the second optocoupler and a trigger circuit, the other end of the fourteenth resistor is electrically connected with the trigger circuit, a fifth pin of the second comparator is electrically connected with the other end of the twelfth resistor and one end of a twentieth resistor, the other end of the twentieth resistor is grounded, the sixth pin of the second comparator is electrically connected with one end of the seventeenth resistor and the positive electrode of the sixth capacitor, the negative electrode of the sixth capacitor and the other end of the nineteenth resistor are grounded, the other end of the seventeenth resistor is electrically connected with a fifth diode cathode, and the fifth diode anode is electrically connected with the inverter peak current limiting circuit.
Further, the fifth diode anode is provided with a second interface.
Further, the twentieth resistor is a varistor.
Further, the trigger circuit of the D trigger comprises a D trigger, a first pin of the D trigger is electrically connected with an anode of a sixth diode, a cathode of the sixth diode is electrically connected with a cathode of a fourth diode, one end of a fifteenth resistor and a capacitor charge-discharge circuit, a third pin of the D trigger is electrically connected with one end of an eleventh resistor and a collector of a second triode, a base of the second triode is electrically connected with the other end of the fifteenth resistor, an emitter of the second triode is electrically connected with a seventh pin of the D trigger, a fifth pin of the D trigger, a fourth pin of the D trigger, an emitter of the first triode and one end of a fourth capacitor as well as ground signals, a collector of the first triode is electrically connected with one end of the sixteenth resistor and the other end of the fourth capacitor, a reset pin is arranged at the other end of the sixteenth resistor, the fourteenth pin of the D trigger, the other end of the eleventh resistor and the other end of the tenth resistor are all electrically connected with the other end of the first resistor, the capacitor charge-discharge circuit and the peak current limiting circuit of the inverter, and one end of the fourth diode anode is electrically connected with one end of the first resistor.
Further, the anode of the fourth diode is provided with a first interface.
Further, the equipment initialization protection circuit comprises a third diode, wherein the anode of the third diode is electrically connected with one end of the first resistor and the peak current limiting circuit of the inverter, the cathode of the third diode is electrically connected with the anode of the first diode, the anode of the second capacitor and one end of the sixth resistor, the cathode of the first diode is electrically connected with the other end of the first resistor, the peak current limiting circuit of the inverter and the starting capacity limiting circuit of the inverter, and the other ends of the cathode of the second capacitor and the sixth resistor are grounded.
Compared with the prior art, the utility model has the advantages that:
the starting capability of the using load can be improved under the condition that the transistor is not excessively flowed; the transistor is subjected to overcurrent protection by realizing the peak current limitation and the starting capacity limitation of the inverter through a circuit without the participation of software; two protection mechanisms are provided, so that overcurrent protection can be better carried out; when the equipment has actual faults, the electrical connection between the inverter and the faulty equipment can be effectively cut off in time, so that the safety of the inverter is ensured.
Drawings
FIG. 1 is a circuit diagram of transistor over-current protection;
FIG. 2 is a circuit diagram of an inverter peak current limit;
fig. 3 is an inverter startup capability limiting circuit diagram;
fig. 4 is a device initialization protection circuit diagram.
Detailed Description
The utility model is described in further detail below with reference to the drawings and the specific examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the utility model.
The design has two protection mechanisms:
1. inverter peak current limit. When the output current value of the inverter exceeds the set critical value, the output of the inverter is cut off, and an inductor exists on the H bridge of the inverter, and the current on the inductor is gradually changed. If the output current value returns to below the critical value, the inverter continues to work normally, otherwise, the process is circularly executed. The design limits the output current value of the inverter to the set threshold value, and ensures that the inverter cannot directly stop working when a plurality of devices or devices accompanied with large current at the moment of starting are driven. But rather wait for the device to start up completely in a continuous loop. The number of cycles, i.e. the starting capability of the inverter to the device, is controlled by the following protection mechanism.
2. And (5) a starting capability limitation. As described above, the inverter limits the peak current without stopping the output, thereby ensuring that the connected device is gradually started. However, if this is done for a long time, it can be determined that the load of the connected device is too large, it is difficult to start normally, or the device has failed. At this time, the starting capability limiting circuit will completely shut off the inverter output. In the case where the reset operation is not performed manually, the inverter will not resume operation. The starting capacity threshold value is adjustable and can be adjusted according to actual conditions.
The circuit structure and principle are as follows:
1. inverter peak current limiting circuit
As shown in fig. 2, IBUS is the sampled value of the current on the H-bridge (inverter output); u2 is a comparator of model LM 393; r7, R8, R2 and R9 are respectively voltage dividing resistors at two paths of input ends of the comparator, wherein R9 is an adjustable resistor; c3 is a filter capacitor at the power input end of the comparator; u1 is a photoelectric coupler of a model TLP 785; r3 is a pull-up resistor, and R4 is an optocoupler input side current limiting resistor; r5 is a pull-up resistor at the output side of the optocoupler, and C1 is a filter capacitor; d2 is a diode; r1 is a pull-up resistor;
principle of: there is an inductance on the H-bridge, on which the current is not instantaneously abrupt, but gradually varies. The value on pin IBUS reflects the magnitude of the current on the H-bridge, i.e., the magnitude of the inverter output current;
the pin IGBT is externally connected with a logic gate circuit and participates in controlling the on-off of an IGBT (insulated gate bipolar transistor) on an H bridge, and the logic is briefly described as follows: the pin is high level, and the IGBT tube can be controlled to be conducted by the CPU. The pin is low level, the IGBT tube is not conducted, and the inverter stops outputting.
The "pin 3" of the comparator U2 is a reference voltage, which is a set peak current threshold, and the magnitude of which can be changed by the adjustable resistor R9. And the pin 2 is the voltage of the IBUS after the voltage is divided by the resistor. When the current on the H-bridge exceeds a set threshold, i.e., the voltage on "pin 2" is greater than the voltage on "pin 3", the comparator outputs a low level. At this time, the optocoupler U1 is turned on, the pin IGBT is connected to ground, the output low level, and the inverter stops outputting. When the current on the H bridge is lower than the set critical value, the comparator outputs a high level, the optocoupler is not conducted, the pin IGBT is pulled up to the high level through the resistor R1, and the inverter recovers to output. The diode D2 is used to prevent the voltage on the output side of the optocoupler from affecting the subsequent stage circuit.
The logic of the circuit is as follows: in a normal operating state, the inverter maintains output. When the output current of the inverter exceeds a set critical value, the inverter is controlled to stop outputting temporarily, and the output current is turned on again after the output current is reduced below a threshold value. If a large current still occurs at this time, the process is cycled.
2. Inverter starting capability limiting circuit
As shown in fig. 3, this circuit is composed of two parts.
Part one: d5 is a diode, and C6 is an electrolytic capacitor of 22 muf/50V; r17, R19, R12 and R20 are respectively voltage dividing resistors at two paths of input ends of the comparator, wherein R20 is an adjustable resistor; u2 is the other path of the comparator of model LM 393; r18 is a pull-up resistor, and R13 is a limiting resistor; u4 is a photoelectric coupler of a model TLP785, R14 is a pull-up resistor at the output side of the photoelectric coupler, and C5 is a filter capacitor.
Principle of: the "pin 5" of the comparator U2 is a reference voltage, which is a set threshold of the starting capability, and its magnitude can be changed by the adjustable resistor R19. When the inverter has output, the IBUS charges the capacitor through the resistor R17; when the inverter stops outputting, the capacitor discharges through the resistor R19. The resistance value of the resistor R17 is far smaller than R19, so that the capacitor charging time is ensured to be smaller than the capacitor discharging time.
Under the normal working state, the voltage value of the U2 pin 6 is obtained by subtracting the voltage drop of the diode D5 from the IBUS and then dividing the voltage by a resistor. Even if the capacitor is full, its voltage is less than the threshold voltage. At this time, the comparator outputs a high level, the optocoupler U4 is not turned on, and the node Uh is at a high level (output side voltage of the optocoupler U4).
When the output current of the inverter exceeds the set peak value, the IBUS voltage increases, the capacitor C6 is further charged, and the voltage value of the "pin" 6 gradually increases. Because the peak current limiting circuit exists, the increased IBUS voltage only exists for a moment, and the capacitor needs to be charged for a time (determined by the resistor R17 and the value of the capacitor), the voltage of the "pin 6" does not exceed the set threshold, and the node Uh is still at a high level.
Only when the inverter is over-peaking output for a certain time, i.e. the peak current limiting circuit is cycled for a certain number of times. The voltage of the capacitor C6 may exceed the set threshold. At this time, the comparator outputs a low level, the optocoupler U4 is turned on, and the node Uh is at a low level. The threshold of the starting capability is regulated, so that the protection action output can be controlled after the number of times of circulation.
Part two: pin CPU_FW is a manual reset pin, and the CPU outputs a high level in a normal state; u3 is a D trigger with the model of MC 14013B; r15 and R16 are current limiting resistors; r10 and R11 are pull-up resistors; v1 and V2 are triodes with the model of MMBT 4401; d4 D6 is a diode;
principle of: the Data and Reset pin designs of the D flip-flop remain low.
(1) In the initial state, the Data and Reset pins are 0 and the set pin is pulled up to high by R10. At this time, the flip-flop pin Q outputs a high level.
(2) In a normal state (normal working state), the CPU outputs a high level to the cpu_fw pin, the transistor V1 is thus turned on, and the SET pin is SET to a low level. At this time, the flip-flop is not operated, and pin Q still outputs a high level.
(3) When the Uh voltage is at a high level, the triode V2 is conducted, and the pin CLK is set at a low level; when the Uh voltage jumps to a low level, V2 is not conductive and pin CLK is pulled up to a high level by R11. At this point, the rising edge of CLK occurs and the Data, reset and Set pins are all low, and the flip-flop pin Q will remain output low.
(4) When the trigger pin Q is low, the pin IGBT is pulled low. At this time, the IGBT on the H bridge is turned off at the same time, and the inverter stops outputting.
(5) The CPU sends a reset signal, i.e. outputs a low level to the CPU FW pin, transistor V1 is not turned on, and pin SET is pulled up to a high level. At this time, the trigger pin Q outputs high level, the trigger returns to normal state, and the H bridge returns to original normal working state.
The logic of the circuit is as follows: when the inverter is in a normal working state or short-time over-peak output occurs, the protection circuit is not started. When the inverter has an excessive peak output for a long time, the protection circuit acts to control the inverter to stop outputting, and in the case where the CPU does not give a reset signal, the inverter will not resume outputting. Further, the inverter duration over-peak output time may be varied by adjusting the starting capability threshold.
3. Equipment initialization protection circuit
As shown in fig. 4, the pin IGBTs are externally connected with a logic gate circuit to participate in controlling the on-off of all the IGBT tubes; r1 is a pull-up resistor, and R6 is a capacitor discharge resistor; d1 and D3 are diodes; c2 is an electrolytic capacitor of 22. Mu.f/50V.
Principle of: at the system initialization moment, the 5V power supply charges the capacitor C2 through the resistor R1, the pin IGBT voltage slowly rises, the low level is maintained for a period of time, and the inverter is controlled not to output. The design ensures that the inverter does not malfunction when the system is initialized.
The foregoing is merely a preferred embodiment of the present utility model and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present utility model, which are intended to be comprehended within the scope of the present utility model.
Claims (10)
1. An overcurrent protection circuit for a transistor, comprising an inverter peak current limiting circuit, characterized in that: one end of the inverter peak current limiting circuit is electrically connected with one end of a first resistor (R1), one end of the equipment initialization protection circuit and one end of the inverter starting capability limiting circuit, one end of the inverter peak current limiting circuit is provided with a first Interface (IGBT), the first Interface (IGBT) is electrically connected with the logic gate circuit, the other end of the inverter peak current limiting circuit is electrically connected with the other end of the inverter starting capability limiting circuit, and the other end of the inverter peak current limiting circuit is provided with a second Interface (IBUS); the other end of the first resistor (R1) is electrically connected with the inverter peak current limiting circuit, the equipment initialization protection circuit and the inverter starting capability limiting circuit; the inverter starting capability limiting circuit comprises a capacitor charging and discharging circuit and a D trigger triggering circuit.
2. The overcurrent protection circuit of claim 1, wherein: the peak current limiting circuit of the inverter comprises a first optocoupler (U1), a first pin of the first optocoupler (U1) is electrically connected with one end of a fourth resistor (R4), the other end of the fourth resistor (R4) is electrically connected with one end of a second resistor (R2), one end of a third capacitor (C3), one end of the third resistor (R3), an eighth pin of a first comparator (U2A) and an inverter starting capacity limiting circuit, the other end of the third resistor (R3) is electrically connected with a second pin of the first optocoupler (U1) and a first pin of a first comparator (U2A), the third pin of the first optocoupler (U1) is electrically connected with one end of a first capacitor (C1) and a ground signal, the other end of the first capacitor (C1) is electrically connected with one end of a fifth resistor (R5), a cathode of a second diode (D2) and a fourth pin of the first optocoupler (U1), the other end of the fifth resistor (R5) is electrically connected with the other end of the first resistor (R1) and the inverter starting capacity limiting circuit, the other end of the second resistor (R2A) is electrically connected with the other end of the third resistor (U2A 2) and the first pin (R2A), the other end of the first resistor (R2) is connected with the other end of the first resistor (R2A) and the third resistor (R2) is connected with the end of the first resistor (R2) and the first pin (R2) and the end of the first resistor (R2) and the second end of the fourth resistor (R2) and the fourth resistor (C3) and the third end is connected with the cathode, the other end of the eighth resistor (R8) is grounded, the other end of the seventh resistor (R7) is electrically connected with the inverter starting capability limiting circuit, and the other end of the third capacitor (C3) is grounded.
3. The overcurrent protection circuit of claim 2, wherein: the other end of the seventh resistor (R7) is provided with a second Interface (IBUS), and the anode of the second diode (D2) is provided with a first Interface (IGBT).
4. The overcurrent protection circuit of claim 2, wherein: the ninth resistor (R9) is a varistor.
5. The overcurrent protection circuit of claim 1, wherein: the capacitor charge-discharge circuit comprises a second optocoupler (U4), a first pin of the second optocoupler (U4) is electrically connected with one end of a thirteenth resistor (R13), the other end of the thirteenth resistor (R13) is electrically connected with one end of an eighteenth resistor (R18), one end of a twelfth resistor (R12) and an inverter peak current limiting circuit, the other end of the eighteenth resistor (R18) is electrically connected with a second pin of the second optocoupler (U4) and a seventh pin of a second comparator (U2B), a third pin of the second optocoupler (U4) is electrically connected with one end of a fifth capacitor (C5) and a ground signal, the other end of the fifth capacitor (C5) is electrically connected with one end of a fourteenth resistor (R14), the other end of the second optocoupler (U4) is electrically connected with a D trigger circuit, the other end of the twelfth resistor (R14) is electrically connected with the D trigger circuit, the other end of the twenty-fourth resistor (R20), the twenty-second pin of the twenty-second comparator (U2B) is electrically connected with one end of the twenty-second resistor (R20), the other end of the twenty-fourth resistor (R20) is electrically connected with the other end of the nineteenth resistor (R19) and the other end of the nineteenth resistor (R5) is connected with the other end of the nineteenth resistor (R6) which is connected with the cathode (R19), the fifth diode (D5) anode is electrically connected to the inverter peak current limiting circuit.
6. The overcurrent protection circuit of claim 5, wherein: the fifth diode (D5) anode is provided with a second Interface (IBUS).
7. The overcurrent protection circuit of claim 5, wherein: the twentieth resistor (R20) is a varistor.
8. The overcurrent protection circuit of claim 1, wherein: the trigger circuit of the D trigger comprises a D trigger (U3), a first pin of the D trigger (U3) is electrically connected with an anode of a sixth diode (D6), a cathode of the sixth diode (D6) is electrically connected with a cathode of a fourth diode (D4), one end of a fifteenth resistor (R15) and a capacitor charge-discharge circuit, a third pin of the D trigger (U3) is electrically connected with one end of an eleventh resistor (R11) and a collector of a second triode (V2), a base of the second triode (V2) is electrically connected with the other end of a fifteenth resistor (R15), an emitter of the second triode (V2) is electrically connected with a seventh pin of the D trigger (U3), a fifth pin of the D trigger (U3), a fourth pin of the D trigger (U3), an emitter of the first triode (V1) and a ground signal, one end of a fourth capacitor (C4) are electrically connected with one end of a tenth resistor (R10), a base of the first triode (V1) is electrically connected with one end of the sixteenth resistor (R3), a base of the fourth triode (V1) is electrically connected with the other end of the fourth resistor (R11) and the other end of the fourth resistor (R11) is electrically connected with the other end of the fourth resistor (R4) of the fourth resistor (R1) and the other end of the trigger circuit is electrically limited by the trigger circuit, the anode of the fourth diode (D4) is electrically connected with one end of the first resistor (R1).
9. The overcurrent protection circuit of claim 8, wherein: the anode of the fourth diode (D4) is provided with a first Interface (IGBT).
10. The overcurrent protection circuit of claim 1, wherein: the equipment initialization protection circuit comprises a third diode (D3), wherein the anode of the third diode (D3) is electrically connected with one end of a first resistor (R1) and an inverter peak current limiting circuit, the cathode of the third diode (D3) is electrically connected with the anode of the first diode (D1), the anode of a second capacitor (C2) and one end of a sixth resistor (R6), the cathode of the first diode (D1) is electrically connected with the other end of the first resistor (R1), the inverter peak current limiting circuit and an inverter starting capacity limiting circuit, and the cathodes of the second capacitor (C2) and the other end of the sixth resistor (R6) are grounded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321853558.5U CN220629177U (en) | 2023-07-14 | 2023-07-14 | Overcurrent protection circuit of transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321853558.5U CN220629177U (en) | 2023-07-14 | 2023-07-14 | Overcurrent protection circuit of transistor |
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| Publication Number | Publication Date |
|---|---|
| CN220629177U true CN220629177U (en) | 2024-03-19 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
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| CN202321853558.5U Active CN220629177U (en) | 2023-07-14 | 2023-07-14 | Overcurrent protection circuit of transistor |
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| CN (1) | CN220629177U (en) |
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- 2023-07-14 CN CN202321853558.5U patent/CN220629177U/en active Active
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