CN220626943U

CN220626943U - Clock circuit and battery pack

Info

Publication number: CN220626943U
Application number: CN202322366401.6U
Authority: CN
Inventors: 彭庚
Original assignee: Eve Energy Co Ltd
Current assignee: Eve Energy Co Ltd
Priority date: 2023-08-31
Filing date: 2023-08-31
Publication date: 2024-03-19
Anticipated expiration: 2033-08-31

Abstract

The utility model relates to a clock circuit and a battery pack, wherein the clock circuit comprises: the clock chip is provided with a chip power supply end, a communication end and an interrupt end; the power module is used for providing power for the clock chip; the communication module is used for communication between the processor and the clock chip; and the interrupt module is used for waking up the clock chip at regular time. The utility model can solve the problem of self-holding of the system time after the battery management unit is powered down in the transportation process of the battery system.

Description

Clock circuit and battery pack

Technical Field

The utility model relates to the technical field of batteries, in particular to a clock circuit and a battery pack.

Background

With the widespread use of energy storage battery systems, battery management units (Battery Management Unit, BMU) of the battery systems are becoming increasingly concerned with the problem of maintaining power down during system time during transportation.

In the related art, there are two general schemes for maintaining the system time of the battery management unit: one is to calibrate the system time on site by the installer after the battery system is transported to the destination, which can ensure accurate system time and high stability, but adds the installation procedure and operation process, and increases the cost in an intangible way. In addition, the scheme is that a power management chip is integrated on the battery management unit or a button battery power supply circuit is designed, so that the technical process of a field installer is simplified, the time is saved, the convenience and the efficiency are improved, the cost is increased from the design level, and the design difficulty and the time are also increased due to the fact that the size of the battery management unit is larger when the circuit board is arranged.

Disclosure of Invention

In view of the above, the utility model provides a clock circuit and a battery pack, which can flexibly select a small-capacity super capacitor according to the transportation time length, and the super capacitor has the advantages of small capacity, small volume, convenient layout, flexible wake-up of a clock chip during the design of a circuit board, reduced power consumption, and improved working reliability due to a simple circuit structure, thereby solving the problem of self-holding of the system time after the battery management unit is powered down during the transportation of the battery system.

In a first aspect, an embodiment of the present utility model provides a clock circuit applied to a battery management unit having a processor disposed therein, the clock circuit including: the clock chip is provided with a chip power supply end, a communication end and an interrupt end; the power module is electrically connected to the power end of the chip and is used for providing power for the clock chip; the communication module is electrically connected with the processor and the communication end and is used for communication between the processor and the clock chip; and the interrupt module is electrically connected with the interrupt end and is used for waking up the clock chip at regular time.

In a second aspect, embodiments of the present utility model provide a battery pack including a battery management unit and the clock circuit.

The power supply module is utilized to provide power for the clock chip, and the small-capacity super capacitor can be flexibly selected according to the transportation time according to aspects of the utility model, so that the layout is more convenient when the circuit board is designed, and meanwhile, the clock circuit can flexibly wake up the clock chip by arranging the communication module and the terminal module, so that the power consumption is reduced, the working reliability is improved due to a simple circuit structure, and the problem of self-holding of the system time after the battery management unit is powered down in the transportation process of the battery system is solved.

Drawings

The technical solution and other advantageous effects of the present utility model will be made apparent by the following detailed description of the specific embodiments of the present utility model with reference to the accompanying drawings.

Fig. 1 shows a schematic diagram of a clock circuit of an embodiment of the utility model.

Detailed Description

The technical solutions in the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model. It will be apparent that the described embodiments are only some, but not all, embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to fall within the scope of the utility model.

In the description of the present utility model, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present utility model. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more of the described features. In the description of the present utility model, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

In the description of the present utility model, it should be noted that, unless explicitly stated otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically connected, electrically connected or can be communicated with each other; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements or interaction relationship between the two elements. The specific meaning of the above terms in the present utility model can be understood by those of ordinary skill in the art according to the specific circumstances.

The following disclosure provides many different embodiments, or examples, for implementing different features of the utility model. In order to simplify the present disclosure, components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present utility model. Furthermore, the present utility model may repeat reference numerals and/or letters in the various examples, which are for the purpose of brevity and clarity, and which do not themselves indicate the relationship between the various embodiments and/or arrangements discussed. In addition, the present utility model provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize the application of other processes and/or the use of other materials. In some instances, well known methods, procedures, components, and circuits have not been described in detail so as not to obscure the present utility model.

The present utility model mainly provides a Clock circuit, which may be a Real Time Clock (RTC) for a battery management unit of an energy storage battery system, where a processor is disposed in the battery management unit, and the Clock circuit includes: the clock chip is provided with a chip power supply end, a communication end and an interrupt end; the power module is electrically connected to the power end of the chip and is used for providing power for the clock chip; the communication module is electrically connected with the processor and the communication end and is used for communication between the processor and the clock chip; and the interrupt module is electrically connected with the interrupt end and is used for waking up the clock chip at regular time.

Fig. 1 shows a schematic diagram of a clock circuit of an embodiment of the utility model. As shown in fig. 1, the clock circuit may include a clock chip 10 (i.e., U1 in fig. 1), a power module 11, a communication module 12, and an interrupt module 13.

In one embodiment, the power module 11 includes a first diode D2, a first resistor R4, a first capacitor C3, and a second capacitor C4. The first capacitor C3 is a super capacitor and has polarity. The power supply module is used for providing power for the clock chip U1.

In an embodiment, the anode of the first diode D2 is electrically connected to the first power supply vcc_5v, and the first power supply may be 5V. The cathode of the first diode D2 is electrically connected to the first end of the first resistor R4.

In an embodiment, the second end of the first resistor R4 is electrically connected to the positive electrode of the first capacitor C3, and the negative electrode of the first capacitor C3 is grounded.

In an embodiment, a first end of the second capacitor C4 is electrically connected to the cathode of the first diode D2, and a second end of the second capacitor C4 is grounded. The second capacitor C4 may be a non-polar capacitor.

In an embodiment, the clock chip U1 is provided with a chip power terminal, and the chip power terminal is electrically connected to the cathode of the first diode D2.

When the battery management unit works normally, the first power supply VCC_ +5V clamps the power supply of the clock chip U1 at 4.3V through the first diode D2, supplies power to the clock chip U1, and simultaneously charges the super capacitor C3. R4 may be encapsulated with 1206, acting as a current limiter.

In the transportation process, the power management unit is in a power-down state, at this time, the first power supply VCC_ +5V is 0V, and the super capacitor C3 supplies power to the clock chip U1, so that the normal operation of the system time is maintained.

Optionally, the first resistor R4 has a resistance value of 60 Ω and is encapsulated with 1206. The rated voltage of the first capacitor C3 is 5.5V, and the capacitance value is 5.0 Farad (F); the capacitance value of the second capacitor C4 is 0.1uF, and 0603 is adopted for encapsulation; the withstand voltage of the first diode D2 was 100V, and the rated current was 0.3A.

In one embodiment, the capacitance of the first capacitor C3 can be calculated by the following formula (1):

c3 =i×t/(U1 '-U2')=i×t/dU equation (3)

Wherein U1 'is the highest voltage at two ends of the super capacitor, U2' is the lowest working voltage of the clock chip, I is the working current of the clock chip, and t is the duration of the first capacitor providing energy for the clock chip.

In the case of selecting the type of the clock chip U1, the type may be selected according to the following specifications. The working current of the clock chip U1 is 0.25uA, the maximum working current is 0.55uA, the highest working voltage of the clock chip U1 is 5.5V, and the lowest working voltage is 0.9V. In order to select a super capacitor with small capacity as much as possible, the utility model designs the clock chip U1 to be powered by a 5V power supply. Considering that charging the super capacitor may damage the voltage drop of the anti-reflection diode D2.7V, the highest voltage actually loaded to both ends of the super capacitor is 4.3V.

In one embodiment, du=4.3V-0.9 v=3.4V. When the super capacitor is required to provide energy for RTC for at least 6 months, then t=6×30×24×60×60= 15552000s, where: (1) C3=0.25ua x 1555200s/3.4v= 1.144F when i=0.25 uA; (2) C3=0.55ua 1555200s/3.4v=2.516F when i=0.55 uA. According to the calculation result, the comprehensive production process, the size of the circuit board, the size of the capacitor and the size of the battery are combined, and the capacitance value of the first capacitor (i.e. the super capacitor) is between 4.95 farad and 5.05 farad.

Therefore, by combining the characteristic that the transportation time of the energy storage battery system does not exceed 6 months, the utility model estimates the working time of the super capacitor after the system is powered down, then reasonably selects the super capacitor, and matches the hardware circuit design, thereby realizing the high stability and high reliability of the power-down protection of the battery management unit system under the goal of low cost. In other words, the super capacitor with the optimal 5.0F is suitable for relevant size, can provide enough energy storage capacity and reduces the cost of the whole clock circuit.

In an embodiment, the communication module 12 includes a second resistor R5, a third resistor R6, a first transistor Q2, a second transistor Q3, a fourth resistor R7, and a fifth resistor R8. The first transistor Q2 and the second transistor Q3 may be transistors. The communication module 12 is used to enable communication between a processor (MCU) and a clock circuit. The processor may be disposed in the battery management unit, and the processor is electrically connected with the clock circuit.

In an embodiment, the first terminal of the first transistor Q2 is electrically connected to a second power supply vcc_3v3, and the second power supply may be 3.3V. The second end of the first triode Q2 is electrically connected to the processor and is used for receiving a first clock signal CPU_RTC_SCL sent by the processor, the third end of the first triode Q2 is electrically connected to the first end of the second resistor R5, and the second end of the second resistor R5 is electrically connected to the first power supply.

In one embodiment, the first terminal of the second transistor Q3 is electrically connected to the second power supply vcc_3v3. The second end of the second triode Q3 is electrically connected to the processor and is used for receiving a second clock signal CPU_RTC_SDA sent by the processor, the third end of the second triode Q3 is electrically connected to the first end of the third resistor R6, and the second end of the third resistor R6 is electrically connected to the first power supply.

In an embodiment, a first end of the fourth resistor R7 is electrically connected to the second power supply, and a second end of the fourth resistor R7 is electrically connected to the second end of the second transistor Q3; the first end of the fifth resistor R8 is electrically connected to the second power supply, and the second end of the fifth resistor R8 is electrically connected to the second end of the second triode Q3.

In one embodiment, the communication terminals include a first communication terminal and a second communication terminal. Specifically, the clock chip U1 is provided with a first communication end SCL and a second communication end SDA, where the first communication end SCL is electrically connected to the third end of the first triode Q2, and the second communication end SDA is electrically connected to the third end of the second triode Q3.

The communication between the processor and the clock chip U1 is realized through the I2C circuit, and the voltage matching is carried out through the second resistor R5, the third resistor R6, the fourth resistor R7 and the fifth resistor R8, so that the reliability of time keeping of the clock chip U1 can be improved, and meanwhile, the communication quality between the processor and the clock chip U1 is improved.

In an embodiment, the interrupt module 13 includes a sixth resistor R1, a seventh resistor R2, an eighth resistor R3, a third transistor Q1, and a second diode D1. The third transistor Q1 may be a bipolar transistor. The interrupt module 13 is configured to wake up the MCU under control of the interrupt signal line cpu_rtc_sig.

In an embodiment, the clock chip U1 is provided with an interrupt terminal INT, a first terminal of the seventh resistor R2 is electrically connected to the interrupt terminal INT, and a second terminal of the seventh resistor R2 is electrically connected to the first terminal of the third triode Q1.

In an embodiment, a first end of the sixth resistor R1 is electrically connected to the second end of the third transistor Q1, and a second end of the sixth resistor R1 is electrically connected to the first end of the third transistor Q1. The second end of the third triode Q1 is electrically connected to the negative electrode of the first diode D2.

In an embodiment, a first end of the eighth resistor R3 is electrically connected to the third end of the third triode Q1, a second end of the eighth resistor R3 is electrically connected to the positive electrode of the second diode D1, the positive electrode of the second diode D1 is electrically connected to the interrupt signal line cpu_rtc_sig, and the negative electrode of the second diode D1 is electrically connected to the second power supply.

When the clock chip U1 needs to be awakened, a CPU_RTC_SIG signal can be sent to the clock chip U1 through the processor, so that the clock chip U1 is awakened. In practical application, the interrupt signal can be turned on at regular time, and the clock chip U1 is awakened in a fixed time period.

In an embodiment, the clock circuit further comprises an oscillation module 14, the oscillation module 14 being configured to generate a clock signal of the RTC. The oscillation module 14 includes a crystal oscillator XL1, a third capacitor C1, and a fourth capacitor C2. The clock chip U1 is provided with a first oscillation end OSCI and a second oscillation end OSCO, and two ends of the crystal oscillator XL1 are respectively and electrically connected to the first oscillation end OSCI and the second oscillation end OSCO. The first end of the third capacitor C1 is electrically connected to the first oscillating end OSCI, and the second end of the third capacitor C1 is grounded; the first end of the fourth capacitor C2 is electrically connected to the second oscillating end OSCO, and the second end of the fourth capacitor C2 is grounded.

In an embodiment, the clock chip U1 is further provided with a ground terminal VSS, and the ground terminal VSS may be directly grounded. The ground terminal of the clock chip U1 may be grounded together with the power module 11 and the oscillation module 14, so as to reduce signal interference of ground.

In summary, the utility model utilizes the power supply module to provide power for the clock chip, can flexibly select the super capacitor with small capacity according to the transportation time length, so that the layout is more convenient when the circuit board is designed, and meanwhile, the clock circuit can flexibly wake up the clock chip by arranging the communication module and the terminal module, thereby reducing the power consumption, improving the working reliability due to the simple circuit structure, and further solving the problem of self-holding of the system time after the battery management unit is powered down in the transportation process of the battery system.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.

The clock circuit and the battery pack provided by the embodiment of the utility model are described in detail, and specific examples are applied to the principle and the implementation of the utility model, and the description of the above embodiment is only used for helping to understand the technical scheme and the core idea of the utility model; those of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the utility model.

Claims

1. A clock circuit for use in a battery management unit having a processor, the clock circuit comprising:

the clock chip is provided with a chip power supply end, a communication end and an interrupt end;

the power module is electrically connected to the power end of the chip and is used for providing power for the clock chip;

the communication module is electrically connected with the processor and the communication end and is used for communication between the processor and the clock chip;

and the interrupt module is electrically connected with the interrupt end and is used for waking up the clock chip at regular time.

2. The clock circuit of claim 1, wherein the power module comprises:

the anode of the first diode is electrically connected with a first power supply, and the cathode of the first diode is electrically connected with the power supply end of the chip;

a first resistor, wherein a first end of the first resistor is electrically connected to the negative electrode of the first diode;

the positive electrode of the first capacitor is electrically connected to the second end of the first resistor, and the negative electrode of the first capacitor is grounded;

and the first end of the second capacitor is electrically connected with the cathode of the first diode, and the second end of the second capacitor is grounded.

3. The clock circuit of claim 2, wherein the first capacitor is a super capacitor, and wherein the capacitance of the first capacitor is between 4.95 farad and 5.05 farad.

4. The clock circuit of claim 2, wherein the communication module comprises:

the second end of the second resistor is electrically connected with the first power supply;

the second end of the third resistor is electrically connected with the first power supply;

the first end of the first triode is electrically connected with the second power supply, the second end of the first triode is electrically connected with the processor and is used for receiving a first clock signal sent by the processor, and the third end of the first triode is electrically connected with the first end of the second resistor;

the first end of the second triode is electrically connected with a second power supply, the second end of the second triode is electrically connected with the processor and is used for receiving a second clock signal sent by the processor, and the third end of the second triode is electrically connected with the first end of the third resistor;

the first end of the fourth resistor is electrically connected with the second power supply, and the second end of the fourth resistor is electrically connected with the second end of the second triode;

and the first end of the fifth resistor is electrically connected with the second power supply, and the second end of the fifth resistor is electrically connected with the second end of the second triode.

5. The clock circuit of claim 4, wherein the communication terminals comprise a first communication terminal and a second communication terminal, the first communication terminal being electrically connected to the third terminal of the first transistor, the second communication terminal being electrically connected to the third terminal of the second transistor.

6. The clock circuit of claim 5, wherein the interrupt module comprises:

the second end of the third triode is electrically connected with the negative electrode of the first diode;

the anode of the second diode is electrically connected with the interrupt signal line, and the cathode of the second diode is electrically connected with the second power supply;

a sixth resistor, wherein a first end of the sixth resistor is electrically connected to the second end of the third triode, and a second end of the sixth resistor is electrically connected to the first end of the third triode;

a seventh resistor, wherein a first end of the seventh resistor is electrically connected to the interrupt end, and a second end of the seventh resistor is electrically connected to the first end of the third triode;

and the first end of the eighth resistor is electrically connected with the third end of the third triode, and the second end of the eighth resistor is electrically connected with the anode of the second diode.

7. The clock circuit of any one of claims 1-6, further comprising an oscillation module for generating a clock signal of the clock circuit, the clock chip having a first oscillation terminal and a second oscillation terminal, the oscillation module comprising:

the two ends of the crystal oscillator are respectively and electrically connected with the first oscillation end and the second oscillation end;

the first end of the third capacitor is electrically connected to the first oscillating end, and the second end of the third capacitor is grounded;

and the first end of the fourth capacitor is electrically connected with the second oscillating end, and the second end of the fourth capacitor is grounded.

8. The clock circuit of claim 7, wherein a ground terminal is further provided on the clock chip, the ground terminal being common to the power module and the oscillating module.

9. A battery pack comprising a battery management unit and a clock circuit according to any one of claims 1-8.