CN220611404U - Chip test system - Google Patents
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- CN220611404U CN220611404U CN202321513811.2U CN202321513811U CN220611404U CN 220611404 U CN220611404 U CN 220611404U CN 202321513811 U CN202321513811 U CN 202321513811U CN 220611404 U CN220611404 U CN 220611404U
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Abstract
The application discloses a chip test system. The chip testing system comprises a sorting machine, a testing machine and a sorting control device. The sorting machine comprises sorting communication ports, and first storage units which are in one-to-one correspondence with the sorting communication ports and store port identifiers of the corresponding sorting communication ports; the testing machine comprises testing stations which are in one-to-one correspondence with the sorting communication ports; the sorting control device comprises communication modules corresponding to the test stations one by one, each communication module comprises a first communication port, a second storage unit and a control module, in the same communication module, the second storage unit stores the test station identification of the test station corresponding to the communication module, the first communication port is connected with the target sorting communication port, the control module is connected with the second storage unit and the first storage unit of the target sorting communication port, and when the control module reads the matched test station identification and port identification from the connected storage unit, the first communication port is controlled to be communicated with the target sorting communication port. The chip detection accident can be reduced.
Description
Technical Field
The application relates to the technical field of integrated circuit testing, in particular to a chip testing system.
Background
Before the chip leaves the factory, the integrated test circuit system is generally used for testing the chip to judge whether the chip has defects, faults or failures and other problems. Integrated test circuitry typically includes a tester and a sorter. On the sorting machine side, a plurality of test stations for placing chips to be tested, and a communication port corresponding to each test station, are typically provided. On the tester side, test stations are provided, which are connected one by one with the test stations. The test station is used for testing the chips connected with the test station. Meanwhile, the test stations are connected with the communication ports on the sorting machine in a one-to-one correspondence manner, so that the test stations can communicate with the sorting machine according to the chip test conditions on each test station.
Currently, as the number of test stations increases, so too does the number of communication ports. In the case of a large number of communication ports, the problem of cross-connection of the flat cable between the test station and the sorting machine often occurs, resulting in chip test errors.
Disclosure of Invention
In view of this, the embodiments of the present application provide a chip testing system, which can reduce chip testing accidents.
In one aspect, the present application provides a chip test system, including:
the sorting machine comprises sorting communication ports and first storage units which are in one-to-one correspondence with the sorting communication ports, wherein the first storage units store port identifiers of the corresponding sorting communication ports;
the testing machine comprises testing stations which are in one-to-one correspondence with the sorting communication ports;
the sorting control device comprises communication modules corresponding to the test stations one by one, wherein each communication module comprises a first communication port, a second storage unit and a control module, in the same communication module, the second storage unit stores the test station identification of the test station corresponding to the communication module, the first communication port is connected with the target sorting communication port, the control module is connected with the second storage unit and the first storage unit of the target sorting communication port, and when the control module reads the matched test station identification and port identification from the connected storage unit, the first communication port is controlled to be communicated with the target sorting communication port.
In some embodiments, the sorting control device further comprises a second communication port connected between the testing station and the first communication port of the communication module, the sorter communicating with the testing station through the first communication port and the second communication port.
In some embodiments, each of the first communication ports includes a plurality of sub-communication ports, the second communication port includes a serial peripheral interface, and at least a portion of the sub-communication ports of the first communication port are connected to the serial peripheral interface.
In some embodiments, the sorting control device further comprises a protocol conversion module connected between the sub-communication port and the serial peripheral interface for protocol conversion.
In some embodiments, the first communication port is connected with the sorting communication port through a flat cable, and the serial peripheral interface is connected with the testing station through a serial data cable.
In some embodiments, the communication module comprises a test switch, the test switch is connected with the first communication port in series, the control module is connected with the test switch, and the control module controls communication between the first communication port and the sorting communication port by controlling on-off of the test switch.
In some embodiments, the sorting control device further comprises an alarm device, the control module is connected with the alarm device, and when the control module reads the unmatched test station identifier and port identifier from the connected storage unit, the control module controls the alarm device to work so as to alarm.
In some embodiments, the alarm devices are arranged in one-to-one correspondence with the communication modules, and a control module in each communication module is connected with the corresponding alarm device to control the connected alarm device to work when the control module reads the unmatched test station identifier and port identifier.
In some embodiments, the chip test system includes a first display device, where the first display device is set in one-to-one correspondence with the first storage units, and the first display device displays the port identifiers stored in the corresponding first storage units.
In some embodiments, the first display device is provided to the sorter in a affixed or coupled manner.
In some embodiments, the chip test system includes a second display device, where the second display device is disposed in one-to-one correspondence with the second storage unit, and the second display device displays the test station identifier stored in the corresponding second storage unit.
In some embodiments, the second display device is provided to the sorting control device in a paste or coupling manner.
In the technical solutions of some embodiments of the present application, in a chip test system, a corresponding first storage unit for storing a port identifier is set for each sorting communication port of a sorting machine, a communication module is set for each test station of the testing machine, and a second storage unit for storing the test station identifier and a control module for performing matching judgment are set in the communication module. With such a system configuration, the first communication port communicates with the sorting communication port only when the sorting communication port to which the first communication port is connected is the sorting communication port corresponding to the test station. And when the branch communication port connected with the first communication port is not the branch communication port corresponding to the test station, the first communication port is not communicated with the sorting communication port. Therefore, the chip test accident caused by the connection error between the first communication port and the sorting communication port can be effectively avoided. Therefore, the chip test accident can be effectively reduced.
Drawings
The features and advantages of the present application will be more clearly understood by reference to the accompanying drawings, which are schematic and should not be interpreted as limiting the application in any way, in which:
FIG. 1 shows a schematic diagram of a chip testing apparatus in some techniques;
FIG. 2 is a schematic diagram showing the chip test apparatus of FIG. 1 when a wiring fault occurs;
FIG. 3 shows a block diagram of a chip testing system provided in one embodiment of the present application;
FIG. 4 shows a block diagram of a chip testing system provided in accordance with another embodiment of the present application;
FIG. 5 shows a block diagram of a chip testing system provided in accordance with another embodiment of the present application;
FIG. 6 shows a block diagram of a chip testing system provided in accordance with another embodiment of the present application;
fig. 7 shows a schematic block diagram of a chip testing system according to another embodiment of the present application.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some of the embodiments of the present application, but not all of the embodiments. All other embodiments, based on the embodiments herein, which are within the scope of the protection of the present application, will be within the skill of the art without inventive effort.
Referring to fig. 1, a schematic diagram of a chip testing apparatus 100 in some technologies is shown. In fig. 1, a chip testing apparatus 100 includes a sorter 11, a tester 12, a test strip 13, and a sorting signal strip 14. Wherein the sorter 11 comprises a plurality of test stations 111 and communication ports 112. The test stations 111 have a one-to-one correspondence with communication ports 112. Tester 12 includes a plurality of test stations 121. The test stations 111 and 121 are connected in one-to-one correspondence by the test flat cable 13. The communication ports 112 are connected to the test stations 121 in one-to-one correspondence via the sorting signal flat cables 14. Each test station 111 may be used to place one chip. Taking fig. 1 as an example, a sorter 11 may be used to place 4 chips. Each test station 121 may be used to test a chip on a connected test station 111. The test station 111 and the communication port 112 connected to the same test station 121 need to correspond. For example, assume that test station 1 corresponds to communication port 1. If test station a is connected to test station 1, then test station a needs to be simultaneously connected to communication port 1.
The sorter 11 may also include a robot arm. The robot arm may communicate with the test station 121 through the communication port 112. The robot arm may automatically place the chip into the test station 111 during the chip inspection, and automatically remove the chip from the test station 111 after the chip inspection is completed. For ease of understanding, the following describes the detection process of one chip by way of example.
Assuming that the manipulator has placed a chip in the test station 1, a message may be sent to the test station a via the communication port 1 corresponding to the test station 1. After receiving the message, the test station a may send a test signal to the chip on the test station 1 to perform a chip test. After the chip test is completed, the test station a may generate a test result of the chip. The test result may be used to characterize the class (e.g., good, bad) to which the chip belongs. The test station a may feed back the test results to the manipulator via the communication port 1. Because the communication port 1 corresponds to the test station 1, after the test result is received by the manipulator, the chip on the test station 1 is taken down from the test station 1 and placed into the category to which the chip belongs. For example, if the test station a detects that the chip belongs to the good, the chip is placed in the chip of the good class.
In the chip testing apparatus 100 shown in fig. 1, a line connection error often occurs due to the number of the testing stations 111, the testing stations 121, and the communication ports 112. Referring to fig. 2 in combination, a schematic diagram of the chip testing apparatus 100 in fig. 1 when a wiring error occurs is shown. In fig. 2, it is assumed that the communication port 3 corresponds to the test station 3 and the communication port 4 corresponds to the test station 4, and the test station C connects the communication port 3 and the test station D connects the communication port 4 and the test station 4, under the correct wiring. Taking test station 3 as an example. Normally, after the manipulator places the chip on the test station 3, a message is sent to the test station C via the communication port 3. After receiving the message, the testing station C tests the chip on the testing station 3, and feeds back the test result to the manipulator through the communication port 3, so that the manipulator takes down the chip on the testing station 3.
However, due to the line connection error, the test station C is actually connected to the communication port 4, and the test station D is connected to the communication port 3. After the manipulator places the chip in the test station 3, a message is actually sent to the test station D via the communication port 3. After receiving the message, the testing station D tests the chip on the testing station 4 and feeds back the test result to the manipulator through the communication port 3. Since the manipulator is the test result received from the communication port 3, the chip on the test station 3 will be placed into the chip category characterized by the test result. It can be seen here that the actual test is of the chip on the test station 4, and the result is the chip type to which the chip on the test station 4 belongs. However, due to the wrong connection of the lines, the manipulator may erroneously remove the chip from the test station 3, which may lead to an accident in the chip test. For example, if the chip of the test station 4 is a qualified chip, but the chip of the test station 3 is a failed chip, under the condition of line connection error, the failed chip of the test station 3 is placed into a qualified chip category, so as to cause chip test accidents.
Generally, since the test station 111 and the test station 121 are located in the same plane (e.g., both are located on the upper surface of the device), there is less chance of a line connection error between the test station 111 and the test station 121. The communication port 112 is located on the side of the sorting machine 11 and is not located on the same plane as the test station 121, so that the probability of line connection error between the communication port 112 and the test station 121 is high. For this reason, in solving the problem of the line connection error of the chip test apparatus 100, the problem of the line connection error between the communication port 112 and the test station 121 may be emphasized.
In view of this, please refer to fig. 3, which is a block diagram of a chip testing system 300 according to an embodiment of the present application. In fig. 3, the chip test system 300 includes a handler 33, a tester 32, and a handler control 31.
The sorter 33 includes sorting communication ports 331, and first storage units 332 in one-to-one correspondence with the sorting communication ports 331. The first storage unit 332 stores the port identification of the corresponding split communication port 331. Specifically, the port identifiers of the split communication ports 331 may have uniqueness, that is, the port identifiers of the different split communication ports 331 are different. The first memory unit 332 may be a readable and writable memory unit. In addition to the above modules, the sorting machine 33 may further include a testing station, a manipulator, and the like, which are in one-to-one correspondence with the sorting communication ports 331. The relevant principle is similar to that of fig. 1 and is not repeated here.
The tester 32 includes test stations 321 in one-to-one correspondence with the split communication ports 331. As described in connection with fig. 1, the test station 321 may communicate with the sorter 33 through a corresponding sort communication port 331 during chip testing.
The sorting control device 31 includes communication modules 311 corresponding to the test stations 321 one by one, the communication modules 311 include a first communication port 3113, a second storage unit 3112 and a control module 3111, in the same communication module 311, the second storage unit 3112 stores a test station identifier of the test station 321 corresponding to the communication module 311, the first communication port 3113 is connected to the target sorting communication port 331, the control module 3111 is connected to the second storage unit 3112 and the first storage unit 332 of the target sorting communication port 331, and when the control module 311 reads the matched test station identifier and port identifier from the connected storage units, the control module 311 controls the first communication port 3113 to communicate with the target sorting communication port 331.
Specifically, each of the first communication ports 3113 may be connected to one of the sorting communication ports 331 (i.e., the target sorting communication port), and the sorting communication ports 331 to which different first communication ports 3113 are connected are different. For example, taking fig. 3 as an example, the first communication port a may be connected to the split communication port a, the second communication port B may be connected to the split communication port B, and so on. Each test station 321 may be connected to the sorter 33 through the first communication port 3113 of the corresponding communication module 311, and the sorting communication port 331 to which the first communication port 3113 is connected. It will be appreciated that if the sorting communication port 331 to which the first communication port 3113 is connected is not the sorting communication port 331 corresponding to the test station 321, then the chip test accident described in fig. 2 occurs. In view of this, in the solution of the present application, the control module 3111 in each communication module 311 may first perform matching determination between the test station identifier and the port identifier, and when the test station identifier and the port identifier match, control the first communication port 3113 to communicate with the sorting communication port 331, so that the test station 321 may communicate with the sorting machine 33 through the corresponding first communication port 3113 and the sorting communication port 331 connected to the first communication port 3113.
Here, the test station identifier matches the port identifier, which means that the test station 321 characterized by the test station identifier corresponds to the sorting communication port 331 characterized by the port identifier. If the test station identifier matches the port identifier, it means that the sorting communication port 331 to which the first communication port 3113 is connected is the sorting communication port 331 corresponding to the test station 321, and therefore, the first communication port 3113 and the sorting communication port 331 can be controlled to communicate with each other, and the test station 321 can communicate with the sorter 33 through the corresponding first communication port 3113 and the sorting communication port 331 to which the first communication port 3113 is connected. However, if the test station identifier does not match the port identifier, it means that the sorting communication port 331 connected to the first communication port 3113 is not the sorting communication port 331 corresponding to the test station 321, so that the first communication port 3113 and the sorting communication port 331 may be controlled not to communicate, so as to avoid chip testing accidents caused by communication between the test station 321 and the sorter 33.
In the present embodiment, in the second storage unit 3112 of each communication module 311, the correspondence relationship of the test station identifier and the port identifier may be stored in advance. This correspondence is used to characterize the correspondence between each test station 321 and the sort communication port 331. After the control module 3111 reads the test station identifier and the port identifier from the connected storage units 3112 and 332, it may determine whether the read test station identifier and the read port identifier are matched based on a pre-stored correspondence, and if yes, control the first communication port 3113 to communicate with the sorting communication port 331; if not, the first communication port 3113 and the sorting communication port 331 are controlled to continue to be kept in the disconnected state.
For ease of understanding, fig. 3 is taken as an example. Assuming that the communication module a corresponds to the test station a, a first communication port a in the communication module a is connected to the sorting communication port a, and a control module 3111 in the communication module a is connected to the second storage unit a and the first storage unit a. In the matching judgment, the control module 3111 compares the identifier of the test station in the second storage unit a with the identifier of the port in the first storage unit a, and if the identifier of the test station in the second storage unit a matches with the identifier of the port in the first storage unit a, it indicates that the sorting communication port a to which the first communication port a is connected is a sorting communication port corresponding to the test station a, so that the first communication port a and the sorting communication port a can be controlled to communicate so that the test station a can communicate with the sorting machine 33 through the first communication port a and the sorting communication port a.
With continued reference to fig. 4, a block diagram of a chip test system 400 according to another embodiment of the present application is provided. Fig. 4 is substantially similar to fig. 3, with the main differences: in the communication module A, a first communication port A is connected with a sub-communication port B, and a control module A is connected with a first storage unit B (the connecting line is shown as a solid line); in the communication module B, the first communication port B is connected to the split communication port a, and the control module B is connected to the first storage unit a (the connection line is shown as a dotted line). Taking the control module a as an example, the test station identifier read by the control module a from the second storage unit a is the test station identifier of the test station a, and the port identifier read by the control module a from the first storage unit B is the port identifier of the sorting communication port B, it is obvious that the read test station identifier and the port identifier are not matched, so that the control module a cannot control the first communication port a to be communicated with the sorting communication port B, and further, the chip test fault caused by the communication of the first communication port a and the sorting communication port B is avoided.
To sum up, in the solutions of some embodiments of the present application, in the chip test system 300, a corresponding first storage unit 332 for storing port identifiers is provided for each of the sorting communication ports 331 of the sorting machine 33, and a communication module 311 is provided for each of the test stations 321 of the testing machine 32, and a second storage unit 3112 for storing the test station identifiers and a control module 3111 for performing matching judgment are provided in the communication module 311. With such a system configuration, the first communication port 3113 communicates with the sorting communication port 331 only when the sorting communication port 331 to which the first communication port 3113 is connected is the sorting communication port 331 corresponding to the test station 321. When the sorting communication port 331 connected to the first communication port 3113 is not the sorting communication port 331 corresponding to the test station 321, the first communication port 3113 does not communicate with the sorting communication port 331. Thus, the chip test accident caused by the connection error between the first communication port 3113 and the sorting communication port 331 can be effectively avoided. Therefore, the chip test accident can be effectively reduced.
With continued reference to fig. 3, in some embodiments, the sorting control device 31 further includes a second communication port 313, the second communication port 313 being connected between the test station 321 and the first communication port 3113 of the communication module 311, and the sorter 33 being in communication with the test station 321 through the first communication port 3113 and the second communication port 313. In this way, the connection between the test station 321 and each of the first communication ports 3113 and thus the connection with the handler 33 are realized, so as to communicate with the handler 33 during the chip test.
In this embodiment, the second communication port 313 may include a serial peripheral interface. The serial peripheral interface is connected with the test station 321 through a serial data line. The plurality of first communication ports 3113 are respectively connected to the same second communication port 313 to be connected to the corresponding test station 321 through the same second communication port 313. For example, the first communication port a is connected to the corresponding test station a through the second communication port 313, and the first communication port B is connected to the corresponding test station B through the second communication port 313. The test station 321 and the sorting control device 31 may communicate according to the SPI (Serial Peripheral Interface ) protocol. In other embodiments, the sorting control device 31 includes a plurality of second communication ports 313. The first communication ports 3113 are connected to the second communication ports 313 in one-to-one correspondence.
In some embodiments, each first communication port 3113 includes a plurality of sub-communication ports. These different sub-communication ports are used for transmitting different signals in chip test, for example, sub-communication port a is used for transmitting chip test results, sub-communication port B is used for transmitting signals representing that chip test is started, and sub-communication port C is used for transmitting signals representing that chip test is stopped. In the case where each of the first communication ports 3113 includes a plurality of sub-communication ports, the first communication ports 3113 are connected to the sorting communication port 331 by a flat cable, and at least part of the sub-communication ports of the first communication ports 3113 are connected to the serial peripheral interface (i.e., the second communication port 313). The sorting control device 31 further includes a protocol conversion module 314, and the protocol conversion module 314 is connected between the sub-communication port and the serial peripheral interface for performing protocol conversion. I.e. the message received based on the wire arrangement communication is converted into a message of SPI protocol.
Referring to fig. 5, a schematic block diagram of a chip testing system 500 according to another embodiment of the present application is shown. Fig. 5 is substantially similar to fig. 3, with the main differences: the communication module 511 includes a test switch 5114, the test switch 5114 is connected in series with the first communication port 5113, the control module 5111 is connected with the test switch 5114, and the control module 5111 controls communication between the first communication port 5113 and the sorting communication port 531 by controlling on-off of the test switch 5114. In this way, on-off control between the first communication port 5113 and the sorting communication port 531 is achieved.
Referring to fig. 6, a schematic block diagram of a chip testing system 600 according to another embodiment of the present application is provided. Fig. 6 is substantially similar to fig. 3, with the main differences: the sorting control device 61 further comprises an alarm device 6115, the control module 6111 is connected with the alarm device 6115, and when the control module 6111 reads the unmatched test station identifier and port identifier from the connected storage unit, the control module 6111 controls the alarm device 6115 to work so as to alarm. Specifically, the alarm device 6115 may be a warning lamp, a horn, or the like. In this way, the worker can be timely reminded to process the sorting communication port 631 and the first communication port 6113 in case of wrong connection.
In the embodiment shown in fig. 6, the alarm devices 6115 are arranged in a one-to-one correspondence with the communication modules 611, and the control module 6111 in each communication module 611 is connected with the corresponding alarm device 6115, so as to control the connected alarm device to work when the control module 6111 reads the unmatched test station identifier and port identifier. In other embodiments, the communication modules 611 include module identifications, with the module identifications of different communication modules 611 being different. The plurality of communication modules 611 may correspond to one alarm device 6115. For communication modules 611 for which a mismatch between the test station identification and the port identification is detected, the alerting device 6115 may display the module identifications of these communication modules 611. In this way, the worker can locate the split communication port 631 and the first communication port 6113 in which the connection error occurs based on the displayed module identification. Only one alarm device 6115 is provided, the volume of the sorting control device 61 can be reduced.
Referring to fig. 7, a schematic block diagram of a chip testing system 700 according to another embodiment of the present application is provided. Fig. 7 is substantially similar to fig. 3, with the main differences: the chip test system 700 includes a first display device 733, where the first display device 733 is disposed in one-to-one correspondence with the first storage unit 732, and the first display device 733 displays the port identifier stored in the corresponding first storage unit 732; and the chip testing system 700 includes a second display device 7117, where the second display device 7117 is disposed in a one-to-one correspondence with the second storage unit 7112, and the second display device 7117 displays the test station identifier stored in the corresponding second storage unit 7112. In this way, during the process of connecting the lines, the staff can determine the correspondence between the split communication ports 731 and the first communication ports 7113 through the display contents of the first display device 733 and the second display device 7117, so as to reduce the probability of connecting the lines.
In some embodiments, the first display device 733 is disposed to the sorter 73 in a affixed or coupled manner. The second display device 7117 is provided to the sorting control device 71 in a sticking or coupling manner.
In summary, in the chip test system of the present application, the port identifier of each sub-communication port is stored by setting the first storage unit on the sorter side, and the test station identifier of the test station is stored by setting the second storage unit on the sorting control device side, so that the sub-communication port and the first communication port can be disconnected under the condition that the port identifier and the test station identifier are not matched, thereby reducing the chip test accident.
In addition, in the application, the communication module, the protocol conversion module and the like are arranged on the sorting control device, so that the change of the tester side can be reduced, and the adaptability is better. For example, if the communication module is set in the testing machine, the corresponding communication module is required to be set in the testing machine for each testing station, which necessarily requires a large modification to the testing machine based on the existing testing machine, and reduces the compatibility of the testing machine. Therefore, by arranging the sorting control device, the compatibility of the testing machine can be greatly improved.
Although embodiments of the present application have been described in connection with the accompanying drawings, various modifications and variations may be made by those skilled in the art without departing from the spirit and scope of the application, and such modifications and variations are within the scope defined by the appended claims.
Claims (12)
1. A chip testing system, the chip testing system comprising:
the sorting machine comprises sorting communication ports and first storage units which are in one-to-one correspondence with the sorting communication ports, wherein the first storage units store port identifiers of the corresponding sorting communication ports;
the testing machine comprises testing stations which are in one-to-one correspondence with the sorting communication ports;
the sorting control device comprises communication modules corresponding to the test stations one by one, wherein each communication module comprises a first communication port, a second storage unit and a control module, in the same communication module, the second storage unit stores the test station identification of the test station corresponding to the communication module, the first communication port is connected with the target sorting communication port, the control module is connected with the second storage unit and the first storage unit of the target sorting communication port, and when the control module reads the matched test station identification and port identification from the connected storage unit, the first communication port is controlled to be communicated with the target sorting communication port.
2. The system of claim 1, wherein the sorting control device further comprises a second communication port connected between the test station and the first communication port of the communication module, the sorter communicating with the test station through the first communication port and the second communication port.
3. The system of claim 2, wherein each of the first communication ports comprises a plurality of sub-communication ports, the second communication port comprises a serial peripheral interface, and at least a portion of the sub-communication ports of the first communication port are coupled to the serial peripheral interface.
4. The system of claim 3, wherein the sorting control device further comprises a protocol conversion module coupled between the sub-communication port and the serial peripheral interface for protocol conversion.
5. The system of claim 3, wherein the first communication port is connected to the sorting communication port by a flat cable, and the serial peripheral interface is connected to the test station by a serial data line.
6. The system of claim 1, wherein the communication module comprises a test switch in series with the first communication port, and wherein the control module is coupled to the test switch, and wherein the control module controls communication between the first communication port and the sorting communication port by controlling the on-off of the test switch.
7. The system of claim 1, wherein the sorting control device further comprises an alarm device, wherein the control module is coupled to the alarm device, and wherein the control module controls the alarm device to operate when the control module reads the unmatched test station identification and port identification from the coupled storage unit to alarm.
8. The system of claim 7, wherein the alarm devices are arranged in a one-to-one correspondence with the communication modules, and a control module in each communication module is connected with a corresponding alarm device to control the connected alarm device to operate when the control module reads the unmatched test station identifier and port identifier.
9. The system of claim 1, wherein the chip test system includes a first display device, the first display device being disposed in one-to-one correspondence with the first storage unit, the first display device displaying the port identification stored by the corresponding first storage unit.
10. The system of claim 9, wherein the first display device is affixed or coupled to the sorter.
11. The system of claim 1, wherein the chip test system includes a second display device, the second display device being disposed in one-to-one correspondence with the second storage unit, the second display device displaying the test station identification stored by the corresponding second storage unit.
12. The system of claim 11, wherein the second display device is attached or coupled to the sorting control device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321513811.2U CN220611404U (en) | 2023-06-13 | 2023-06-13 | Chip test system |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321513811.2U CN220611404U (en) | 2023-06-13 | 2023-06-13 | Chip test system |
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| CN220611404U true CN220611404U (en) | 2024-03-19 |
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| CN202321513811.2U Active CN220611404U (en) | 2023-06-13 | 2023-06-13 | Chip test system |
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