CN112180240A - Test system for chip production - Google Patents
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- CN112180240A CN112180240A CN202011091417.5A CN202011091417A CN112180240A CN 112180240 A CN112180240 A CN 112180240A CN 202011091417 A CN202011091417 A CN 202011091417A CN 112180240 A CN112180240 A CN 112180240A
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- 238000012360 testing method Methods 0.000 title claims abstract description 204
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 230000005284 excitation Effects 0.000 claims description 10
- 238000013500 data storage Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 4
- 230000007547 defect Effects 0.000 abstract description 3
- 230000002950 deficient Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007726 management method Methods 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R35/00—Testing or calibrating of apparatus covered by the other groups of this subclass
Abstract
The invention relates to a test system, in particular to a test system for chip production, which comprises a controller, a chip classification test mechanism, a chip to be tested and identity marks arranged on the chip classification test mechanism and the chip to be tested, wherein the controller is connected with a chip picking mechanism used for putting the chip to be tested into the chip classification test mechanism or picking the chip to be tested from the chip classification test mechanism; the technical scheme provided by the invention can effectively overcome the defects that the working state of the testing device cannot be ensured, the testing process of the chip to be tested cannot be effectively monitored, and whether the chip to be tested is matched with the testing device or not in the prior art.
Description
Technical Field
The invention relates to a test system, in particular to a test system for chip production.
Background
At present, the domestic chip testing equipment market is still dominated by overseas manufacturers, and the domestic market of the foreign famous enterprises always takes a leading position by virtue of powerful technologies and brand advantages. In the face of large market demand and relatively low production cost in China, foreign enterprises dominate most domestic markets by investing in China to establish independent enterprises and joint-fund factories. According to the statistics of the society of semiconductor industry of China, Tairadyne (Teradyne), Edwardten (Advantest) of Japan, Agilent (Agilent) of America, Kelidon (Xcerra) of America and Kehuo (Cohu) of America occupy more than about 80% of the domestic market share in the industry of chip testing equipment.
After the chip is packaged, it is tested to separate good products from bad products. The existing chip testing method generally adopts a manual testing mode, 2-3 test benches are placed in front of each tester, and the information of indicator lamps of the test benches (for example, green indicator lamps represent good products, and red indicator lamps represent defective products) is checked manually to test, so that whether the tested chip is good products or not is judged.
However, when a defective product occurs, it is unclear whether the defective product occurs due to the quality problem of the chip itself or due to the failure of the testing device, and when the testing processes are many, the testing process cannot be effectively monitored, so that the repeated testing of the same process is easily performed, and the testing efficiency is very low. In addition, whether the chip to be tested is matched with the testing device cannot be determined by adopting the testing mode, namely, a situation that a defective product is caused due to confusion of chip testing items may occur.
Disclosure of Invention
Technical problem to be solved
Aiming at the defects in the prior art, the invention provides a test system for chip production, which can effectively overcome the defects in the prior art that the working state of a test device cannot be ensured, the test flow of a chip to be tested cannot be effectively monitored, and whether the chip to be tested is matched with the test device cannot be determined.
(II) technical scheme
In order to achieve the purpose, the invention is realized by the following technical scheme:
a test system for chip production comprises a controller, a chip classification test mechanism, a chip to be tested and an identity mark arranged on the chip classification test mechanism and the chip to be tested, wherein the controller is connected with a chip pickup mechanism for placing the chip to be tested into the chip classification test mechanism or picking up the chip to be tested from the chip classification test mechanism;
the controller is connected with a data storage module used for storing the identification result of the identification module, the controller is connected with a test flow generation module used for generating a test flow chart of the chip to be tested according to the identification result, and the controller uploads the identification result and the test flow chart to an upper computer;
the chip classification testing mechanism comprises a signal receiving module, a testing control module, a fixed testing module and a matching judgment module, wherein the signal receiving module is used for receiving a testing excitation signal sent by the controller, the testing control module is used for generating a testing operation signal according to the testing excitation signal, the fixed testing module is used for generating a channel signal according to the testing operation signal to test a chip to be tested and receiving a feedback signal, and the matching judgment module is used for judging whether the chip to be tested is matched with the chip classification testing mechanism or not according to the feedback signal.
Preferably, when the chip picking mechanism puts the chip to be tested into the chip classification testing mechanism, the controller adjusts the identification angle of the identification module through the identification angle adjusting mechanism, and the identification module identifies the chip classification testing mechanism and the identity identification on the chip to be tested.
Preferably, the identity of the chip classification testing mechanism includes a serial number of a testing machine, and the identity of the chip to be tested includes a serial number of the chip.
Preferably, the identifier recognition module recognizes the identity identifier of the chip classification testing mechanism once, and + 1% of the number of times of use corresponding to the chip classification testing mechanism, and sends the calculated number of times of use and the serial number of the testing machine to the controller.
Preferably, the controller is connected with an alarm module, and when the controller judges that the number of times of use reaches a threshold value, the controller starts the alarm module and uploads the number of times of use and the serial number of the testing machine to an upper computer.
Preferably, the test flow generation module generates a test flow chart of the chip to be tested according to the identification result, and takes the time of the chip to be tested for completing the last test as the file name of the test flow chart of the chip to be tested.
Preferably, the controller is connected with a display module for displaying a test flow chart of the chip to be tested.
Preferably, the test control module determines the test type after receiving the test excitation signal, converts the channel signal corresponding to the channel interface into a test operation signal according to the test type, and sends the test operation signal to the fixed test module.
Preferably, the fixed test module is used for fixing a chip to be tested and is provided with channel interfaces electrically connected with pins of the chip to be tested one by one, and after the fixed test module receives the test operation signal, the fixed test module generates a channel signal in the channel interfaces to test the chip to be tested and receive the feedback signal.
Preferably, after receiving the feedback signals, the matching judgment module judges whether all the feedback signals are greater than a threshold value, and sends a judgment result to the controller;
if all the feedback signals are greater than the threshold value, the matching judgment module judges that the chip to be tested is matched with the chip classification testing mechanism; otherwise, the matching judgment module judges that the chip to be tested is not matched with the chip classification testing mechanism.
(III) advantageous effects
Compared with the prior art, the test system for chip production provided by the invention can confirm the working state of the test device in time, prevent the situation that the test fails due to the fact that the test device cannot work normally, can generate the test flow chart of the chip to be tested, effectively supervise the test flow of the chip to be tested, and can autonomously judge whether the chip to be tested is matched with the chip to be tested, thereby preventing the situation that the test fails due to the fact that the test items of the chip are mixed up.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
FIG. 1 is a schematic diagram of the system of the present invention;
FIG. 2 is a schematic diagram of the chip sorting and testing mechanism of FIG. 1 according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
A test system for chip production is disclosed, as shown in fig. 1 and fig. 2, comprising a controller, a chip classification test mechanism, a chip to be tested, and an identity mark on the chip to be tested, wherein the controller is connected with a chip pick-up mechanism for putting the chip to be tested into the chip classification test mechanism or picking up the chip to be tested from the chip classification test mechanism, the controller is connected with an identification module for identifying the identity mark, and the identification module is installed on the chip pick-up mechanism through an identification angle adjusting mechanism.
When the chip picking mechanism puts the chip to be tested into the chip classification testing mechanism, the controller adjusts the identification angle of the identification module through the identification angle adjusting mechanism, and the identification module identifies the chip classification testing mechanism and the identity identification on the chip to be tested. The identity of the chip classification testing mechanism comprises a serial number of a testing machine, and the identity of the chip to be tested comprises a serial number of the chip.
The identification module identifies the identity identification of the chip classification testing mechanism once, and the use times corresponding to the chip classification testing mechanism is plus 1, and the calculated use times and the serial number of the testing machine are sent to the controller.
The controller is connected with the alarm module, and when the controller judges that the use times reach the threshold value, the controller starts the alarm module and uploads the use times and the serial number of the testing machine to the upper computer. Meanwhile, the controller controls the chip classification testing mechanism to stop working.
And after receiving the serial number of the testing machine sent by the controller, the upper computer timely informs a manager to detect and adjust the chip classification testing mechanism and timely confirms the working state of the testing device.
When the chip classification testing mechanism detects a defective product, the controller controls the chip picking mechanism to place the chip to be tested into the chip classification testing mechanism for the second time for testing again, and the test does not count the use times. If the second test still shows that the chip to be tested is a defective product, the controller controls the chip picking mechanism to place the chip to be tested into a defective product area.
The controller is connected with a data storage module used for storing the identification result of the identification module, the controller is connected with a test flow generation module used for generating a test flow chart of the chip to be tested according to the identification result, and the controller uploads the identification result and the test flow chart to the upper computer.
The test flow generation module generates a test flow chart of the chip to be tested according to the identification result, the time of the chip to be tested for completing the last test is used as the file name of the test flow chart of the chip to be tested, file management is facilitated, and meanwhile the controller displays the test flow chart of the chip to be tested through the display module.
The chip classification testing mechanism comprises a signal receiving module, a testing control module, a fixed testing module and a matching judgment module, wherein the signal receiving module is used for receiving a testing excitation signal sent by the controller, the testing control module is used for generating a testing operation signal according to the testing excitation signal, the fixed testing module is used for generating a channel signal according to the testing operation signal to test a chip to be tested and receiving a feedback signal, and the matching judgment module is used for judging whether the chip to be tested is matched with the chip classification testing mechanism or not according to the feedback signal.
The test control module judges the test type after receiving the test excitation signal, converts the channel signal corresponding to the channel interface into a test operation signal according to the test type and sends the test operation signal to the fixed test module.
The fixed test module is used for fixing a chip to be tested and is provided with channel interfaces which are electrically connected with pins of the chip to be tested one by one, and after the fixed test module receives a test operation signal, a channel signal is generated in the channel interfaces to test the chip to be tested and receive a feedback signal.
After receiving the feedback signals, the matching judgment module judges whether all the feedback signals are greater than a threshold value and sends the judgment result to the controller;
if all the feedback signals are greater than the threshold value, the matching judgment module judges that the chip to be tested is matched with the chip classification testing mechanism; otherwise, the matching judgment module judges that the chip to be tested is not matched with the chip classification testing mechanism.
For example, when two chips to be tested with the same shape, the same number of pins, and different pin distribution positions are required to be tested in different test items, the chip to be tested is placed in the fixed test module through the chip pick-up mechanism, and the chip pins are electrically connected with the channel interfaces one by one.
The test control module judges the test type after receiving the test excitation signal and sends the test operation signal to the fixed test module, and the fixed test module generates a channel signal in the channel interface to test the chip to be tested after receiving the test operation signal. When the chip to be tested is matched with the chip classification testing mechanism, all chip pins are connected, the feedback voltage is a normal value, namely all feedback signals are all larger than a threshold value; when the chip to be tested is not matched with the chip classification testing mechanism, the pins of some chips are not connected, so that part of feedback voltage is zero.
The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the corresponding technical solutions.
Claims (10)
1. A test system for chip production, characterized by: the controller is connected with a chip picking mechanism used for putting the chip to be tested into the chip classification testing mechanism or picking the chip to be tested from the chip classification testing mechanism, the controller is connected with an identification module used for identifying the identification, and the identification module is installed on the chip picking mechanism through an identification angle adjusting mechanism;
the controller is connected with a data storage module used for storing the identification result of the identification module, the controller is connected with a test flow generation module used for generating a test flow chart of the chip to be tested according to the identification result, and the controller uploads the identification result and the test flow chart to an upper computer;
the chip classification testing mechanism comprises a signal receiving module, a testing control module, a fixed testing module and a matching judgment module, wherein the signal receiving module is used for receiving a testing excitation signal sent by the controller, the testing control module is used for generating a testing operation signal according to the testing excitation signal, the fixed testing module is used for generating a channel signal according to the testing operation signal to test a chip to be tested and receiving a feedback signal, and the matching judgment module is used for judging whether the chip to be tested is matched with the chip classification testing mechanism or not according to the feedback signal.
2. The test system for chip production according to claim 1, wherein: when the chip picking mechanism puts the chip to be tested into the chip classification testing mechanism, the controller adjusts the identification angle of the identification module through the identification angle adjusting mechanism, and the identification module identifies the chip classification testing mechanism and the identity mark on the chip to be tested.
3. The test system for chip production according to claim 2, wherein: the identity of the chip classification testing mechanism comprises a serial number of a testing machine, and the identity of the chip to be tested comprises a serial number of the chip.
4. The test system for chip production according to claim 3, wherein: the identification recognition module recognizes the identity identification of the chip classification testing mechanism once, and the use times corresponding to the chip classification testing mechanism is plus 1, and the calculated use times and the serial number of the testing machine are sent to the controller.
5. The test system for chip production according to claim 4, wherein: the controller is connected with the alarm module, and when the controller judges that the use times reach a threshold value, the controller starts the alarm module and uploads the use times and the serial number of the testing machine to the upper computer.
6. The test system for chip production according to claim 1, wherein: and the test flow generation module generates a test flow chart of the chip to be tested according to the identification result, and takes the time of the chip to be tested for completing the last test as the file name of the test flow chart of the chip to be tested.
7. The test system for chip production of claim 6, wherein: the controller is connected with a display module used for displaying a test flow chart of the chip to be tested.
8. The test system for chip production according to claim 1, wherein: and the test control module judges the test type after receiving the test excitation signal, converts the channel signal corresponding to the channel interface into a test operation signal according to the test type and sends the test operation signal to the fixed test module.
9. The test system for chip production of claim 8, wherein: the fixed test module is used for fixing a chip to be tested and is provided with channel interfaces which are electrically connected with pins of the chip to be tested one by one, and after the fixed test module receives a test operation signal, a channel signal is generated in the channel interfaces to test the chip to be tested and receive a feedback signal.
10. The test system for chip production of claim 9, wherein: after receiving the feedback signals, the matching judgment module judges whether all the feedback signals are greater than a threshold value and sends a judgment result to the controller;
if all the feedback signals are greater than the threshold value, the matching judgment module judges that the chip to be tested is matched with the chip classification testing mechanism; otherwise, the matching judgment module judges that the chip to be tested is not matched with the chip classification testing mechanism.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011091417.5A CN112180240A (en) | 2020-10-13 | 2020-10-13 | Test system for chip production |
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| CN202011091417.5A CN112180240A (en) | 2020-10-13 | 2020-10-13 | Test system for chip production |
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| CN112180240A true CN112180240A (en) | 2021-01-05 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114247664A (en) * | 2021-12-27 | 2022-03-29 | 厦门科塔电子有限公司 | Chip FT test system and method integrating sorting and testing |
| CN117110846A (en) * | 2023-10-23 | 2023-11-24 | 紫光同芯微电子有限公司 | Automatic detection method and related device for chip anti-breaking function |
| CN117472816A (en) * | 2023-12-28 | 2024-01-30 | 联和存储科技(江苏)有限公司 | Configuration method of chip pins |
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| CN105717439A (en) * | 2016-02-24 | 2016-06-29 | 上海东软载波微电子有限公司 | Chip test method and system |
| CN108828275A (en) * | 2018-06-28 | 2018-11-16 | 苏州通富超威半导体有限公司 | Chip test system |
| CN110045268A (en) * | 2019-05-07 | 2019-07-23 | 广东工业大学 | A kind of chip detecting system |
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2020
- 2020-10-13 CN CN202011091417.5A patent/CN112180240A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105717439A (en) * | 2016-02-24 | 2016-06-29 | 上海东软载波微电子有限公司 | Chip test method and system |
| CN108828275A (en) * | 2018-06-28 | 2018-11-16 | 苏州通富超威半导体有限公司 | Chip test system |
| CN110045268A (en) * | 2019-05-07 | 2019-07-23 | 广东工业大学 | A kind of chip detecting system |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114247664A (en) * | 2021-12-27 | 2022-03-29 | 厦门科塔电子有限公司 | Chip FT test system and method integrating sorting and testing |
| CN117110846A (en) * | 2023-10-23 | 2023-11-24 | 紫光同芯微电子有限公司 | Automatic detection method and related device for chip anti-breaking function |
| CN117110846B (en) * | 2023-10-23 | 2024-03-01 | 紫光同芯微电子有限公司 | Automatic detection method and related device for chip anti-breaking function |
| CN117472816A (en) * | 2023-12-28 | 2024-01-30 | 联和存储科技(江苏)有限公司 | Configuration method of chip pins |
| CN117472816B (en) * | 2023-12-28 | 2024-04-02 | 联和存储科技(江苏)有限公司 | Configuration method of chip pins |
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