CN220583602U - Balanced photoelectric detector capable of precisely zeroing - Google Patents
Balanced photoelectric detector capable of precisely zeroing Download PDFInfo
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- CN220583602U CN220583602U CN202322186293.4U CN202322186293U CN220583602U CN 220583602 U CN220583602 U CN 220583602U CN 202322186293 U CN202322186293 U CN 202322186293U CN 220583602 U CN220583602 U CN 220583602U
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Abstract
The utility model relates to a balanced photoelectric detector capable of precisely zeroing, which comprises a voltage stabilizing circuit, a photoelectric conversion circuit, an I-V conversion circuit and a secondary amplifying circuit, wherein the voltage stabilizing circuit is connected with the photoelectric conversion circuit; the photoelectric conversion circuit is connected with the I-V conversion circuit; the I-V conversion circuit is connected with the secondary amplifying circuit; the I-V conversion circuit comprises a transimpedance amplifying circuit and a precise zeroing circuit; the transimpedance amplifying circuit is used for converting a current signal output by the photoelectric conversion circuit into a voltage signal; the precise zeroing circuit comprises a voltage reference circuit and a fine-tuning circuit; the voltage reference circuit is connected with the fine-tuning circuit; the fine-tuning circuit is connected with the transimpedance amplifying circuit. In the utility model, the precise zero-setting circuit selects a precise low-temperature drift voltage reference chip, and the function of counteracting direct-current voltage generated by inconsistent photodiode parameters and unbalance of an actual operational amplifier is realized by finely adjusting the resistance value of the resistor, so that quantum state quantum noise in continuous variable quantum information scientific research can be effectively measured.
Description
Technical Field
The utility model belongs to the technical field of photoelectric detection, and particularly relates to a balanced photoelectric detector capable of precisely zeroing.
Background
The continuous variable compression state light field can break through quantum noise limit in specific components, and becomes an indispensable quantum resource in the development of quantum information science. The balanced photoelectric detector is widely applied to quantum optical experiments and can realize effective detection of a compressed state of an optical field.
In the traditional balanced photoelectric detector, due to the fact that parameters of two photodiodes are not completely consistent and offset voltage and bias current of an actual operational amplifier device are influenced, direct-current components exist in the obtained quantum signals, and measurement of a compression state in a quantum optical experiment is not facilitated. In the prior art, a capacitor blocking mode is adopted to eliminate direct current components, but the mode can lead the input impedance to change along with the frequency, reduce the amplification factor of a low frequency band, and have weak capability of transmitting low frequency signals, so that the frequency characteristic of the amplifier is poor.
In addition, the circuit of the traditional detector adopts the compensation resistor with the same resistance value connected in series with the same phase end of the operational amplifier so as to reduce the offset effect caused by the input current of the operational amplifier, but the offset effect caused by the input current of the operational amplifier cannot be completely offset by the resistance matching method due to the existence of the input offset current.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present utility model is to provide a balanced photodetector capable of precisely zeroing, which is used for solving the problems of inaccurate zeroing, poor stability and low reliability of the photodetector in the prior art.
The technical scheme adopted by the utility model is that the balanced photoelectric detector capable of precisely zeroing comprises a voltage stabilizing circuit, a photoelectric conversion circuit, an I-V conversion circuit and a secondary amplifying circuit;
the photoelectric conversion circuit is connected with the I-V conversion circuit; the I-V conversion circuit is connected with the secondary amplifying circuit; the voltage stabilizing circuit is used for converting and stabilizing the power supply voltage; the voltage stabilizing circuit is respectively connected with the photoelectric conversion circuit, the I-V conversion circuit and the secondary amplifying circuit;
the I-V conversion circuit comprises a transimpedance amplifying circuit and a precise zeroing circuit;
the transimpedance amplifying circuit is used for converting a current signal output by the photoelectric conversion circuit into a voltage signal;
the precise zeroing circuit comprises a voltage reference circuit and a fine-tuning circuit;
the voltage reference circuit is connected with the fine-tuning circuit; the fine-tuning circuit is connected with the transimpedance amplifying circuit.
Preferably, the voltage reference circuit includes a fifth operational amplifier U5, a sixth operational amplifier, a first voltage reference chip L1, a second voltage reference chip L2, an eighth resistor R8, and a ninth resistor R9;
one end of the ninth resistor R9 is connected with positive power supply voltage, and the other end of the ninth resistor R9 is connected with the first voltage reference chip L1 and the non-inverting input end of the fifth operational amplifier U5; the other end of the first voltage reference chip L1 is grounded; the inverting input end of the fifth operational amplifier U5 is connected with the output end;
one end of the eighth resistor R8 is connected with a negative power supply voltage, and the other end of the eighth resistor R8 is connected with the second voltage reference chip L2 and the non-inverting input end of the sixth operational amplifier U6; the other end of the second voltage reference chip L2 is grounded; the inverting input end of the sixth operational amplifier U6 is connected with the output end.
Preferably, the trimmable circuit includes a second resistor R2, a fourth resistor R4 and a third resistor R3 connected in sequence; one end of the second resistor R2 is connected with the output end of the fifth operational amplifier U5; one end of the third resistor R3 is connected with the output end of the sixth operational amplifier U6; the fourth resistor R4 is a trimming potentiometer; and the adjusting end of the fourth resistor R4 is connected with the transimpedance amplifying circuit.
Preferably, the transimpedance amplifying circuit comprises a first operational amplifier U1 and a first resistor R1; two ends of the first resistor R1 are respectively connected with an inverting input end and an output end of the first operational amplifier U1; the non-inverting input end of the first operational amplifier U1 is connected with the adjusting end of the fourth resistor R4; the inverting input end of the first operational amplifier U1 is connected with the output end of the photoelectric conversion circuit 2; the output end of the first operational amplifier U1 is connected with the secondary amplifying circuit.
Preferably, the photoelectric conversion circuit includes a first photodiode D1 and a second photodiode D2 arranged in series; the anode of the first photodiode D1 and the cathode of the second photodiode D2 are connected with the input end of the I-V conversion circuit.
Preferably, the second-stage amplifying circuit includes a second operational amplifier U2, a fifth resistor R5, a sixth resistor R6, and a seventh resistor R7;
one end of the fifth resistor R5 is connected with the output end of the I-V conversion circuit, and the other end of the fifth resistor R5 is connected with the non-inverting input end of the second operational amplifier U2; one end of the sixth resistor R6 is grounded, and the other end of the sixth resistor R6 is connected with the inverting input end of the second operational amplifier U2; two ends of the seventh resistor R7 are respectively connected with an inverting input end and an output end of the second operational amplifier U2.
Preferably, the voltage stabilizing circuit 1 includes a first positive voltage stabilizing chip U3, a second negative voltage stabilizing chip U4, a first capacitor C1, a second capacitor C2, a third capacitor C3 and a fourth capacitor C4;
the input end of the first positive voltage stabilizing chip U3 is connected with positive power supply voltage, the common end of the first positive voltage stabilizing chip U3 is grounded, and the output end of the first positive voltage stabilizing chip U3 is respectively connected with the cathode of the first photodiode D1, the positive power supply end of the first operational amplifier U1, the positive power supply end of the second operational amplifier U2, the positive power supply end of the fifth operational amplifier U5 and the positive power supply end of the sixth operational amplifier U6; the positive electrode of the first capacitor C1 is connected with the input end of the first positive voltage stabilizing chip U3, and the negative electrode of the first capacitor C is grounded; the positive electrode of the second capacitor C2 is connected with the output end of the first positive voltage stabilizing chip U3, and the negative electrode of the second capacitor C is grounded;
the input end of the second negative voltage stabilizing chip U4 is connected with a negative power supply voltage, the common end of the second negative voltage stabilizing chip U4 is grounded, and the output end of the second negative voltage stabilizing chip U4 is respectively connected with the positive electrode of the second photodiode D2, the negative power supply end of the first operational amplifier U1, the negative power supply end of the second operational amplifier U2, the negative power supply end of the fifth operational amplifier U5 and the negative power supply end of the sixth operational amplifier U6; the negative electrode of the third capacitor C3 is connected with the input end of the second negative voltage stabilizing chip U4, and the positive electrode of the third capacitor C is grounded; the negative electrode of the fourth capacitor C4 is connected with the output end of the second negative voltage stabilizing chip U4, and the positive electrode of the fourth capacitor C is grounded.
Preferably, the parallel value of the second resistor R2 and the third resistor R3 is equal to the first resistor R1; and the second resistor R2 and the third resistor R3 are metal film chip resistors.
Preferably, the first voltage reference chip L1 and the second voltage reference chip L2 are low-temperature drift voltage reference chips; the fifth operational amplifier U5 and the sixth operational amplifier U6 are precision operational amplifiers.
The utility model provides stable and low-temperature-drift power supply voltage for the fine-tuning circuit through the voltage reference circuit, ensures that the external resistor is matched to offset the influence of the bias current through the precise zero setting circuit, and simultaneously adopts a positive and negative voltage power supply mode, so that the resistance value of the resistor can be finely tuned to generate positive and negative voltage components, offset the influence of input offset voltage and offset current, and further eliminate the influence of the direct current component on the quantum signal. Compared with the prior method of isolating the direct current component by using the capacitor, the stability and the reliability of the circuit are greatly improved.
Drawings
FIG. 1 is a circuit block diagram of the present utility model;
Detailed Description
The utility model is further described below with reference to the drawings and specific examples.
As shown in fig. 1, a balanced photoelectric detector capable of precisely zeroing comprises a voltage stabilizing circuit 1, a photoelectric conversion circuit 2, an I-V conversion circuit 3 and a secondary amplifying circuit 4;
the voltage stabilizing circuit 1 is used for converting and stabilizing the power supply voltage to +/-5V, the photoelectric conversion circuit 2 is used for converting optical signals from two paths of light beams into current signals, the current signals are converted into voltage signals by the I-V conversion circuit 3 after being differenced, and the voltage signals are amplified by the secondary amplification circuit 4 and then output;
the photoelectric conversion circuit 2 includes a first photodiode D1 and a second photodiode D2 arranged in series; the anode of the first photodiode D1 and the cathode of the second photodiode D2 are connected with the input end of the I-V conversion circuit 3; the first photodiode D1 and the second photodiode D2 are both PIN photodiodes S5971 made of Si material with low dark current, low junction capacitance and good consistency, which is beneficial to improving the balance characteristic of the photoelectric conversion circuit 2 and reducing errors.
The I-V conversion circuit 3 comprises a transimpedance amplifier circuit 31 and a precision zeroing circuit 32; the output end of the photoelectric conversion circuit 2 is connected with the input end of the transimpedance amplification circuit 31; the transimpedance amplifier circuit 31 is used for converting a current signal output by the photoelectric conversion circuit 2 into a voltage signal; in this process, if the parameters of the two photodiodes are not completely consistent, such as inconsistent dark current, and weak dc current components still exist after the difference between the two current signals, the two current signals are converted into dc voltage components in the transimpedance amplifying circuit, and the imbalance of the internal structure of the op amp itself also generates a dc voltage component, and these unnecessary dc voltages not only affect the detection of the quantum signals, but also easily cause the saturation of the secondary amplifying circuit 4, so that filtering is required, and in this scheme, the precise zeroing circuit 32 is used to effectively filter the dc voltage;
the transimpedance amplifier circuit 31 includes a first operational amplifier U1 and a first resistor R1; two ends of the first resistor R1 are respectively connected with an inverting input end and an output end of the first operational amplifier U1; the inverting input end of the first operational amplifier U1 is connected with the anode of the first photodiode D1 and the cathode of the second photodiode D2, wherein the first operational amplifier U1 adopts AD8045 with high speed, high bandwidth and low noise, the slew rate is 1350V/us, the-3 dB bandwidth is 1GHz, the offset voltage is up to 1mV at most, the offset voltage drift is larger and reaches 8 uA/DEG C, and a precise zeroing circuit is needed to counteract the influence of the offset voltage on a quantum signal;
the fine zeroing circuit 32 includes a voltage reference circuit 321 and a trimmable circuit 322;
the voltage reference circuit 321 includes a fifth operational amplifier U5, a sixth operational amplifier U6, a first voltage reference chip L1, a second voltage reference chip L2, an eighth resistor R8, and a ninth resistor R9;
one end of the ninth resistor R9 is connected with positive power supply voltage, and the other end of the ninth resistor R9 is connected with the first voltage reference chip L1 and the non-inverting input end of the fifth operational amplifier U5; the other end of the first voltage reference chip L1 is grounded; the inverting input end of the fifth operational amplifier U5 is connected with the output end and outputs +1.2V voltage; one end of the eighth resistor R8 is connected with a negative power supply voltage, and the other end of the eighth resistor R8 is connected with the second voltage reference chip L2 and the non-inverting input end of the sixth operational amplifier U6; the other end of the second voltage reference chip L2 is grounded; the inverting input end of the sixth operational amplifier U6 is connected with the output end and outputs-1.2V voltage, wherein the voltage reference chips L1 and L2 adopt precise and low-temperature-drift ADR512, the output voltage is 1.2V, the initial precision is +/-0.3% at maximum, and the temperature coefficient is 60 ppm/. Degree.C. The operational amplifiers U5 and U6 both adopt ultra-precise OPA189 operational amplifiers, the maximum offset voltage is 3uV, the temperature coefficient is as low as 0.003 uV/DEG C, and the operational amplifiers can provide stable and low-temperature-drift power supply voltage for the trimmable circuit 322.
The trimmable circuit 322 includes a second resistor R2, a fourth resistor R4, and a third resistor R3 connected in sequence; one end of the second resistor R2 is connected with the output end of the fifth operational amplifier U5, and the other end of the second resistor R2 is connected with the fourth resistor R4; one end of the third resistor R3 is connected with the output end of the sixth operational amplifier U6; the fourth resistor R4 is a small-resistance trimming potentiometer, and preferably, the fourth resistor R4 is 0-10Ω; the regulating end of the fourth resistor R4 is connected with the non-inverting input end of the first operational amplifier U1, wherein the second resistor R2 and the third resistor R3 are metal film patch resistors (model ERA6ARB 122V), the tolerance is low to +/-0.1%, the temperature coefficient is low to +/-10 ppm/DEG C, the stability is good, the fourth resistor R4 is a trimming potentiometer (model 3329H-1-100 LF), the tolerance is low to +/-10%, the temperature coefficient is low to +/-100 ppm/DEG C, the parallel value of the second resistor R2 and the third resistor R3 is equal to the first resistor R1, the influence of offset current is guaranteed to be offset by matching of external resistors, meanwhile, the positive and negative voltage power supply modes are adopted, the resistance values of the resistors can be trimmed, positive and negative voltage components are generated, and the influence of input offset voltage and offset current is offset.
In this embodiment, the second-stage amplifying circuit 4 includes a second operational amplifier U2, a fifth resistor R5, a sixth resistor R6, and a seventh resistor R7; one end of the fifth resistor R5 is connected with the output end of the first operational amplifier U1, and the other end of the fifth resistor R5 is connected with the non-inverting input end of the second operational amplifier U2; one end of the sixth resistor R6 is grounded, and the other end of the sixth resistor R6 is connected with the inverting input end of the second operational amplifier U2; the two ends of the seventh resistor R7 are respectively connected with the inverting input end and the output end of the second operational amplifier U2, the voltage signal output by the I-V conversion circuit 3 is filtered by the precise zeroing circuit 32 and is output after being amplified (1+R7/R6) times by the secondary amplifying circuit 4, wherein the second operational amplifier U2 adopts high-speed, high-bandwidth and low-noise OPA847, the slew rate is 950V/us, and the gain bandwidth product is up to 3.9GHz;
in this embodiment, the voltage stabilizing circuit 1 includes a first positive voltage stabilizing chip U3, a second negative voltage stabilizing chip U4, a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4; the input end of the first positive voltage stabilizing chip U3 is connected with positive power supply voltage, the common end of the first positive voltage stabilizing chip U3 is grounded, and the output end of the first positive voltage stabilizing chip U3 is respectively connected with the cathode of the first photodiode D1, the positive power supply end of the first operational amplifier U1, the positive power supply end of the second operational amplifier U2, the positive power supply end of the fifth operational amplifier U5 and the positive power supply end of the sixth operational amplifier U6; the positive electrode of the first capacitor C1 is connected with the input end of the first positive voltage stabilizing chip U3, and the negative electrode of the first capacitor C is grounded; the positive electrode of the second capacitor C2 is connected with the output end of the first positive voltage stabilizing chip U3, and the negative electrode of the second capacitor C is grounded; the input end of the second negative voltage stabilizing chip U4 is connected with a negative power supply voltage, the common end of the second negative voltage stabilizing chip U4 is grounded, and the output end of the second negative voltage stabilizing chip U4 is respectively connected with the positive electrode of the second photodiode D2, the negative power supply end of the first operational amplifier U1, the negative power supply end of the second operational amplifier U2, the negative power supply end of the fifth operational amplifier U5 and the negative power supply end of the sixth operational amplifier U6; the negative electrode of the third capacitor C3 is connected with the input end of the second negative voltage stabilizing chip U4, and the positive electrode of the third capacitor C is grounded; the negative electrode of the fourth capacitor C4 is connected with the output end of the second negative voltage stabilizing chip U4, and the positive electrode of the fourth capacitor C4 is grounded, wherein the first capacitor C1, the second capacitor C2, the third capacitor C3 and the fourth capacitor C4 are all polarity capacitors; the first positive voltage stabilizing chip U3 selects 7805 voltage stabilizing chips, the second negative voltage stabilizing chip U4 selects 7905 voltage stabilizing chips, the capacitance value of the first capacitor C1 and the third capacitor C3 is 220nF, the capacitance value of the second capacitor C2 and the fourth capacitor C4 is 100nF, and the voltage stabilizing circuit realizes the conversion and stabilization of power supply voltage.
Claims (9)
1. The balanced photoelectric detector capable of precisely zeroing is characterized by comprising a voltage stabilizing circuit (1), a photoelectric conversion circuit (2), an I-V conversion circuit (3) and a secondary amplifying circuit (4);
the photoelectric conversion circuit (2) is connected with the I-V conversion circuit (3); the I-V conversion circuit (3) is connected with the secondary amplifying circuit (4); the voltage stabilizing circuit (1) is used for converting and stabilizing the power supply voltage; the voltage stabilizing circuit (1) is respectively connected with the photoelectric conversion circuit (2), the I-V conversion circuit (3) and the secondary amplifying circuit (4);
the I-V conversion circuit (3) comprises a transimpedance amplifying circuit (31) and a precise zeroing circuit (32);
the transimpedance amplifying circuit (31) is used for converting a current signal output by the photoelectric conversion circuit (2) into a voltage signal;
the precise zeroing circuit (32) comprises a voltage reference circuit (321) and a trimmable circuit (322);
the voltage reference circuit (321) is connected with the fine-tuning circuit (322); the fine-tuning circuit (322) is connected with the transimpedance amplifying circuit (31).
2. The precisely zeroable balanced photodetector according to claim 1, wherein said voltage reference circuit (321) comprises a fifth operational amplifier U5, a sixth operational amplifier U6, a first voltage reference chip L1, a second voltage reference chip L2, an eighth resistor R8 and a ninth resistor R9;
one end of the ninth resistor R9 is connected with positive power supply voltage, and the other end of the ninth resistor R9 is connected with the first voltage reference chip L1 and the non-inverting input end of the fifth operational amplifier U5; the other end of the first voltage reference chip L1 is grounded; the inverting input end of the fifth operational amplifier U5 is connected with the output end;
one end of the eighth resistor R8 is connected with a negative power supply voltage, and the other end of the eighth resistor R8 is connected with the second voltage reference chip L2 and the non-inverting input end of the sixth operational amplifier U6; the other end of the second voltage reference chip L2 is grounded; the inverting input end of the sixth operational amplifier U6 is connected with the output end.
3. The precisely zeroable balanced photodetector according to claim 2, wherein said trimmable circuit (322) comprises a second resistor R2, a fourth resistor R4 and a third resistor R3 connected in sequence; one end of the second resistor R2 is connected with the output end of the fifth operational amplifier U5; one end of the third resistor R3 is connected with the output end of the sixth operational amplifier U6; the fourth resistor R4 is a trimming potentiometer; and the adjusting end of the fourth resistor R4 is connected with a transimpedance amplifying circuit (31).
4. A balanced photodetector with fine nulling according to claim 3, characterized in that the transimpedance amplification circuit (31) comprises a first operational amplifier U1 and a first resistor R1; two ends of the first resistor R1 are respectively connected with an inverting input end and an output end of the first operational amplifier U1; the non-inverting input end of the first operational amplifier U1 is connected with the adjusting end of the fourth resistor R4; the inverting input end of the first operational amplifier U1 is connected with the output end of the photoelectric conversion circuit (2); the output end of the first operational amplifier U1 is connected with the secondary amplifying circuit (4).
5. The precisely zeroable balanced photodetector according to claim 1, characterized in that said photoelectric conversion circuit (2) comprises a first photodiode D1 and a second photodiode D2 arranged in series; the anode of the first photodiode D1 and the cathode of the second photodiode D2 are connected with the input end of the I-V conversion circuit (3).
6. The precisely zeroable balanced photodetector according to claim 1, wherein said secondary amplifying circuit (4) comprises a second operational amplifier U2, a fifth resistor R5, a sixth resistor R6 and a seventh resistor R7;
one end of the fifth resistor R5 is connected with the output end of the I-V conversion circuit (3), and the other end of the fifth resistor R5 is connected with the non-inverting input end of the second operational amplifier U2; one end of the sixth resistor R6 is grounded, and the other end of the sixth resistor R6 is connected with the inverting input end of the second operational amplifier U2; two ends of the seventh resistor R7 are respectively connected with an inverting input end and an output end of the second operational amplifier U2.
7. The precisely zeroable balanced photodetector according to any one of the claims 1 to 6, wherein said voltage regulator circuit (1) comprises a first positive voltage regulator chip U3, a second negative voltage regulator chip U4, a first capacitor C1, a second capacitor C2, a third capacitor C3 and a fourth capacitor C4;
the input end of the first positive voltage stabilizing chip U3 is connected with positive power supply voltage, the common end of the first positive voltage stabilizing chip U3 is grounded, and the output end of the first positive voltage stabilizing chip U3 is respectively connected with the cathode of the first photodiode D1, the positive power supply end of the first operational amplifier U1, the positive power supply end of the second operational amplifier U2, the positive power supply end of the fifth operational amplifier U5 and the positive power supply end of the sixth operational amplifier U6; the positive electrode of the first capacitor C1 is connected with the input end of the first positive voltage stabilizing chip U3, and the negative electrode of the first capacitor C is grounded; the positive electrode of the second capacitor C2 is connected with the output end of the first positive voltage stabilizing chip U3, and the negative electrode of the second capacitor C is grounded;
the input end of the second negative voltage stabilizing chip U4 is connected with a negative power supply voltage, the common end of the second negative voltage stabilizing chip U4 is grounded, and the output end of the second negative voltage stabilizing chip U4 is respectively connected with the positive electrode of the second photodiode D2, the negative power supply end of the first operational amplifier U1, the negative power supply end of the second operational amplifier U2, the negative power supply end of the fifth operational amplifier U5 and the negative power supply end of the sixth operational amplifier U6; the negative electrode of the third capacitor C3 is connected with the input end of the second negative voltage stabilizing chip U4, and the positive electrode of the third capacitor C is grounded; the negative electrode of the fourth capacitor C4 is connected with the output end of the second negative voltage stabilizing chip U4, and the positive electrode of the fourth capacitor C is grounded.
8. The precisely zeroable balanced photodetector of claim 3 or 4, wherein the parallel value of said second resistor R2 and third resistor R3 is equal to the first resistor R1; and the second resistor R2 and the third resistor R3 are metal film chip resistors.
9. The balanced photodetector of claim 2, wherein the first voltage reference chip L1 and the second voltage reference chip L2 are low temperature drift voltage reference chips; the fifth operational amplifier U5 and the sixth operational amplifier U6 are precision operational amplifiers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322186293.4U CN220583602U (en) | 2023-08-14 | 2023-08-14 | Balanced photoelectric detector capable of precisely zeroing |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322186293.4U CN220583602U (en) | 2023-08-14 | 2023-08-14 | Balanced photoelectric detector capable of precisely zeroing |
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| Publication Number | Publication Date |
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| CN220583602U true CN220583602U (en) | 2024-03-12 |
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| CN202322186293.4U Active CN220583602U (en) | 2023-08-14 | 2023-08-14 | Balanced photoelectric detector capable of precisely zeroing |
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2023
- 2023-08-14 CN CN202322186293.4U patent/CN220583602U/en active Active
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