CN220554004U - AD sampling system - Google Patents
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- CN220554004U CN220554004U CN202321027843.1U CN202321027843U CN220554004U CN 220554004 U CN220554004 U CN 220554004U CN 202321027843 U CN202321027843 U CN 202321027843U CN 220554004 U CN220554004 U CN 220554004U
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- 238000005070 sampling Methods 0.000 title claims abstract description 92
- 238000001914 filtration Methods 0.000 claims abstract description 28
- 239000003990 capacitor Substances 0.000 claims description 30
- 239000004973 liquid crystal related substance Substances 0.000 claims description 7
- 238000006243 chemical reaction Methods 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 12
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- 101100041125 Arabidopsis thaliana RST1 gene Proteins 0.000 description 2
- 101100443250 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) DIG1 gene Proteins 0.000 description 2
- 101100420795 Schizosaccharomyces pombe (strain 972 / ATCC 24843) sck1 gene Proteins 0.000 description 2
- 101100309620 Schizosaccharomyces pombe (strain 972 / ATCC 24843) sck2 gene Proteins 0.000 description 2
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Abstract
The utility model discloses an AD sampling system, which comprises: the device comprises an AD sampling module, a main control module and a display module; the AD sampling module is connected with the main control module and is used for collecting signals of a circuit to be tested according to the control of the main control module; the display module is connected with the main control module and is used for displaying the acquired voltage value according to the control of the main control module; the main control module is also used for filtering the data acquired by the AD sampling module by adopting a median average filtering algorithm. The AD sampling system provided by the embodiment of the utility model solves the technical problem of low high-precision AD sampling conversion speed.
Description
Technical Field
The utility model relates to the technical field of AD sampling, in particular to an AD sampling system.
Background
At present, most AD sampling is concentrated in a singlechip and used as a built-in module of the singlechip, and the sampling precision is low and the temperature drift is large. The accuracy of AD sampling of the independent chips adopted in most of the market is slightly improved, and the AD sampling can reach 16 bits, but the AD sampling is expensive, but the AD sampling still does not meet the requirements of many industrial scenes. For many battery voltage signal acquisition modules, the voltage accuracy is required to be about 18 bits, and the anti-interference capability is required to be strong, and many AD sampling conversion speeds are slow, and the signal acquisition speed is slow, so that the real-time requirement cannot be met.
Disclosure of Invention
The utility model provides an AD sampling system for solving the technical problem of low conversion speed of high-precision AD sampling.
The utility model provides an AD sampling system, comprising: the device comprises an AD sampling module, a main control module and a display module;
the AD sampling module is connected with the main control module and is used for collecting signals of a circuit to be tested according to the control of the main control module;
the display module is connected with the main control module and is used for displaying the acquired voltage value according to the control of the main control module;
the main control module is also used for filtering the data acquired by the AD sampling module by adopting a median average filtering algorithm.
Optionally, the AD sampling system further includes a reference voltage adjustment module;
the reference voltage adjusting module is connected with the AD sampling module and is used for providing stable reference voltage for the AD sampling circuit.
Optionally, the AD sampling system further includes a filtering module;
the filtering module is connected with the AD sampling module and used for guaranteeing the accuracy of AD sampling.
Optionally, the reference voltage adjustment module includes: REF2925 chip.
Optionally, the AD sampling module includes an ADs1256 chip.
Optionally, the main control module includes an STM32F103C8T6 chip.
Optionally, the display module comprises a liquid crystal display screen and a GT20L16S 1Y-shaped library chip.
The STM32F103C8T6 chip comprises a first pin, a second pin, a third pin, a fourth pin, a fifth pin, a sixth pin, a seventh pin, an eighth pin and a ninth pin;
the liquid crystal display includes: the first chip select end, the first reset end, the first data end, the register select end, the first clock end, the power end and the grounding end;
the GT20L16S 1Y-word stock chip comprises: the power supply end, the grounding end, the second chip select end, the second clock end, the second output end and the second input end;
the first pin is connected with the second chip select end, the second pin is connected with the second clock end, the third pin is connected with the second output end, and the fourth pin is connected with the second input end;
the fifth pin is connected with the first chip select end, the sixth pin is connected with the first reset end, the seventh pin is connected with the first data end, the eighth pin is connected with the first clock end, and the ninth pin is connected with the register select end.
Optionally, the filtering module includes a plurality of filtering circuits, and the plurality of filtering circuits are connected with the AD sampling module;
optionally, the filter circuit includes a resistor and a capacitor;
one end of the resistor is connected with the AD sampling module, and the other end of the resistor is connected with a circuit to be tested through a twisted pair with a shielding layer;
one end of the capacitor is connected with the AD sampling module, and the other end of the capacitor is grounded.
Optionally, the reference voltage adjustment module further includes a third capacitor and a fourth capacitor;
the REF2925 chip comprises a voltage input end, a voltage output end and a grounding end;
the positive electrode of the third capacitor is connected with the voltage input end, the negative electrode of the third capacitor is grounded, and the positive electrode of the third capacitor is also connected with the input voltage;
the positive electrode of the fourth capacitor is connected with the voltage output end, and the negative electrode of the fourth capacitor is grounded;
the voltage output end is also connected with the AD sampling module and is used for providing stable reference voltage for the AD sampling module.
The AD sampling system provided by the embodiment of the utility model comprises: the device comprises an AD sampling module, a main control module and a display module; the AD sampling module is connected with the main control module and is used for collecting signals of a circuit to be tested according to the control of the main control module; the display module is connected with the main control module and is used for displaying the acquired voltage value according to the control of the main control module; the main control module is also used for filtering the data acquired by the AD sampling module by adopting a median average filtering algorithm. The AD sampling system provided by the embodiment of the utility model solves the technical problem of low high-precision AD sampling conversion speed.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the utility model or to delineate the scope of the utility model. Other features of the present utility model will become apparent from the description that follows.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present utility model, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of an AD sampling system according to an embodiment of the present utility model;
fig. 2 is a schematic structural diagram of another AD sampling system according to an embodiment of the present utility model;
fig. 3 is a schematic structural diagram of a reference voltage adjustment module according to an embodiment of the present utility model;
fig. 4 is a schematic structural diagram of a filtering module according to an embodiment of the present utility model;
fig. 5 is a schematic structural diagram of a main control module according to an embodiment of the present utility model;
fig. 6 is a schematic structural diagram of a display module according to an embodiment of the utility model.
Detailed Description
In order that those skilled in the art will better understand the present utility model, a technical solution in the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present utility model, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present utility model without making any inventive effort, shall fall within the scope of the present utility model.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present utility model and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the utility model described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Example 1
Fig. 1 is a schematic structural diagram of an AD sampling system according to an embodiment of the present utility model, and referring to fig. 1, the AD sampling system includes: AD sampling module 110, main control module 120, and display module 130.
The AD sampling module 110 is connected to the main control module 120, and is configured to perform signal acquisition on a circuit to be tested according to control of the main control module 120.
The display module 130 is connected to the main control module 120, and is configured to display the collected voltage value according to control of the main control module 120.
The main control module 120 is further configured to perform filtering processing on the data collected by the AD sampling module 110 by using a median average filtering algorithm.
The AD sampling system provided by the embodiment of the utility model comprises: the device comprises an AD sampling module, a main control module and a display module; the AD sampling module is connected with the main control module and is used for collecting signals of a circuit to be tested according to the control of the main control module; the display module is connected with the main control module and is used for displaying the acquired voltage value according to the control of the main control module; the main control module is also used for filtering the data acquired by the AD sampling module by adopting a median average filtering algorithm. The AD sampling system provided by the embodiment of the utility model solves the technical problem of low high-precision AD sampling conversion speed.
Example two
Fig. 2 is a schematic structural diagram of another AD sampling system according to an embodiment of the present utility model, and referring to fig. 2, the AD sampling system further includes a reference voltage adjustment module 140. The reference voltage adjustment module 140 is connected to the AD sampling module 110, and is configured to provide a stable reference voltage for the AD sampling circuit.
Fig. 3 is a schematic structural diagram of a reference voltage adjustment module according to an embodiment of the present utility model, and referring to fig. 3, optionally, in an embodiment of the present utility model, a reference voltage adjustment module 140 includes: REF2925 chip. The reference voltage adjustment module 140 further includes a third capacitor C3 and a fourth capacitor C4.
With continued reference to fig. 3, the REF2925 chip includes a voltage input Vin, a voltage output Vout, and a ground GND. The positive pole of the third capacitor C3 is connected with the voltage input end Vin, the negative pole is grounded, and the positive pole of the third capacitor C3 is also connected with the input voltage. The positive electrode of the fourth capacitor C4 is connected with the voltage output end Vout, and the negative electrode is grounded.
In the embodiment of the present utility model, the voltage output terminal Vout is further connected to the AD sampling module 110, so as to provide a stable reference voltage for the AD sampling module.
Optionally, in an embodiment of the present utility model, the AD sampling module 110 includes an ADs1256 chip, where the ADs1256 chip includes a reference voltage input terminal VREFp, and the voltage output terminal Vout is connected to the AD sampling module 110 through the reference voltage input terminal VREFp.
Wherein the input voltage is plus 5V, the capacitance value of the third capacitor C3 is 0.1uf, and the capacitance value of the fourth capacitor is 10uf.
The reference voltage adjusting module provided by the embodiment of the utility model can ensure that the reference voltage is 2.5V and provide stable reference voltage for the AD sampling module.
Optionally, with continued reference to fig. 2, the AD sampling system further includes a filtering module 150. The filtering module 150 is connected to the AD sampling module 110, and is configured to ensure the accuracy of AD sampling.
Optionally, in an embodiment of the present utility model, the filtering module 150 includes a plurality of filtering circuits, and a plurality of the filtering circuits are connected to the AD sampling module 110.
Fig. 4 is a schematic structural diagram of a filter circuit according to an embodiment of the present utility model, and referring to fig. 4, a filter circuit 151 includes a resistor R and a capacitor C.
One end of the resistor R is connected with the AD sampling module 110, the other end of the resistor R is connected with the circuit 160 to be tested through the twisted pair 152 with the shielding layer, one end of the capacitor C is connected with the AD sampling module 110, and the other end of the capacitor C is grounded.
In the embodiment of the utility model, the shortest twisted pair with the shielding layer is used, and in addition, the acquisition is carried out in a silent, airtight and dustproof environment, so that the influence of interference on external input signals can be ensured to be as small as possible.
The filter circuit provided by the embodiment of the utility model can improve the accuracy of AD sampling.
Fig. 5 is a schematic structural diagram of a main control module according to an embodiment of the present utility model, and referring to fig. 5, a main control module 120 includes an STM32F103C8T6 chip.
The STM32F103C8T6 chip comprises a first pin PB1, a second pin PB2, a third pin PB3, a fourth pin PB4, a fifth pin PB5, a sixth pin PB6, a seventh pin PB7, an eighth pin PB8 and a ninth pin PB9.
Optionally, in the embodiment of the present utility model, the display module 130 includes a liquid crystal display and a GT20L16S 1Y-word stock chip.
Fig. 6 is a schematic structural diagram of a display module according to an embodiment of the present utility model, and referring to fig. 6, a display module 130 includes a liquid crystal display 131 and a GT20L16S 1Y-bank chip 132.
The liquid crystal display 131 includes: the first chip select terminal CS1, the first reset terminal RST1, the first data terminal SDA1, the register select terminal RS1, the first clock terminal SCK1, the power supply terminal VDD, and the ground terminal GND.
The GT20L16S 1Y-word stock chip 132 includes: a power supply terminal VDD, a ground terminal GND, a second chip select terminal CS2, a second clock terminal SCK2, a second output terminal OUT2, and a second input terminal IN2.
IN the embodiment of the present utility model, the first pin PB1 is connected to the second chip select terminal CS2, the second pin PB2 is connected to the second clock terminal SCK2, the third pin PB3 is connected to the second output terminal OUT2, and the fourth pin PB4 is connected to the second input terminal IN2.
The fifth pin PB5 is connected to the first chip select terminal CS1, the sixth pin PB6 is connected to the first reset terminal RST1, the seventh pin PB7 is connected to the first data terminal SDA1, the eighth pin PB8 is connected to the first clock terminal SCK1, and the ninth pin is connected to the register select terminal RS 1.
The embodiment of the utility model provides the main control module which can improve the AD sampling conversion speed, has high signal acquisition speed, can display the signals in time through the display module and meets the real-time requirement.
The above embodiments do not limit the scope of the present utility model. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present utility model should be included in the scope of the present utility model.
Claims (7)
1. An AD sampling system, comprising: the device comprises an AD sampling module, a main control module and a display module;
the AD sampling module is connected with the main control module and is used for collecting signals of a circuit to be tested according to the control of the main control module;
the display module is connected with the main control module and is used for displaying the acquired voltage value according to the control of the main control module;
the main control module is also used for filtering the data acquired by the AD sampling module by adopting a median average filtering algorithm; the main control module comprises an STM32F103C8T6 chip;
the AD sampling system further comprises a filtering module;
the filtering module is connected with the AD sampling module and is used for guaranteeing the accuracy of AD sampling;
the filtering module comprises a plurality of filtering circuits, and the filtering circuits are connected with the AD sampling module;
the filter circuit comprises a resistor and a capacitor;
one end of the resistor is connected with the AD sampling module, and the other end of the resistor is connected with a circuit to be tested through a twisted pair with a shielding layer;
one end of the capacitor is connected with the AD sampling module, and the other end of the capacitor is grounded.
2. The AD sampling system of claim 1, further comprising a reference voltage adjustment module;
the reference voltage adjusting module is connected with the AD sampling module and is used for providing stable reference voltage for the AD sampling module.
3. The AD sampling system of claim 2, wherein the reference voltage adjustment module comprises: REF2925 chip.
4. The AD sampling system of claim 1, wherein the AD sampling module comprises an ADs1256 chip.
5. The AD sampling system of claim 1, wherein the display module comprises a liquid crystal display and a GT20L16S 1Y-bank chip.
6. The AD sampling system of claim 5, wherein the STM32F103C8T6 chip comprises a first pin, a second pin, a third pin, a fourth pin, a fifth pin, a sixth pin, a seventh pin, an eighth pin, a ninth pin;
the liquid crystal display includes: the first chip select end, the first reset end, the first data end, the register select end, the first clock end, the power end and the grounding end;
the GT20L16S 1Y-word stock chip comprises: the power supply end, the grounding end, the second chip select end, the second clock end, the second output end and the second input end;
the first pin is connected with the second chip select end, the second pin is connected with the second clock end, the third pin is connected with the second output end, and the fourth pin is connected with the second input end;
the fifth pin is connected with the first chip select end, the sixth pin is connected with the first reset end, the seventh pin is connected with the first data end, the eighth pin is connected with the first clock end, and the ninth pin is connected with the register select end.
7. The AD sampling system of claim 3, wherein the reference voltage adjustment module further comprises a third capacitor and a fourth capacitor;
the REF2925 chip comprises a voltage input end, a voltage output end and a grounding end;
the positive electrode of the third capacitor is connected with the voltage input end, the negative electrode of the third capacitor is grounded, and the positive electrode of the third capacitor is also connected with the input voltage;
the positive electrode of the fourth capacitor is connected with the voltage output end, and the negative electrode of the fourth capacitor is grounded;
the voltage output end is also connected with the AD sampling module and is used for providing stable reference voltage for the AD sampling module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321027843.1U CN220554004U (en) | 2023-05-04 | 2023-05-04 | AD sampling system |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321027843.1U CN220554004U (en) | 2023-05-04 | 2023-05-04 | AD sampling system |
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| CN220554004U true CN220554004U (en) | 2024-03-01 |
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| CN202321027843.1U Active CN220554004U (en) | 2023-05-04 | 2023-05-04 | AD sampling system |
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- 2023-05-04 CN CN202321027843.1U patent/CN220554004U/en active Active
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