CN213517468U - Double-singlechip battery test circuit - Google Patents
Double-singlechip battery test circuit Download PDFInfo
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- CN213517468U CN213517468U CN202021436497.9U CN202021436497U CN213517468U CN 213517468 U CN213517468 U CN 213517468U CN 202021436497 U CN202021436497 U CN 202021436497U CN 213517468 U CN213517468 U CN 213517468U
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Abstract
The application relates to a double-singlechip battery test circuit, which at least comprises a first singlechip circuit and a second singlechip circuit, wherein the first singlechip circuit comprises a first singlechip and a power supply circuit connected to the anode of a workpiece to be tested, the first singlechip is respectively connected with a test host and the power supply circuit, and the first singlechip is used for receiving instructions of the test host and discharging at two ends of the workpiece to be tested through the power supply circuit; the second single chip microcomputer circuit comprises a second single chip microcomputer and an acquisition circuit connected to any end of the workpiece to be tested, the second single chip microcomputer is respectively connected with the test host and the acquisition circuit, and the second single chip microcomputer is used for acquiring the test value of the workpiece to be tested through the acquisition circuit and feeding the test value back to the receiving test host. The beneficial effects are that: according to the method and the device, microsecond-level high-precision event synchronous processing can be realized by arranging the first single chip microcomputer circuit and the second single chip microcomputer circuit, debugging is more convenient and accurate, and the reliability of the system is improved.
Description
Technical Field
The application relates to the technical field of battery production, in particular to a double-singlechip battery test circuit.
Background
The traditional battery test equipment adopts a detection system consisting of a single chip microcomputer, and when two or more tasks need to be carried out synchronously, an accurate result cannot be obtained. Moreover, when a high-precision microsecond-level test is required, because one single chip microcomputer cannot synchronously execute two events, the test result is easy to have errors, and the product yield is low.
Disclosure of Invention
The application provides a double-singlechip battery test circuit for solving the technical problem that errors are easy to occur in the test result of a singlechip due to the fact that two events cannot be synchronously executed, and the product yield is not high.
A dual-single-chip battery test circuit at least comprises a first single-chip circuit and a second single-chip circuit, wherein,
the first single chip microcomputer circuit comprises a first single chip microcomputer and a power supply circuit connected to the anode OB + of the workpiece to be tested, the first single chip microcomputer is respectively connected with the test host and the power supply circuit, and the first single chip microcomputer is used for receiving instructions of the test host and discharging at two ends of the workpiece to be tested through the power supply circuit;
the second single chip microcomputer circuit comprises a second single chip microcomputer and an acquisition circuit connected to any end of the workpiece to be tested, the second single chip microcomputer is respectively connected with the test host and the acquisition circuit, and the second single chip microcomputer is used for acquiring the test value of the workpiece to be tested through the acquisition circuit and feeding the test value back to the receiving test host.
Optionally, the first single chip microcomputer is provided with a test communication input end and a first signal end, the first single chip microcomputer is connected with the test host through the test communication input end, and the first single chip microcomputer is connected with the power supply circuit through the first signal end.
Optionally, the first single chip microcomputer is further provided with a first power input end connected with an input power supply, and the first power input end is further connected with a filter capacitor.
Optionally, the power supply circuit includes a first operational amplifier connected to the first single chip, a non-inverting input terminal of the first operational amplifier is connected to the first signal terminal, and an inverting input terminal of the first operational amplifier is connected to an output terminal of the first operational amplifier; the output end of the first operational amplifier is connected with the anode of the workpiece to be detected, and the cathode of the workpiece to be detected is grounded through a first resistor; and a first capacitor is connected between the anode and the cathode of the workpiece to be measured.
Optionally, a second resistor is further connected between the non-inverting input terminal and the first signal terminal of the first operational amplifier.
Optionally, the second single chip microcomputer is provided with a test communication output end and a second signal end, the second single chip microcomputer is connected with the test host through the test communication output end, and the first single chip microcomputer is connected with the acquisition circuit through the second signal end.
Optionally, the second single chip microcomputer is further provided with a second power input end connected with an input power supply, and the second power input end is further connected with a filter capacitor.
Optionally, the acquisition circuit includes a second operational amplifier, a non-inverting input terminal of the second operational amplifier is connected to a negative electrode of the workpiece to be measured through a third resistor, and an output terminal of the second operational amplifier is connected to the second signal terminal; the inverting input end of the second operational amplifier is grounded through a fourth resistor, and the inverting input end of the second operational amplifier is connected with the output end of the second operational amplifier through a fifth resistor.
Optionally, the output end of the second operational amplifier is further connected to a filter circuit, and the filter circuit includes a second capacitor and a sixth resistor which are connected in parallel between the output end of the second operational amplifier and a power ground.
Optionally, the first single chip microcomputer and the second single chip microcomputer are both STM32F103VCT6 in model.
The application discloses two single chip microcomputer battery test circuit, its beneficial effect lies in: according to the method and the device, microsecond-level high-precision event synchronous processing can be realized by arranging the first single chip microcomputer circuit and the second single chip microcomputer circuit, no matter how large the first single chip microcomputer program is written, interruption for performing certain processing is not needed to be considered, debugging is greatly facilitated, and the reliability of the system is improved; thereby providing the yield of the product.
Drawings
Fig. 1 is a schematic structural diagram of a circuit according to an embodiment of the present application.
Fig. 2 is a schematic diagram of a first single chip microcomputer according to an embodiment of the present application.
Fig. 3 is a schematic diagram of a power supply circuit according to an embodiment of the present application.
Fig. 4 is a power supply schematic diagram of a second single chip microcomputer according to the embodiment of the present application.
Fig. 5 is a schematic diagram of an acquisition circuit according to an embodiment of the present application.
Detailed Description
The following detailed description of the preferred embodiments of the present application, taken in conjunction with the accompanying drawings, will make the advantages and features of the present application more readily appreciated by those skilled in the art, and thus will more clearly define the scope of the invention.
In an embodiment as shown in fig. 1, the present application provides a dual-monolithic-machine battery test circuit comprising at least a first monolithic circuit and a second monolithic circuit, wherein,
the first single chip microcomputer circuit comprises a first single chip microcomputer U1 and a power supply circuit connected to the anode OB + of the workpiece to be tested, the first single chip microcomputer U1 is respectively connected with the test host and the power supply circuit, and the first single chip microcomputer U1 is used for receiving instructions of the test host and discharging at two ends of the workpiece to be tested through the power supply circuit;
the second single chip microcomputer circuit comprises a second single chip microcomputer U2 and an acquisition circuit connected to any end of the workpiece to be tested, the second single chip microcomputer U2 is connected with the test host and the acquisition circuit respectively, and the second single chip microcomputer U2 is used for acquiring the test value of the workpiece to be tested through the acquisition circuit and feeding the test value back to the receiving test host.
In the embodiment, the first single chip microcomputer circuit receives an instruction sent by a test host, and outputs an instruction pair operation to a workpiece to be tested through the power supply circuit according to the instruction; meanwhile, the second singlechip circuit collects the test value of the workpiece to be tested through the collecting circuit and feeds the test value back to the test host through the second singlechip U2 to complete the test of the workpiece to be tested. The workpiece to be tested can be a workpiece, and the instruction sent by the test host can be system voltage, current or a delay command; the first monolithic circuit outputs a corresponding system voltage or current or a delay command; the acquisition circuit acquires corresponding system voltage values, current values or delay values and outputs the system voltage values, the current values or the delay values to the test host through the second single chip microcomputer U2. According to the method and the device, microsecond-level high-precision event synchronous processing can be realized by arranging the first single chip microcomputer circuit and the second single chip microcomputer circuit, no matter how large the U1 program is written, interruption for performing certain processing is not needed to be considered, debugging is greatly facilitated, and the reliability of the system is improved; thereby providing the yield of the product.
In some embodiments, referring to fig. 2, the first single chip microcomputer U1 is provided with a test communication input terminal U1_ PA9, a test communication input terminal U1_ PA10, a test communication input terminal GND and a first signal terminal U1_ DA1, the first single chip microcomputer U1 is connected with the test host through the test communication input terminal U1_ PA9, the test communication input terminal U1_ PA10 and the test communication input terminal GND, and the first single chip microcomputer U1 is connected with the power supply circuit through the first signal terminal U1_ DA 1. The first single chip microcomputer U1 can be a chip with the model number of STM32F103VCT6, the first single chip microcomputer U1 obtains signals of the test host through connection of a test communication input end U1_ PA9 and a test communication input end U1_ PA10 with the test host through GND; and the first singlechip U1 is connected with the power supply circuit through a first signal end U1_ DA1 to output corresponding operation. First singlechip U1 still sets up the first power input end who is connected with input power VCC, and first power input end still is connected with filter capacitor. In this embodiment, the input power VCC may be a 3.3V single chip microcomputer operating power supply. And 6 first power supply input ends are arranged in the first single chip microcomputer U1 and used for acquiring an input power supply VCC. Still be connected with filter capacitor at first power input end, filter capacitor other end ground connection, wherein, filter capacitor plays the clutter that filters input power VCC in this embodiment for the protection circuit effect.
In some embodiments, referring to fig. 3, the power supply circuit includes a first operational amplifier U3 connected to the first monolithic computer U1, a non-inverting input of the first operational amplifier U3 connected to the first signal terminal U1_ DA1, an inverting input of the first operational amplifier U3 connected to an output of the first operational amplifier U3; the output end of the first operational amplifier U3 is connected with the anode OB + of the workpiece to be detected, and the cathode OB-of the workpiece to be detected is grounded through a first resistor R1; and a first capacitor C1 is connected between the anode and the cathode of the workpiece to be measured. In the embodiment in this market, the first operational amplifier U3 receives a signal from the first single chip microcomputer U1 through the non-inverting input terminal, and outputs the signal to the positive electrode OB + of the workpiece to be tested, i.e., the positive electrode of the battery, through the first operational amplifier U3. The negative pole OB-of the workpiece to be measured is also connected with a first capacitor C1 and a first resistor R1, and is used for filtering a clutter stabilizing circuit. A second resistor R2 is connected between the non-inverting input terminal of the first operational amplifier U3 and the first signal terminal U1_ DA1, and is used for current-limiting protection of the power supply circuit. In this embodiment, the first operational amplifier U3 may be an OP279 OP amp chip.
In some embodiments, referring to fig. 4, the second mcu U2 is provided with a test communication output terminal U2_ PA9, a test communication output terminal U2_ PA10, a test communication output terminal GND and a second signal terminal U2_ DA1, the second mcu U2 is connected to the test host through the test communication output terminal U2_ PA9, the test communication output terminal U2_ PA10 and the test communication output terminal GND, and the first mcu U1 is connected to the acquisition circuit through the second signal terminal U2_ DA 1. The second single chip microcomputer U2 can be a chip with model STM32F103VCT6, the second single chip microcomputer U2 obtains the signals collected by the collecting circuit through a second signal end U2_ DA1, and transmits the collected signals to the test host through a test communication output end U2_ PA9 and a test communication output end U2_ PA 10. The second singlechip U2 still sets up the second power input end who is connected with input power VCC, and second power input end still is connected with filter capacitor. In this embodiment, the input power VCC may be a 3.3V single chip microcomputer operating power supply. And 6 second power supply input ends are arranged in the second single chip microcomputer U2 and used for acquiring an input power supply VCC. The second power input end is also connected with a filter capacitor, and the other end of the filter capacitor is grounded, wherein the filter capacitor plays a role in filtering clutter of the input power VCC in the embodiment and is used for protecting the circuit.
In some embodiments, referring to fig. 5, the acquisition circuit includes a second operational amplifier U4, the non-inverting input terminal of the second operational amplifier U4 is connected to the negative pole OB "of the workpiece to be tested through a third resistor R3, and the output terminal of the second operational amplifier U4 is connected to a second signal terminal U2_ DA 1; the inverting input terminal of the second operational amplifier U4 is connected to ground through a fourth resistor R4, and the inverting input terminal of the second operational amplifier U4 is connected to the output terminal of the second operational amplifier U4 through a fifth resistor R5. In the embodiment, the non-inverting input end of the second operational amplifier U4 is connected to the negative pole OB-of the workpiece to be tested through a third resistor R3, wherein the third resistor R3 plays a role in current limiting; the second operational amplifier U4 collects the voltage value or the current value or the delay value of the workpiece to be detected through the non-inverting input end and outputs the voltage value or the current value or the delay value to the second singlechip U2 through the output end of the second operational amplifier U4. The inverting input terminal of the second operational amplifier U4 is grounded through a fourth resistor R4, and the inverting input terminal of the second operational amplifier U4 is connected to the output terminal of the second operational amplifier U4 through a fifth resistor R5; the circuit is stabilized by the fourth resistor R4 and the fifth resistor R5. The output end of the second operational amplifier U4 is further connected with a filter circuit, and the filter circuit comprises a second capacitor C2 and a sixth resistor R6 which are connected in parallel between the output end of the second operational amplifier U4 and the power ground. In this embodiment, the filter circuit filters noise through the second capacitor C2, and performs current limiting through the sixth resistor R6 to protect the circuit. In this embodiment, the second operational amplifier U4 chip may be an AD8552 op-amp chip.
When the first single-chip microcomputer U1 receives a voltage/current/delay command of a test system, a value set by the system is immediately output according to the command, and meanwhile, the second single-chip microcomputer U2 also receives a synchronous acquisition command and feeds back whether the system of the first single-chip microcomputer U1 is successfully executed in real time. Moreover, when high-precision microsecond-level protection delay grabbing is needed, the accuracy of the system is better, because the two single-chip microcomputers are synchronously carried out, the whole system is not influenced by program size, scanning time of the single-chip microcomputers, program interruption and the like, and numerical values can be quickly and accurately acquired. No matter how large the program of the first single chip microcomputer U1 is written, interruption is not needed to be considered for carrying out certain processing, debugging is greatly facilitated, and reliability of the system is improved.
The embodiments of the present application have been described in detail with reference to the drawings, but the present application is not limited to the above embodiments, and various changes can be made without departing from the spirit of the present application within the knowledge of those skilled in the art.
Claims (10)
1. A dual-single-chip battery test circuit is characterized by at least comprising a first single-chip circuit and a second single-chip circuit, wherein,
the first single chip microcomputer circuit comprises a first single chip microcomputer (U1) and a power supply circuit connected to the anode of the workpiece to be tested, the first single chip microcomputer (U1) is respectively connected with the test host and the power supply circuit, and the first single chip microcomputer (U1) is used for receiving instructions of the test host and discharging at two ends of the workpiece to be tested through the power supply circuit;
the second single chip microcomputer circuit comprises a second single chip microcomputer (U2) and an acquisition circuit connected to any end of the workpiece to be tested, the second single chip microcomputer (U2) is connected with the test host and the acquisition circuit respectively, and the second single chip microcomputer (U2) is used for acquiring the test value of the workpiece to be tested through the acquisition circuit and feeding the test value back to the receiving test host.
2. The dual-singlechip battery test circuit as claimed in claim 1, wherein the first singlechip (U1) is provided with test communication input terminals (U1_ PA9, U1_ PA10, GND) and a first signal terminal (U1_ DA1), the first singlechip (U1) is connected with a test host through the test communication input terminals (U1_ PA9, U1_ PA10, GND), and the first singlechip (U1) is connected with the power supply circuit through the first signal terminal (U1_ DA 1).
3. The dual-singlechip battery test circuit according to claim 2, wherein the first singlechip (U1) is further provided with a first power input terminal connected to an input power supply (VCC), and the first power input terminal is further connected to a filter capacitor.
4. The dual-singlechip battery test circuit of claim 2, wherein the power supply circuit comprises a first operational amplifier (U3) connected to a first singlechip (U1), a non-inverting input terminal of the first operational amplifier (U3) is connected to a first signal terminal (U1_ DA1), and an inverting input terminal of the first operational amplifier (U3) is connected to an output terminal of the first operational amplifier (U3); the output end of the first operational amplifier (U3) is connected to the anode of the workpiece to be detected, and the cathode of the workpiece to be detected is grounded through a first resistor (R1); and a first capacitor (C1) is also connected between the anode and the cathode of the workpiece to be measured.
5. The dual-chip-machine battery test circuit according to claim 4, wherein a second resistor (R2) is further connected between the non-inverting input terminal of the first operational amplifier (U3) and the first signal terminal (U1_ DA 1).
6. The dual-singlechip battery test circuit as claimed in claim 1, wherein the second singlechip (U2) is provided with a test communication output terminal (U2_ PA9, U2_ PA10, GND) and a second signal terminal (U2_ DA1), the second singlechip (U2) is connected with the test host through the test communication output terminal (U2_ PA9, U2_ PA10, GND), and the first singlechip (U1) is connected with the acquisition circuit through the second signal terminal (U2_ DA 1).
7. The dual-singlechip battery test circuit according to claim 6, wherein the second singlechip (U2) is further provided with a second power input terminal connected with an input power supply (VCC), and the second power input terminal is further connected with a filter capacitor.
8. The dual-singlechip battery test circuit according to claim 6, wherein the acquisition circuit comprises a second operational amplifier (U4), a non-inverting input terminal of the second operational amplifier (U4) is connected to a negative electrode of a workpiece to be tested through a third resistor (R3), and an output terminal of the second operational amplifier (U4) is connected to the second signal terminal (U2_ DA 1); the inverting input terminal of the second operational amplifier (U4) is grounded through a fourth resistor (R4), and the inverting input terminal of the second operational amplifier (U4) is connected to the output terminal of the second operational amplifier (U4) through a fifth resistor (R5).
9. The dual-singlechip battery test circuit according to claim 8, wherein a filter circuit is further connected to the output terminal of the second operational amplifier (U4), and the filter circuit comprises a second capacitor (C2) and a sixth resistor (R6) which are connected in parallel between the output terminal of the second operational amplifier (U4) and a power ground.
10. The dual-singlechip battery test circuit of claim 8, wherein the first singlechip (U1) and the second singlechip (U2) are STM32F103VCT 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021436497.9U CN213517468U (en) | 2020-07-20 | 2020-07-20 | Double-singlechip battery test circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202021436497.9U CN213517468U (en) | 2020-07-20 | 2020-07-20 | Double-singlechip battery test circuit |
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| CN213517468U true CN213517468U (en) | 2021-06-22 |
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| CN202021436497.9U Active CN213517468U (en) | 2020-07-20 | 2020-07-20 | Double-singlechip battery test circuit |
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