CN220553929U - Power factor correction circuit - Google Patents
Power factor correction circuit Download PDFInfo
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- CN220553929U CN220553929U CN202321910364.4U CN202321910364U CN220553929U CN 220553929 U CN220553929 U CN 220553929U CN 202321910364 U CN202321910364 U CN 202321910364U CN 220553929 U CN220553929 U CN 220553929U
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- 238000012937 correction Methods 0.000 title claims abstract description 59
- 239000003990 capacitor Substances 0.000 claims abstract description 114
- 238000006243 chemical reaction Methods 0.000 claims abstract description 24
- 230000004044 response Effects 0.000 description 12
- 230000006698 induction Effects 0.000 description 5
- 230000007423 decrease Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000013461 design Methods 0.000 description 2
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- 238000011156 evaluation Methods 0.000 description 2
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- 238000005070 sampling Methods 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000005347 demagnetization Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
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- 230000010355 oscillation Effects 0.000 description 1
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The utility model discloses a power factor correction circuit, which is electrically connected with an alternating current power supply and a resonance conversion circuit respectively, and comprises: the device comprises a first chip, a first compensation unit, a second compensation unit, a bus electrolytic capacitor, a voltage control unit, a first inductor, a voltage division unit, a first MOS tube, a current limiting unit, a rectifying unit and a parallel resistor unit. The second compensation unit is added into the power factor correction circuit and is connected after the power factor correction circuit is fully started, so that the power factor correction circuit can output voltage capable of meeting the normal working voltage value of the later-stage circuit during the fully-loaded starting.
Description
Technical Field
The utility model relates to the technical field of circuits, in particular to a power factor correction circuit.
Background
The resonant conversion circuit has more application in high-power supply products due to the characteristics of high reliability, good EMI performance and the like. Typically, the resonant conversion circuit is used together with the pfc circuit, and forms a two-stage architecture of the resonant conversion circuit and the pfc circuit. The power factor correction circuit can be used as a front stage to provide a stable input voltage for a rear-stage resonant conversion circuit, so that the power supply can work in a wider input voltage range; meanwhile, the power factor correction circuit can enable the power supply to obtain higher power factor and lower harmonic distortion.
However, when the power output end of the existing power factor correction circuit is in heavy-load operation, the bus electrolytic capacitor is pulled out of large current, so that the voltage on the bus electrolytic capacitor is pulled down more in a period of time, the voltage output by the power factor correction circuit is reduced, and the resonant conversion circuit at the later stage cannot work normally due to the reduction of the input voltage.
Accordingly, the prior art is to be improved and developed.
Disclosure of Invention
The utility model aims to solve the technical problems that the power factor correction circuit aims to solve the problems that the voltage output by the power factor correction circuit is reduced when the power output end of the power factor correction circuit works in heavy load.
The technical scheme adopted for solving the technical problems is as follows: there is provided a power factor correction circuit electrically connected to an ac power source and a resonant conversion circuit, respectively, the power factor correction circuit comprising: the device comprises a first chip, a first compensation unit, a second compensation unit, a bus electrolytic capacitor, a voltage control unit, a first inductor, a voltage division unit, a first MOS tube, a current limiting unit, a rectifying unit and a parallel resistor unit; the 1 pin of the first chip is connected with the bus electrolytic capacitor through the voltage control unit and is used for receiving the voltage of the bus electrolytic capacitor, wherein the voltage of the bus electrolytic capacitor is the output voltage of the power factor correction circuit; the 2 pin of the first chip is connected with the first compensation unit; the 3 pins of the first chip are connected with the alternating current power supply through the voltage dividing unit and the rectifying unit and are used for inputting a sine reference signal of the power factor correction circuit into the first chip; the 4 pins of the first chip are connected with the first MOS tube through the parallel resistor unit; the 5 pin of the first chip is connected with the first inductor; the 6 pins of the first chip are grounded; the pin 7 of the first chip is connected with the first MOS tube and is used for providing grid driving voltage for the first MOS tube; the 8 pins of the first chip are connected with the alternating current power supply through the current limiting unit and the rectifying unit and used for providing starting current for the first chip; the second compensation unit is connected with the first compensation unit, and is connected into the power factor correction circuit after the power factor correction circuit is fully loaded and started.
In a further arrangement of the utility model, the first chip is a chip of model L6562.
The first compensation unit of the present utility model further comprises: a first capacitor, a second capacitor and a first resistor; one end of the first capacitor is connected with the 1 pin of the first chip, and the other end of the first capacitor is connected with the 2 pin of the first chip; one end of the second capacitor is connected with the other end of the first resistor, and the other end of the second capacitor is connected with the 2 pin of the first chip; one end of the first resistor is connected with one end of the first capacitor.
The second compensation unit of the present utility model further comprises: an N-channel enhancement transistor, a third capacitor, a fourth capacitor, a fifth diode, a second resistor, a third resistor, a fourth resistor and a fifth resistor; one end of the third capacitor is connected with the other end of the second resistor, and the other end of the third capacitor is connected with the other end of the second capacitor; one end of the second resistor is connected with the other end of the third resistor and the drain electrode of the N-channel enhancement transistor respectively; one end of the third resistor is connected with one end of the first resistor and the source electrode of the N-channel enhancement transistor respectively; the grid electrode of the N channel enhancement type transistor is respectively connected with the other end of the fourth capacitor, the other end of the fourth resistor and one end of the fifth resistor; one end of the fourth capacitor is connected with one end of the fourth resistor; one end of the fifth resistor is connected with the other end of the fourth resistor, and the other end of the fifth resistor is connected with the other end of the fifth diode; one end of the fifth diode is connected with the other end of the fifth capacitor.
The rectifying unit of the present utility model further includes: a first diode, a second diode, a third diode, and a fourth diode; one end of the first diode is connected with the other end of the second diode and the alternating current power supply respectively, and the other end of the first diode is connected with the other end of the third diode; one end of the second diode is connected with one end of the fourth diode; the other end of the fourth diode is connected with one end of the third diode and the alternating current power supply respectively.
The utility model further provides that the voltage dividing unit comprises: a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, and a tenth resistor; one end of the sixth resistor is connected with the other end of the first diode and the other end of the third diode respectively, and the other end of the sixth resistor is connected with one end of the seventh resistor; the other end of the seventh resistor is connected with one end of the eighth resistor; the other end of the eighth resistor is connected with one end of the ninth resistor; the other end of the ninth resistor is connected with one end of the tenth resistor and the 3 rd pin of the first chip respectively; the other end of the tenth resistor is connected with one end of the fourth capacitor.
Further, the current limiting unit includes: eleventh, twelfth, and thirteenth resistances; one end of the eleventh resistor is connected with the other end of the first diode and the other end of the third diode respectively, and the other end of the eleventh resistor is connected with one end of the twelfth resistor; the other end of the twelfth resistor is connected with one end of the thirteenth resistor; the other end of the thirteenth resistor is connected with the 8 pins of the first chip.
Further, the voltage control unit of the present utility model includes: fourteenth, fifteenth, sixteenth, seventeenth and eighteenth resistors; one end of the fourteenth resistor is connected with the first inductor, and the other end of the fourteenth resistor is connected with one end of the first capacitor, the 1 pin of the first chip and the other end of the fifteenth resistor respectively; one end of the fifteenth resistor is connected with the other end of the sixteenth resistor; one end of the sixteenth resistor is connected with the other end of the seventeenth resistor; one end of the seventeenth resistor is connected with the other end of the eighteenth resistor; one end of the eighteenth resistor is connected with one end of the busbar electrolytic capacitor.
In a further arrangement of the utility model, the first inductance is an inductance of model EF 25.
The beneficial effects are that: the second compensation unit is added into the power factor correction circuit and is connected after the power factor correction circuit is fully started, so that the power factor correction circuit can output voltage capable of meeting the normal working voltage value of the later-stage circuit during the fully-loaded starting.
Drawings
Fig. 1 is a schematic block diagram of a power factor correction circuit of the present utility model when connected to a circuit.
Fig. 2 is a schematic block diagram of the power factor correction circuit of fig. 1.
Fig. 3 is a specific circuit configuration diagram of the pfc circuit shown in fig. 1.
Reference numerals illustrate: 100. an alternating current power supply; 200. a power factor correction circuit; 300. a resonant conversion circuit; 201. a first compensation unit; 202. a second compensation unit; 203. a voltage control unit; 204. a voltage dividing unit; 205. a current limiting unit; 206. a rectifying unit; 207. a parallel resistor unit; u1, a first chip; c0, a bus electrolytic capacitor; c1, a first capacitor; c2, a second capacitor; c3, a third capacitor; c4, a fourth capacitor; c5, a fifth capacitor; c6, a sixth capacitor; c7, a seventh capacitor; r1, a first resistor; r2, a second resistor; r3, a third resistor; r4, a fourth resistor; r5, a fifth resistor; r6, a sixth resistor; r7, a seventh resistor; r8, eighth resistor; r9, ninth resistor; r10, tenth resistor; r11, eleventh resistor; r12, twelfth resistor; r13, thirteenth resistance; r14, fourteenth resistor; r15, fifteenth resistor; r16, sixteenth resistance; r17, seventeenth resistance; r18, eighteenth resistor; r19, nineteenth resistor; r20, twentieth resistance; r21, twenty-first resistance; r22, a twenty-second resistor; r23, twenty-third resistor; r24, twenty-fourth resistor; d1, a first diode; d2, a second diode; d3, a third diode; d4, a fourth diode; d5, a fifth diode; d6, a sixth diode; d7, a seventh diode; v1, a first MOS tube; s1, an N-channel enhancement transistor; q1, a first triode; q2, second triode.
Detailed Description
It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other. The utility model will be described in detail below with reference to the drawings in connection with embodiments.
In order to make the objects, technical solutions and advantages of the present utility model more clear and clear, the present utility model will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the utility model.
Resonant conversion circuits (LLC) are commonly used in conjunction with power factor correction circuits (PFC) to form a two-stage architecture of the PFC + resonant conversion circuit. The power factor correction circuit can be used as a front stage to provide a stable input voltage for a resonance conversion circuit of a rear stage, so that the power supply can work in a wider input voltage range; meanwhile, the power factor correction circuit can enable the power supply to obtain higher power factor and lower harmonic distortion. However, when the power output terminal is connected to the heavy load, the busbar electrolytic capacitor C0 receives a larger current, so that the output voltage drops more in a period of time. This may cause the input voltage of the subsequent resonant conversion circuit to decrease, thereby causing the resonant conversion circuit to fail to operate normally. To solve this problem, it is necessary to ensure that the input voltage supplied from the power factor correction circuit of the preceding stage to the resonant conversion circuit of the following stage is maintained at a level or higher
In order to solve the problems of the prior art, the present utility model provides a power factor correction circuit, and the method is described below with reference to specific embodiments.
As shown in fig. 1, 2 and 3, the embodiment of the present utility model provides a power factor correction circuit, which is electrically connected to an ac power source 100 and a resonant conversion circuit 300, respectively. The power factor correction circuit 200 includes: the device comprises a first chip U1, a first compensation unit 201, a second compensation unit 202, a busbar electrolytic capacitor C0, a voltage control unit 203, a first inductor L1, a voltage division unit 204, a first MOS tube V1, a current limiting unit 205, a rectification unit 206 and a parallel resistor unit 207. In the embodiment of the present application, the first chip U1 is a chip with a model number L6562.
As shown in fig. 2 and fig. 3, the first chip U1 is a chip with eight pins, and pin 1 of the first chip U1 is an input terminal of an error amplifier, which may specifically be an input terminal of the error amplifier. The pin 1 of the first chip U1 is connected to the busbar electrolytic capacitor C0 through the voltage control unit 203, and is configured to receive the voltage of the busbar electrolytic capacitor C0, where the voltage of the busbar electrolytic capacitor C0 is the output voltage of the pfc circuit 200. The bus electrolytic capacitor C0 refers to an electrolytic capacitor provided on the power factor correction circuit 200.
The 2 pin of the first chip U1 is an output end of the error amplifier, and the 2 pin of the first chip U1 is connected with the first compensation unit 201.
Specifically, as shown in fig. 3, the first compensation unit 201 includes: a first capacitor C1, a second capacitor C2 and a first resistor R1; one end of the first capacitor C1 is connected with the 1 pin of the first chip U1, and the other end of the first capacitor C1 is connected with the 2 pin of the first chip U1; one end of the second capacitor C2 is connected with the other end of the first resistor R1, and the other end of the second capacitor C2 is connected with the 2 pin of the first chip U1; one end of the first resistor R1 is connected to one end of the first capacitor C1. In this way, a compensation unit network, that is, the first compensation unit 201, is formed between the 1 pin and the 2 pin of the first chip U1, so as to increase the phase margin and the gain margin of the whole circuit, so that the system is less prone to oscillation or instability, and the effects of realizing the stability of the voltage control loop and ensuring high power factor and low harmonic distortion are achieved.
Specifically, the voltage control unit 203 includes: a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, and an eighteenth resistor R18; one end of the fourteenth resistor R14 is connected to the 4 pin of the first inductor L1, and the other end of the fourteenth resistor R14 is connected to one end of the first capacitor C1, the 1 pin of the first chip U1, and the other end of the fifteenth resistor R15, respectively; one end of the fifteenth resistor R15 is connected with the other end of the sixteenth resistor R16; one end of the sixteenth resistor R16 is connected with the other end of the seventeenth resistor R17; one end of the seventeenth resistor R17 is connected to the other end of the eighteenth resistor R18; one end of the eighteenth resistor R18 is connected to one end of the busbar electrolytic capacitor C0. In this way, the loop of the voltage control unit 203, which is composed of the fourteenth resistor R14, the fifteenth resistor R15, the sixteenth resistor R16, the seventeenth resistor R17 and the eighteenth resistor R18, transmits the voltage signal on the busbar electrolytic capacitor C0 to the first chip U1 through the 1 pin of the first chip U1, so as to monitor the voltage of the busbar electrolytic capacitor C0, that is, the output voltage of the pfc circuit 200, and compare with the preset reference voltage to set the voltage on the busbar electrolytic capacitor C0.
Further, the 3 pin of the first chip U1 is a multiplier input terminal, and the 3 pin of the first chip U1 is connected to the ac power supply 100 through the voltage dividing unit 204 and the rectifying unit 206, and is used for inputting the sinusoidal reference signal of the pfc circuit 200 into the first chip U1.
Specifically, the rectifying unit 206 includes: a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4; one end of the first diode D1 is connected to the other end of the second diode D2 and the ac power supply 100, and the other end of the first diode D1 is connected to the other end of the third diode D3; one end of the second diode D2 is connected with one end of the fourth diode D4; the other end of the fourth diode D4 is connected to one end of the third diode D3 and the ac power supply 100, respectively.
The voltage dividing unit 204 includes: a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, and a tenth resistor R10; one end of the sixth resistor R6 is respectively connected with the other end of the first diode D1 and the other end of the third diode D3, and the other end of the sixth resistor R6 is connected with one end of the seventh resistor R7; the other end of the seventh resistor R7 is connected with one end of the eighth resistor R8; the other end of the eighth resistor R8 is connected with one end of the ninth resistor R9; the other end of the ninth resistor R9 is respectively connected with one end of the tenth resistor R10 and the 3 rd pin of the first chip U1; the other end of the tenth resistor R10 is connected to the second compensation unit 202 and the busbar electrolytic capacitor C0, respectively.
The ac power supply 100 outputs ac power, which is changed into pulsating dc power by a bridge rectifier circuit comprising diodes (the first diode D1, the second diode D2, the third diode D3 and the fourth diode D4) in the rectifier unit 206, and is connected to the 3 pin of the first chip U1 by a voltage dividing unit 204 (resistor voltage divider) comprising the sixth resistor R6, the seventh resistor R7, the eighth resistor R8, the ninth resistor R9 and the tenth resistor R10, so as to provide a sinusoidal reference signal for the current loop of the pfc circuit 200, thereby achieving the function of performing power factor correction according to the sinusoidal reference signal.
Further, the 4 pin of the first chip U1 is a positive input end of the internal PWM comparator, and the 4 pin of the first chip U1 is connected with the first MOS transistor V1 through the parallel resistor unit 207.
Specifically, the parallel resistance unit 207 is connected in parallel with a plurality of resistors, and the parallel resistance unit 207 includes: nineteenth resistor R19, twentieth resistor R20, twenty-first resistor R21, twenty-second resistor R22, twenty-third resistor R23, and twenty-fourth resistor R24. In this way, the current flowing when the first MOS transistor V1 is turned on may generate a voltage signal at two ends of the nineteenth resistor R19, the twentieth resistor R20, the twenty first resistor R21, the twenty second resistor R22, the twenty third resistor R23, and the twenty fourth resistor R24, and apply the voltage signal to the 4 pins of the first chip U1, and the internal sinusoidal reference value generated by the multiplier inside the first chip U1, that is, the sinusoidal reference signal, is compared to determine the current turn-off value of the first MOS transistor V1.
Further, the 5 pin of the first chip U1 is a demagnetizing induction input end of the first inductor L1, and the 5 pin of the first chip U1 is connected with the first inductor L1. The first inductor L1 may be a boost inductor, and specifically may be an inductor with a model number EF 25.
The 5 pin of the first chip U1 is configured to monitor the current in the first inductor L1, and when the current in the first inductor L1 changes, the magnetic field generated in the first inductor L1 also changes. When the current decreases or breaks, the magnetic field in the first inductor L1 gradually decreases or disappears, and a demagnetizing induction is formed. In this way, when the first inductor L1 performs demagnetizing induction, the magnetic field changes, and an induced electromotive force is generated. The rate of change of this induced electromotive force determines the waveform characteristics of the generated signal. In general, when the first inductor L1 generates demagnetizing induction, the induced electromotive force generates a negative side signal with a fast falling edge.
When the current in the first inductor L1 decreases, a negative side signal generated by demagnetization induction is input into the first chip U1 to prompt the first MOS transistor V1 to be triggered and turned on.
Further, the 6 pins of the first chip U1 are ground pins, and the 6 pins of the first chip U1 are grounded to provide a loop for the signal current and the gate driving current inside the first chip U1.
Further, pin 7 of the first chip U1 is a gate driver output end, and pin 7 of the first chip U1 is connected to the first MOS transistor V1, and is configured to provide a gate driving voltage for the first MOS transistor V1. Thus, when the negative side signal is received by the pin 5 of the first chip U1, the pin 7 of the first chip U1 outputs the gate driving voltage for the first MOS transistor V1, so as to start the first MOS transistor V1.
Further, the 8 pins of the first chip U1 are chip power pins, and the 8 pins of the first chip U1 are connected with the ac power supply 100 through the current limiting unit 205 and the rectifying unit 206, so as to provide a starting current for the first chip U1.
Specifically, the current limiting unit 205 includes: an eleventh resistor R11, a twelfth resistor R12, and a thirteenth resistor R13; one end of the eleventh resistor R11 is connected to the other end of the first diode D1 and the other end of the third diode D3, respectively, and the other end of the eleventh resistor R11 is connected to one end of the twelfth resistor R12; the other end of the twelfth resistor R12 is connected to one end of the thirteenth resistor R13.
The ac power output by the ac power supply 100 is changed into pulsating dc power by a bridge rectifier circuit formed by diodes (the first diode D1, the second diode D2, the third diode D3 and the fourth diode D4) in the rectifier unit 206, and then is subjected to current limiting by the current limiting unit 205 (the eleventh resistor R11, the twelfth resistor R12 and the thirteenth resistor R13), and is filtered by the sixth capacitor C6, and then is connected to the 8 pin of the first chip U1, so as to provide current for the first chip U1. After the first chip U1 is started, the auxiliary winding voltage of the first inductor L1 is reduced through the seventh capacitor C7, and is rectified through the sixth diode D6 and the seventh diode D7 to supply power to the 8 pin of the first chip U1.
The present power factor correction circuit 200 composed of a single compensation circuit is operated for a period of time, and then the voltage of the busbar electrolytic capacitor C0 in the circuit is pulled down for a period of time, which is caused by untimely feedback of the single compensation of the first compensation unit 201.
The second compensation unit 203 is disposed in the pfc circuit 200, the second compensation unit 202 is connected to the first compensation unit 201, the second compensation unit 202 is not connected to the pfc circuit 200 when the pfc circuit 200 is fully started, and the second compensation unit 202 is connected to the pfc circuit 200 after the pfc circuit 200 is fully started.
Specifically, the second compensation unit 203 includes: an N-channel enhancement transistor S1, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a fifth diode D5, a second resistor R2, a third resistor R3, a fourth resistor R4, and a fifth resistor R5; one end of the third capacitor C3 is connected with the other end of the second resistor R2, and the other end of the third capacitor C3 is connected with the other end of the second capacitor C2; one end of the second resistor R2 is connected to the other end of the third resistor R3 and the drain electrode of the N-channel enhancement transistor S1, respectively; one end of the third resistor R3 is connected to one end of the first resistor R1 and the source of the N-channel enhancement transistor S1, respectively; the grid electrode of the N-channel enhancement transistor S1 is respectively connected with the other end of the fourth capacitor C4, the other end of the fourth resistor R4 and one end of the fifth resistor R5; one end of the fourth capacitor C4 is connected to the other end of the tenth resistor R10 and one end of the fourth resistor R4, respectively; one end of the fifth resistor R5 is connected with the other end of the fourth resistor R4, and the other end of the fifth resistor R5 is connected with the other end of the fifth diode D5; one end of the fifth diode D5 is connected to the other end of the fifth capacitor C5.
In a specific operation, when the ac power supply 100 is initially energized, the power factor correction circuit 200 does not start to operate, the midpoint of the half-bridge (the first triode Q1 and the second triode Q2) is not voltage, the first MOS tube V1 is in a non-conducting state, and the third resistor R3 is set to be a larger resistance value, so that in the second compensation unit 202, a circuit formed by the third capacitor C3, the second resistor R2 and the third resistor R3 is equivalent to an open circuit, the second compensation unit 202 is not connected into the circuit, and in the initial stage, the first compensation unit 201 compensates the power factor correction circuit 200, and the response speed is faster. After the pfc circuit 200 is fully loaded and started, the half-bridge is in a working state, the fifth capacitor C5 is sampling and reducing the voltage from the midpoint of the half-bridge, and the fifth capacitor C5 is rectified by the fifth diode D5, the fifth resistor R5 and the fourth resistor R4 are voltage-dividing and current-limiting, and then charge the fourth capacitor C4, and when the voltage on the fourth capacitor C4 reaches the turn-on voltage of the N-channel enhancement transistor S1, the third resistor R3 is turned on and short-circuited to access the second compensation unit 202. In this way, the second path compensation is connected to the pfc circuit 200 to stabilize the output voltage of the pfc circuit 200, so that the resonant conversion circuit 300 connected in the subsequent stage can receive a normal operating voltage, and the resonant conversion circuit 300 can operate normally.
The following is a detailed description in connection with experimental data.
The two-stage circuit formed by the power factor correction circuit 200+the resonant conversion circuit 300 outputs a constant voltage source voltage of 24V, the maximum output current is 6.25A, the AC power source 100 is AC198V, the bus voltage is set to 400V during a test experiment, and an oscilloscope is used to test the voltage of the bus electrolytic capacitor C0.
When the second compensation unit 202 is not connected to the pfc circuit 200, the first resistor R1 is set to 4.7kΩ, the first capacitor C1 is set to 10NF, and the second capacitor C2 is set to 680NF. When the load is full, the oscilloscope detects that the voltage of the busbar electrolytic capacitor C0 is reduced to about 350V at the lowest, so that the voltage output by the power factor correction circuit 200 to the resonance conversion circuit 300 is too low to work normally. Therefore, when the output load needs to be reduced to 5A and then the power is turned on, the output side of the power factor correction circuit 200 can work normally, the measured power factor is more than 0.95, and the total harmonic is less than 15%.
When the first resistor R1 is 68kΩ, the first capacitor C1 is 10NF, and the second capacitor C2 is 22 NF. The voltage waveform of the busbar electrolytic capacitor C0 is tested by using an oscilloscope, the lowest busbar voltage drops to about 367V when the voltage is actually measured to be full, the resonant conversion circuit 300 can work normally, but the input parameters become worse, the measured power factor is less than 0.9, and the total harmonic is more than 20%, so that the design parameters do not meet the common examination requirements.
The response time of the first capacitor C1 is calculated by different configurations of the two compensation networks when only the first compensation unit 201 is connected, and the first capacitor C1 is ignored for the sake of easy calculation of the response time of the compensation network because the capacitance value of the first capacitor C1 is equal. According to an RC circuit time constant calculation formula t=rc, when the first resistor R1 is 4.7kΩ and the second capacitor C2 is 680NF, the response time t= 0.003196 seconds of the first compensation unit 201 of the compensation network; when the first resistor R1 is 68kΩ and the second capacitor C2 is 22NF, the first compensation unit 201 has a response time t= 0.001496 seconds. Therefore, it is obtained that when the pfc circuit 200 is only connected to the first compensation unit 201, the response time of the compensation network is fast, and the compensation network can work normally when the pfc circuit is fully loaded and started, but the input parameters are poor, so that the input parameters do not meet the normal examination requirements; when the response time of the compensation network is reduced, the input parameters are good, but the compensation network cannot work when full load is started. Therefore, the power factor correction circuit 200 with a single compensation network has a fast response speed of the compensation network when the full load is started, and the bus voltage is not reduced too much, so that the resonant conversion circuit 300 can work normally; and the response speed of the compensation network is reduced after the operation, so that the parameters meet the requirements. Obviously, this requirement is paradoxical, and the power factor correction circuit 200 of a single compensation network cannot meet the design requirement.
Therefore, the present utility model further provides access to the second compensation unit 202 in the pfc circuit 200. In the first compensation unit 201, the first resistor R1 is 68kΩ, the first capacitor C1 is 10NF, and the second capacitor C2 is 22NF; in the second compensation unit 202, the third capacitance C3 is 1uF, the second resistance R2 is 10kΩ, and the third resistance R3 is 680kΩ. And the second compensation unit 202 is not connected when the second compensation unit 202 is started up in full load, and is connected to the second compensation unit 202 to the power factor correction circuit 200 when the second compensation unit 202 works normally after the full load is started up.
In a specific operation, when the ac power supply 100 is initially powered on, the pfc circuit 200 does not start to operate, the midpoint of the half-bridge is not voltage-free, the first MOS transistor V1 is not turned on, and because the third resistor R3 has a larger resistance value, in this way, in the second compensation unit 202, the circuit formed by the third capacitor C3, the second resistor R2 and the third resistor R3 is equivalent to an open circuit, the second compensation unit 202 is not connected to the circuit, at this time, the network response compensated by the first compensation unit 201 is faster, the pfc circuit 200 can maintain an output of more than 360V, and in the initial stage, the first compensation unit 201 compensates the pfc circuit 200 with a faster response speed, and can meet the voltage requirement of the resonant conversion circuit 300. And after full-load starting, the half-bridge is in a working state, the fifth capacitor C5 is sampling from the midpoint of the half-bridge and reducing the voltage, the fifth diode D5 is used for rectifying, the fifth resistor R5 and the fourth resistor R4 are used for dividing and limiting the voltage and then charging the fourth capacitor C4, and when the voltage on the fourth capacitor C4 reaches the conduction voltage of the N-channel enhancement transistor S1, the third resistor R3 is turned on and short-circuited to be connected to the second compensation unit 202. At this time, the response time T' =0.01 seconds (the third capacitor c3×the second resistor R2, and the first resistor R1, the first capacitor C1, and the second capacitor C2 are omitted for the convenience of calculation), so as to meet the evaluation requirement of the input parameter, and the access time of the second compensation unit 202 may be finely adjusted by adjusting the parameters of the fourth resistor R4, the fifth resistor R5, and the fourth capacitor C4, so as to obtain an effect that the voltage output by the pfc circuit 200 during full-load startup meets the voltage of the normal operation of the resonant conversion circuit 300 and meets the evaluation requirement of the input parameter.
In summary, the second compensation unit connected to the first compensation unit is added to the pfc circuit, and the second compensation unit is connected to the pfc circuit after the pfc circuit is fully started, so as to compensate the pfc circuit, so that the pfc circuit can output a voltage capable of meeting the normal operating voltage value of the later stage circuit during the full-load starting.
It is to be understood that the utility model is not limited in its application to the examples described above, but is capable of modification and variation in light of the above teachings by those skilled in the art, and that all such modifications and variations are intended to be included within the scope of the appended claims.
Claims (9)
1. A power factor correction circuit, wherein the power factor correction circuit is electrically connected with an ac power source and a resonant conversion circuit, respectively, the power factor correction circuit comprising: the device comprises a first chip, a first compensation unit, a second compensation unit, a bus electrolytic capacitor, a voltage control unit, a first inductor, a voltage division unit, a first MOS tube, a current limiting unit, a rectifying unit and a parallel resistor unit;
the 1 pin of the first chip is connected with the bus electrolytic capacitor through the voltage control unit and is used for receiving the voltage of the bus electrolytic capacitor, wherein the voltage of the bus electrolytic capacitor is the output voltage of the power factor correction circuit;
the 2 pin of the first chip is connected with the first compensation unit;
the 3 pins of the first chip are connected with the alternating current power supply through the voltage dividing unit and the rectifying unit and are used for inputting a sine reference signal of the power factor correction circuit into the first chip;
the 4 pins of the first chip are connected with the first MOS tube through the parallel resistor unit;
the 5 pin of the first chip is connected with the first inductor;
the 6 pins of the first chip are grounded;
the pin 7 of the first chip is connected with the first MOS tube and is used for providing grid driving voltage for the first MOS tube;
the 8 pins of the first chip are connected with the alternating current power supply through the current limiting unit and the rectifying unit and used for providing starting current for the first chip;
the second compensation unit is connected with the first compensation unit, and is connected into the power factor correction circuit after the power factor correction circuit is fully loaded and started.
2. The power factor correction circuit of claim 1, wherein the first chip is a model L6562 chip.
3. The power factor correction circuit of claim 2, wherein the first compensation unit comprises: a first capacitor, a second capacitor and a first resistor;
one end of the first capacitor is connected with the 1 pin of the first chip, and the other end of the first capacitor is connected with the 2 pin of the first chip;
one end of the second capacitor is connected with the other end of the first resistor, and the other end of the second capacitor is connected with the 2 pin of the first chip;
one end of the first resistor is connected with one end of the first capacitor.
4. A power factor correction circuit as claimed in claim 3, wherein the second compensation unit comprises: an N-channel enhancement transistor, a third capacitor, a fourth capacitor, a fifth diode, a second resistor, a third resistor, a fourth resistor and a fifth resistor;
one end of the third capacitor is connected with the other end of the second resistor, and the other end of the third capacitor is connected with the other end of the second capacitor;
one end of the second resistor is connected with the other end of the third resistor and the drain electrode of the N-channel enhancement transistor respectively;
one end of the third resistor is connected with one end of the first resistor and the source electrode of the N-channel enhancement transistor respectively;
the grid electrode of the N channel enhancement type transistor is respectively connected with the other end of the fourth capacitor, the other end of the fourth resistor and one end of the fifth resistor;
one end of the fourth capacitor is connected with one end of the fourth resistor;
one end of the fifth resistor is connected with the other end of the fourth resistor, and the other end of the fifth resistor is connected with the other end of the fifth diode;
one end of the fifth diode is connected with the other end of the fifth capacitor.
5. The power factor correction circuit of claim 4, wherein the rectifying unit comprises: a first diode, a second diode, a third diode, and a fourth diode;
one end of the first diode is connected with the other end of the second diode and the alternating current power supply respectively, and the other end of the first diode is connected with the other end of the third diode;
one end of the second diode is connected with one end of the fourth diode;
the other end of the fourth diode is connected with one end of the third diode and the alternating current power supply respectively.
6. The power factor correction circuit of claim 5, wherein the voltage dividing unit comprises: a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, and a tenth resistor;
one end of the sixth resistor is connected with the other end of the first diode and the other end of the third diode respectively, and the other end of the sixth resistor is connected with one end of the seventh resistor;
the other end of the seventh resistor is connected with one end of the eighth resistor;
the other end of the eighth resistor is connected with one end of the ninth resistor;
the other end of the ninth resistor is connected with one end of the tenth resistor and the 3 rd pin of the first chip respectively;
the other end of the tenth resistor is connected with one end of the fourth capacitor.
7. The power factor correction circuit of claim 6, wherein the current limiting unit comprises: eleventh, twelfth, and thirteenth resistances;
one end of the eleventh resistor is connected with the other end of the first diode and the other end of the third diode respectively, and the other end of the eleventh resistor is connected with one end of the twelfth resistor;
the other end of the twelfth resistor is connected with one end of the thirteenth resistor;
the other end of the thirteenth resistor is connected with the 8 pins of the first chip.
8. The power factor correction circuit of claim 7, wherein the voltage control unit comprises: fourteenth, fifteenth, sixteenth, seventeenth and eighteenth resistors;
one end of the fourteenth resistor is connected with the first inductor, and the other end of the fourteenth resistor is connected with one end of the first capacitor, the 1 pin of the first chip and the other end of the fifteenth resistor respectively;
one end of the fifteenth resistor is connected with the other end of the sixteenth resistor;
one end of the sixteenth resistor is connected with the other end of the seventeenth resistor;
one end of the seventeenth resistor is connected with the other end of the eighteenth resistor;
one end of the eighteenth resistor is connected with one end of the busbar electrolytic capacitor.
9. The power factor correction circuit of claim 8, wherein the first inductor is an inductor of model EF 25.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321910364.4U CN220553929U (en) | 2023-07-19 | 2023-07-19 | Power factor correction circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321910364.4U CN220553929U (en) | 2023-07-19 | 2023-07-19 | Power factor correction circuit |
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| CN220553929U true CN220553929U (en) | 2024-03-01 |
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