CN220552944U - Integrated circuit testing device - Google Patents

Abstract

An integrated circuit testing device. The integrated circuit testing device includes: main test board and sub test board. The main test board comprises a connecting unit and a plurality of signal input ends. The connection unit comprises a plurality of joints. The signal input ends are electrically connected with the contacts. The sub-test board comprises a plurality of pins. And the pins are connected with a plurality of signal ports of the chip on the sub-test board. When the sub-test board is connected with the main test board, the pins are correspondingly connected with the contacts.

Description

Integrated circuit testing device

Technical Field

The present utility model relates to the field of semiconductors, and more particularly, to an integrated circuit testing apparatus.

Background

In the prior art, the pin count or the signals that the pins need to receive are different for each integrated circuit product. Therefore, when a reliability bias test is required, a new test circuit board needs to be soldered manually to each integrated circuit product for voltage testing. However, the work efficiency performed manually is low and there is a problem in that welding errors are liable to occur.

Disclosure of Invention

In view of the above, the present application provides an integrated circuit testing device to solve the above-mentioned problems.

According to one embodiment of the present application, an integrated circuit testing apparatus is provided. The integrated circuit testing device includes: main test board and sub test board. The main test board comprises a connecting unit and a plurality of signal input ends. The connection unit comprises a plurality of joints. The signal input ends are electrically connected with the contacts. The sub-test board comprises a plurality of pins. And the pins are connected with a plurality of signal ports of the chip on the sub-test board. When the sub-test board is connected with the main test board, the pins are correspondingly connected with the contacts.

According to an embodiment of the present application, the sub-test board further includes a patterned conductive layer connecting the plurality of pins to the plurality of signal ports of the chip.

According to one embodiment of the application, the chip is attached to the sub-test board.

According to an embodiment of the application, the sub-test board further comprises a chip holder, and the chip is embedded in the chip holder to be arranged on the sub-test board.

According to an embodiment of the present application, the connection unit includes a socket, and a plurality of pins of the socket are connected with the plurality of contacts. The socket receives the sub-test board when the sub-test board is connected with the main test board.

According to an embodiment of the present application, the connection unit includes a plurality of pin holes. And when the sub test board is connected with the main test board, the pin holes are connected with the pins.

According to an embodiment of the present application, the main test plate comprises a plurality of the connection units. The main test board also comprises a patterned conductive layer, wherein the patterned conductive layer is connected with the corresponding contact point in each connecting unit.

According to an embodiment of the present application, the main test board includes a plurality of connection units, each connection unit further includes a plurality of jumper holes, and the plurality of jumper holes are electrically connected with the plurality of contacts.

In the integrated circuit testing device provided by the application, the connection of convenience is realized through the detachable main test board and the sub test board, the troubleshooting of the whole main test board and the sub test board is more facilitated, and the independent sub test board is favorable for timely separating from the main test board when abnormality occurs, so that the test quality is improved.

Drawings

The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate the application and, together with the description, do not limit the application. In the drawings:

FIG. 1 illustrates a schematic diagram of an integrated circuit testing device according to one embodiment of the present application.

FIG. 2 illustrates a schematic diagram of an integrated circuit testing device according to another embodiment of the present application.

FIG. 3 illustrates a schematic diagram of an integrated circuit testing device according to another embodiment of the present application.

FIG. 4 illustrates a schematic diagram of an integrated circuit testing device according to another embodiment of the present application.

Detailed Description

The following disclosure provides various embodiments or examples that can be used to implement the various features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. It is to be understood that these descriptions are merely exemplary and are not intended to limit the present disclosure. For example, in the following description, forming a first feature on or over a second feature may include certain embodiments in which the first and second features are in direct contact with each other; and may include embodiments in which additional components are formed between the first and second features such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. Such reuse is for brevity and clarity purposes and does not itself represent a relationship between the different embodiments and/or configurations discussed.

Moreover, spatially relative terms, such as "under," "below," "lower," "upper," and the like, may be used herein to facilitate a description of the relationship between one element or feature to another element or feature as illustrated in the figures. These spatially relative terms are intended to encompass a variety of different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be placed in other orientations (e.g., rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein interpreted accordingly.

Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the application are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. However, any numerical value inherently contains certain standard deviations found in their respective testing measurements. As used herein, "about" generally means that the actual value is within plus or minus 10%, 5%, 1% or 0.5% of a particular value or range. Alternatively, the term "about" means that the actual value falls within an acceptable standard error of the average value, depending on the consideration of those ordinarily skilled in the art to which the present application pertains. It is to be understood that all ranges, amounts, values, and percentages used herein (e.g., to describe amounts of materials, lengths of time, temperatures, operating conditions, ratios of amounts, and the like) are modified by the term "about" unless otherwise specifically indicated. Accordingly, unless indicated to the contrary, the numerical parameters set forth in the present specification and attached claims are approximations that may vary depending upon the desired properties. At least these numerical parameters should be construed as the number of significant digits and by applying ordinary rounding techniques. Herein, a numerical range is expressed as from one end point to another end point or between two end points; unless otherwise indicated, all numerical ranges recited herein include endpoints.

Fig. 1 illustrates a schematic diagram of an integrated circuit testing apparatus 1 according to an embodiment of the present application. In certain embodiments, the integrated circuit testing device 1 is configured to bias test an integrated circuit chip. In some embodiments, integrated circuit testing device 1 includes a main test board M1 and a sub-test board Z1. In some embodiments, the sub-test panel Z1 is removably connected to the main test panel M1. In some embodiments, the main test board M1 includes a connection unit 110 (identified by a dashed box in the figure) and a signal input 120. The main test board M1 includes a plurality of connection units 110 to facilitate batch testing of integrated circuit chips. The main test board M1 includes a plurality of signal input terminals 120 to facilitate the simultaneous access of a plurality of input signals to the integrated circuit chip for testing, wherein the plurality of connection units 110 are arranged in a matrix on the main test board M1. In some embodiments, the signal input terminals 120 may receive the bias signal VDD, the ground GND, the clock signal CLK and the adjustment signal Trim from external signal sources, respectively. In other embodiments, the signal input 120 may also accept other desired signals from an external signal source.

In some embodiments, the connection unit 110 includes a plurality of contacts D110, wherein each signal input terminal 120 is electrically connected to a corresponding contact D110 in a row of connection units 110 closest to the signal input terminal 120, such that the connection units 110 receive an input signal from the signal input terminal 120 through the contact D110. In some embodiments, the connection between the signal input terminal 120 and the contact D110 may be through a patterned conductive layer (shown in dotted lines) previously provided on the main test board M1.

In some embodiments, the sub-test board Z1 includes a number of pins 210. In some embodiments, the number of pins 210 corresponds to the number of contacts D110 on the connection unit 110. In some embodiments, each pin 210 is connected (as shown in phantom) with a signal port of a chip C on the sub-test board Z1. In some embodiments, the chip C may be attached to the sub-test board Z1 by an SMT process. In some embodiments, when the sub-test board Z1 is connected to the main test board M1, the pins 210 of the sub-test board Z1 are correspondingly connected to the contacts D110 of the connection unit 110.

In some embodiments, the connection unit 110 further includes a receptacle a110 and a number of jumper holes K110. Each socket a110 includes a plurality of pins B110, wherein the number of pins B110 is identical to the number of contacts D110, and the contacts D110 receive the pins B110 such that the pins B110 are connected with the contacts D110. In addition, each contact D110 is electrically connected to the corresponding jumper hole K110. In some embodiments, each contact D110 and corresponding jumper hole K110 may also be connected by a patterned conductive layer previously provided on the main test board M1. In some embodiments, the jumper holes K110 are configured to receive a jumper T, and when the corresponding jumper holes K110 of each connection unit 110 are connected by the jumper T, connection between the connection units 110 may be achieved.

With this arrangement, when the pin 210 of the sub-test board Z1 is inserted into the socket a110 to connect with the main test board M1, the signal input terminal 120 transmits a signal (e.g., the bias signal VDD) received from an external signal source to the chip C through the patterned conductive layer, the contact D110, the jumper T, the socket a110 and the pin 210 to perform the bias test. The sub-test board Z1 is connected with the main test board M1 conveniently, faults of the whole main test board M1 and the sub-test board Z1 are more easily checked, and the independent sub-test board Z1 is easily separated from the main test board M1 in time when abnormality occurs, so that test quality is improved.

In the embodiment of fig. 1, the signal input terminal 120 is connected to the contact D110 in the nearest row of connection units 110 through the patterned conductive layer, and the connection units 110 are connected through the jumper T, thereby completing the signal connection of the signal input terminal 120 to the entire main test board M1.

However, in other embodiments, the signal input terminal 120 may be directly connected to the contact D110 in all the connection units 110 through the patterned conductive layer, thereby omitting the provision of the jumper hole K110 and the use of the jumper T.

Referring to fig. 2, fig. 2 illustrates a schematic diagram of an integrated circuit testing device 2 according to another embodiment of the present application. In certain embodiments, integrated circuit testing device 2 is configured to bias test an integrated circuit chip. In some embodiments, integrated circuit testing device 2 includes a main test board M2 and a sub-test board Z2. In some embodiments, the sub-test panel Z2 is removably connected to the main test panel M2. In some embodiments, the main test board M2 includes a connection unit 111 (indicated by a dashed box in the figure) and a signal input terminal 121. The main test board M2 includes a plurality of connection units 111 to facilitate batch testing of the integrated circuit chips. The main test board M2 includes a plurality of signal input terminals 121 to facilitate the simultaneous connection of a plurality of input signals to the integrated circuit chip for testing, wherein the plurality of connection units 111 are arranged in a matrix on the main test board M2. In some embodiments, the signal input terminals 121 may receive the bias signal VDD, the ground GND, the clock signal CLK and the adjustment signal Trim from external signal sources, respectively. In other embodiments, signal input 121 may also receive other desired signals from an external signal source.

In some embodiments, the connection units 111 include a plurality of contacts D111, wherein each signal input terminal 121 is electrically connected to a corresponding contact D111 in each connection unit 111, such that each connection unit 111 receives an input signal from the signal input terminal 121 through the contact D111. In the embodiment of fig. 2, the connection of the signal input 121 to the contact D111 is shown in dashed lines. In some embodiments, the connection of the signal input 121 to the contact D111 is made through a patterned conductive layer previously provided on the main test board M2.

In some embodiments, the subtest board Z2 is identical to the subtest board Z1 of the embodiment of FIG. 1. The sub-test board Z2 includes a number of pins 211. In some embodiments, the number of pins 211 corresponds to the number of contacts D111 on the connection unit 111. In some embodiments, each pin 211 is connected with a signal port (as shown in phantom) of a chip C on the sub-test board Z2. In some embodiments, the chip C may be attached to the sub-test board Z2 by an SMT process. In some embodiments, when the sub-test board Z2 is connected to the main test board M2, the pin 211 of the sub-test board Z2 is correspondingly connected to the contact D111 of the connection unit 111.

In certain embodiments, the connection unit 111 further comprises a socket a111. Each socket a111 includes a plurality of pins B111, wherein the number of pins B11 is identical to the number of contacts D1111, and the contacts D111 receive the pins B111 such that the pins B111 are connected with the contacts D111.

In some embodiments, the contacts D111 and the contacts D111 corresponding to each connection unit 111 are electrically connected to the corresponding signal input terminals 121 through a patterned conductive layer, so that the jumper hole K110 and the jumper T are omitted, thereby completing the signal connection between the signal input terminals 121 and the whole main test board M2.

With this arrangement, when the sub-test board Z2 is connected to the main test board M2, the signal input terminal 121 transmits a signal (e.g., the bias signal VDD) received from an external signal source to the chip C through the patterned conductive layer, the contact D111, the socket a111 and the pin 211 for performing the bias test. The sub-test board Z2 is connected with the main test board M2 conveniently, faults of the whole main test board M2 and the sub-test board Z2 are more easily checked, and the independent sub-test board Z2 is easily separated from the main test board M2 in time when abnormality occurs, so that test quality is improved.

Fig. 3 illustrates a schematic diagram of an integrated circuit testing device 3 according to another embodiment of the present application. In certain embodiments, integrated circuit testing device 3 is configured to bias test an integrated circuit chip. In some embodiments, integrated circuit testing device 3 includes a main test board M3 and a sub-test board Z3. In some embodiments, the sub-test panel Z3 is removably connected to the main test panel M3. In some embodiments, the main test plate M3 includes a connection unit 112 (identified by a dashed box in the figure) and a signal input 122. The main test board M3 includes a plurality of connection units 112 to facilitate batch testing of integrated circuit chips. The main test board M3 includes a plurality of signal input terminals 122 for simultaneously inputting a plurality of input signals to the integrated circuit chip for testing, wherein the plurality of connection units 112 are arranged in a matrix on the main test board M3. In some embodiments, the signal input terminals 122 may receive the bias signal VDD, the ground GND, the clock signal CLK and the adjustment signal Trim from external signal sources, respectively. In other embodiments, the signal input 122 may also receive other desired signals from an external signal source.

In some embodiments, the connection unit 112 includes a plurality of contacts D112, wherein each signal input terminal 122 is electrically connected to a corresponding contact D112 in a row of connection units 112 closest to the signal input terminal 122, such that the connection units 112 receive an input signal from the signal input terminal 122 through the contact D112. In some embodiments, the connection between the signal input terminal 122 and the contact D112 may be through a patterned conductive layer (shown in dotted lines) previously provided on the main test board M3.

In some embodiments, the sub-test board Z3 includes a number of pins 212. In some embodiments, the number of pins 212 corresponds to the number of contacts D112 on the connection unit 112. In some embodiments, each pin 212 is connected (as shown in phantom) with a signal port of chip C on sub-test board Z3. In some embodiments, the sub-test board Z3 includes a chip holder 222, wherein the chip C is embedded in the chip holder 222 to be disposed on the sub-test board Z3. In some embodiments, when the sub-test board Z3 is connected to the main test board M3, the pin 212 of the sub-test board Z3 is correspondingly connected to the contact D112 of the connection unit 112.

In some embodiments, the connection unit 112 further includes a number of pin holes a112 and a number of jumper holes K112. The number of the pin holes A112 is consistent with that of the contacts D112, and the contacts D112 are connected with the pin holes A112. In addition, each contact D112 is electrically connected to the corresponding jumper hole K112. In some embodiments, each contact D112 and corresponding jumper hole K112 may also be connected by a patterned conductive layer previously provided on the main test board M3. In some embodiments, the jumper holes K112 are configured to receive a jumper T through which a connection between the connection units 112 may be made when the corresponding jumper holes K112 of each connection unit 112 are connected.

With this arrangement, when the pin 212 of the sub-test board Z3 is inserted into the pin hole a112 to connect with the main test board M3, the signal input terminal 122 transmits a signal (e.g., the bias signal VDD) received from an external signal source to the chip C through the patterned conductive layer, the contact D112, the jumper T, the pin hole a112 and the pin 212 to perform the bias test. The sub-test board Z3 is connected with the main test board M3 conveniently, faults of the whole main test board M3 and the sub-test board Z3 are more easily checked, and the independent sub-test board Z3 is easily separated from the main test board M3 in time when abnormality occurs, so that test quality is improved.

In the embodiment of fig. 3, the signal input terminal 122 is connected to the contact D112 in the nearest row of connection units 112 through the patterned conductive layer, and the connection units 112 are connected through the jumper T, thereby completing the signal connection of the signal input terminal 122 to the entire main test board M3.

However, in other embodiments, the signal input terminal 122 may be directly connected to the contact D112 in all the connection units 112 through the patterned conductive layer, thereby omitting the provision of the jumper hole K112 and the use of the jumper T.

Referring to fig. 4, fig. 4 illustrates a schematic diagram of an integrated circuit testing device 4 according to another embodiment of the present application. In certain embodiments, integrated circuit testing device 4 is configured to bias test an integrated circuit chip. In some embodiments, integrated circuit testing device 4 includes a main test board M4 and a sub-test board Z4. In some embodiments, the sub-test panel Z4 is removably connected to the main test panel M4. In some embodiments, the main test plate M4 includes a connection unit 113 (identified by a dashed box in the figure) and a signal input 123. The main test board M4 includes a plurality of connection units 113 to facilitate batch testing of integrated circuit chips. The main test board M4 includes a plurality of signal input terminals 123 for facilitating the simultaneous connection of a plurality of input signals to the integrated circuit chip for testing, wherein the plurality of connection units 113 are arranged in a matrix on the main test board M4. In some embodiments, the signal input terminals 123 may receive the bias signal VDD, the ground GND, the clock signal CLK and the adjustment signal Trim from external signal sources, respectively. In other embodiments, signal input 123 may also receive other desired signals from an external signal source.

In some embodiments, the connection units 113 include a plurality of contacts D113, wherein each signal input terminal 123 is electrically connected to a corresponding contact D113 in each connection unit 113, such that each connection unit 113 receives an input signal from the signal input terminal 123 through the contact D113. In the embodiment of fig. 4, the connection of the signal input 123 to the junction D113 is shown in dashed lines. In some embodiments, the connection of the signal input 123 to the contact D113 is made through a patterned conductive layer previously provided on the main test board M4.

In some embodiments, the sub-test panel Z4 is identical to the sub-test panel Z3 of the embodiment of FIG. 3. The sub-test board Z4 includes a number of pins 213. In some embodiments, the number of pins 213 corresponds to the number of contacts D113 on the connection unit 113. In some embodiments, each pin 213 is connected (as shown in phantom) to a signal port of chip C on sub-test board Z4. In some embodiments, the sub-test board Z4 includes a chip holder 223, wherein the chip C is embedded in the chip holder 223 to be disposed on the sub-test board Z4. In some embodiments, when the sub-test board Z4 is connected to the main test board M4, the pin 213 of the sub-test board Z4 is correspondingly connected to the contact D113 of the connection unit 113.

In some embodiments, the connection unit 113 further includes a plurality of pin holes a113, and the number of pin holes a113 is identical to the number of contacts D113, and the contacts D113 are connected to the pin holes a 113. In some embodiments, the contacts D113 and the contacts D113 of each connection unit 113 are electrically connected to the corresponding signal input terminals 123 through the patterned conductive layer, so that the jumper hole K113 and the jumper T are omitted, thereby completing the signal connection between the signal input terminals 123 and the whole main test board M4.

With this arrangement, when the pin 213 of the sub-test board Z4 is inserted into the pin hole a113 to connect with the main test board M4, the signal input terminal 123 transmits a signal (e.g., the bias signal VDD) received from an external signal source to the chip C through the patterned conductive layer, the contact D113, the pin hole a113 and the pin 213 to perform the bias test. The sub-test board Z4 is connected with the main test board M4 conveniently, faults of the whole main test board M4 and the sub-test board Z4 are more easily checked, and the independent sub-test board Z4 is easily separated from the main test board M4 in time when abnormality occurs, so that test quality is improved.

In the embodiment of fig. 1 to 4, one chip C is provided on each of the sub-test boards Z1 to Z4. However, this is not a limitation of the present application. In other embodiments, each sub-test board may be provided with a plurality of chips C, so long as the signal port of each chip can be electrically connected with the corresponding pin, when the sub-test board is connected with the main test board, the signal input terminals can receive the signal source from the signal input terminals to the chips, so as to implement batch test.

As used herein, the terms "approximately," "substantially," and "about" are used to describe and account for minor variations. When used in connection with an event or circumstance, the terms can refer to instances where the event or circumstance occurs precisely and instances where it occurs to the close approximation. As used herein with respect to a given value or range, the term "about" generally means within ±10%, ±5%, ±1% or ±0.5% of the given value or range. Ranges can be expressed herein as from one endpoint to the other endpoint, or between two endpoints. Unless otherwise specified, all ranges disclosed herein include endpoints. The term "substantially coplanar" may refer to two surfaces within a few micrometers (μm) positioned along a same plane, for example, within 10 μm, within 5 μm, within 1 μm, or within 0.5 μm positioned along the same plane. When referring to "substantially" the same value or property, the term may refer to a value that is within ±10%, 5%, 1% or 0.5% of the average value of the values.

As used herein, the terms "approximately," "substantially," and "about" are used to describe and explain minor variations. When used in connection with an event or circumstance, the terms can refer to instances where the event or circumstance occurs precisely and instances where it occurs to the close approximation. For example, when used in conjunction with a numerical value, the term can refer to a range of variation of less than or equal to ±10% of the numerical value, e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, two values may be considered to be "substantially" or "about" the same if the difference between the two values is less than or equal to ±10% (e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%) of the average value of the values. For example, "substantially" parallel may refer to a range of angular variation of less than or equal to ±10° relative to 0 °, for example, less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°. For example, "substantially" perpendicular may refer to a range of angular variation of less than or equal to ±10° relative to 90 °, for example, less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

For example, two surfaces may be considered to be coplanar or substantially coplanar if the displacement between the two surfaces is equal to or less than 5 μm, equal to or less than 2 μm, equal to or less than 1 μm, or equal to or less than 0.5 μm. A surface may be considered planar or substantially planar if the displacement of the surface relative to the plane between any two points on the surface is equal to or less than 5 μm, equal to or less than 2 μm, equal to or less than 1 μm, or equal to or less than 0.5 μm.

As used herein, the singular terms "a" and "an" may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided "on" or "over" another component may encompass the case where the former component is directly on (e.g., in physical contact with) the latter component, as well as the case where one or more intermediate components are located between the former component and the latter component.

As used herein, spatially relative terms such as "below," "lower," "above," "upper," "lower," "left," "right," and the like may be used herein for ease of description to describe one component or feature's relationship to another component or feature as illustrated in the figures. In addition to the orientations depicted in the figures, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present.

The foregoing has outlined features of several embodiments and detailed aspects of the present disclosure. The embodiments described in this disclosure may be readily used as a basis for designing or modifying other processes and structures for carrying out the same or similar purposes and/or obtaining the same or similar advantages of the embodiments introduced herein. Such equivalent constructions do not depart from the spirit and scope of the present disclosure and are susceptible to various changes, substitutions and alterations without departing from the spirit and scope of the present disclosure.

Claims (8)

1. An integrated circuit testing apparatus, comprising:

the main test board comprises a connecting unit and a plurality of signal input ends, wherein the connecting unit comprises a plurality of joints,

the signal input ends are electrically connected with the contacts; and

the sub-test board comprises a plurality of pins, wherein the pins are connected with a plurality of signal ports of a chip on the sub-test board, and the pins are correspondingly connected with the contacts when the sub-test board is connected with the main test board.

2. The integrated circuit testing device of claim 1, wherein the sub-test board further comprises a patterned conductive layer connecting the plurality of pins to the plurality of signal ports of the chip.

3. The integrated circuit testing device of claim 2, wherein the chip is attached to the sub-test board.

4. The integrated circuit testing device of claim 2, wherein the sub-test board further comprises a chip carrier, the chip being embedded in the chip carrier for placement on the sub-test board.

5. The integrated circuit testing device of claim 1, wherein the connection unit comprises a socket, a plurality of pins of the socket being connected to the plurality of contacts, the socket receiving the sub-test board when the sub-test board is connected to the main test board.

6. The integrated circuit testing device of claim 1, wherein the connection unit includes a plurality of pin holes connected with the plurality of pins when the sub-test board is connected with the main test board.

7. The integrated circuit testing device of claim 1, wherein said main test plate includes a plurality of said connection units, said main test plate further including a patterned conductive layer connecting corresponding ones of said connection units.

8. The integrated circuit testing device of claim 1, wherein the main test board comprises a plurality of the connection units, each of the connection units further comprising a plurality of jumper holes, the plurality of jumper holes electrically connected to the plurality of contacts.