CN220543345U - EEPROM control circuit - Google Patents
EEPROM control circuit Download PDFInfo
- Publication number
- CN220543345U CN220543345U CN202321877857.2U CN202321877857U CN220543345U CN 220543345 U CN220543345 U CN 220543345U CN 202321877857 U CN202321877857 U CN 202321877857U CN 220543345 U CN220543345 U CN 220543345U
- Authority
- CN
- China
- Prior art keywords
- eeprom
- pin
- state
- mcu
- control circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000010586 diagram Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Landscapes
- Read Only Memory (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Storage Device Security (AREA)
Abstract
The utility model relates to the technical field of control, in particular to an EEPROM control circuit, wherein an SCL pin, an SDA pin and a WP pin are all provided with MCU control, and are connected with the MCU through resistors at the same time, and are connected with positive 5V high level through the resistors at the same time.
Description
Technical Field
The utility model relates to the technical field of control, in particular to an EEPROM control circuit.
Background
As shown in fig. 1, the conventional circuit is also shown in fig. 1, the EEPROM control circuit is shown in the figure, the SDL (5 pin) and SCL (6 pin) of the EEPROM (D9) are in communication with the MCU, wherein WP (7 pin) is used for determining whether the EEPROM is in a read-only state or a read-write state, in the read-only state, the MCU can only read data of the EEPROM but cannot write data, in the read-write state, the MCU can not only read data of the EEPROM but also write data, when WP is connected with 5V, the EEPROM is in the read-only state, and when WP is connected with GND, the EEPROM is in the read-write state, so the conventional design is to select R67 and R84, or R67 has no R84 (read-only state), or no R67 has R84 (read-write state).
In most cases, during the operation of the circuit board, the MCU needs to write data into the EEPROM, so that no R67 has R84 (readable and writable state), in which case, since the EEPROM is always in the readable and writable state, external interference may cause erroneous data to be written, so that the data of the EEPROM is rewritten by mistake, resulting in failure of the circuit board.
In view of the above drawbacks, the present technical solution has been specially developed.
Disclosure of Invention
An object of the present utility model is to provide an EEPROM control circuit for controlling whether the WP pin is in a high level (5V) state or a low level (GND) state by an MCU, thereby controlling whether the EEPROM is in a read-only state or a readable-writable state.
In order to achieve the above purpose, the present utility model provides the following technical solutions:
an EEPROM control circuit is provided with MCU control on SCL pin, SDA pin and WP pin, wherein the SCL pin, the SDA pin and the WP pin are connected with the MCU through resistors at the same time and are connected with positive 5V high level through the resistors at the same time.
According to the technical scheme, based on an original circuit, the control of the WP pin is increased, whether the WP pin is in a high level (5V) state or a low level (GND) state is controlled through the MCU, so that the EEPROM is in a read-only state or a readable and writable state is controlled, if the MCU needs to write data, the MCU outputs a low level to enable the EEPROM to be in the readable and writable state, and after the MCU finishes writing data, the MCU outputs a high level to enable the EEPROM to be in the read-only state, so that the EEPROM is in the read-only state most of the time except when the EEPROM needs to write data, even if an interference signal exists, the EEPROM cannot be written in the EEPROM, and the reliability of the circuit board is improved.
The technical scheme can reduce the probability of rewriting EEPROM data by external interference and improve the reliability of the circuit board.
Drawings
FIG. 1 is a prior art EEPROM control circuit diagram;
fig. 2 is a circuit diagram of the eeprimd control circuit of the present embodiment.
Detailed Description
Please refer to fig. 2.
An EEPROM control circuit is provided with MCU control on SCL pin, SDA pin and WP pin, wherein the SCL pin, the SDA pin and the WP pin are connected with the MCU through resistors at the same time and are connected with positive 5V high level through the resistors at the same time.
The WP pin is controlled to be in a high level (5V) state or a low level (GND) state by the MCU, so that the EEPROM is controlled to be in a read-only state or a readable and writable state, if the MCU needs to write data, the MCU outputs a low level to enable the EEPROM to be in the readable and writable state, and after the MCU finishes writing data, the MCU outputs a high level to enable the EEPROM to be in a read-only state, so that the EEPROM is in the read-only state most of the time except when the EEPROM needs to write data, and even if an interference signal exists, the EEPROM cannot be written in the EEPROM, thereby improving the reliability of the circuit board.
The foregoing description is only a preferred embodiment of the present utility model, but the scope of the present utility model is not limited thereto, and any person skilled in the art, who is within the scope of the present utility model, should make equivalent substitutions or modifications according to the technical solution of the present utility model and the inventive concept thereof, and should be covered by the scope of the present utility model.
Claims (1)
1. An EEPROM control circuit is characterized in that an SCL pin, an SDA pin and a WP pin are all provided with MCU control, and are connected with the MCU through resistors at the same time, and are connected with positive 5V high level through the resistors at the same time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321877857.2U CN220543345U (en) | 2023-07-18 | 2023-07-18 | EEPROM control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321877857.2U CN220543345U (en) | 2023-07-18 | 2023-07-18 | EEPROM control circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN220543345U true CN220543345U (en) | 2024-02-27 |
Family
ID=89966673
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202321877857.2U Active CN220543345U (en) | 2023-07-18 | 2023-07-18 | EEPROM control circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN220543345U (en) |
-
2023
- 2023-07-18 CN CN202321877857.2U patent/CN220543345U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20120089766A1 (en) | Non-volatile memory storage apparatus, memory controller and data storing method | |
| US8984250B2 (en) | Memory controller, memory device and method for determining type of memory device | |
| US9552287B2 (en) | Data management method, memory controller and embedded memory storage apparatus using the same | |
| CN104658612A (en) | Method for accessing storage unit in flash memory and device using the same | |
| CN103544994A (en) | Flash memory controller and flash memory debugging method | |
| US10387361B2 (en) | Serial device with configuration mode for changing device behavior | |
| TWI509615B (en) | Data storing method, and memory controller and memory storage apparatus using the same | |
| US10191533B2 (en) | Method of enabling sleep mode, memory control circuit unit and storage apparatus | |
| CN220543345U (en) | EEPROM control circuit | |
| US20160364148A1 (en) | Buffer memory accessing method, memory controller and memory storage device | |
| US20040054859A1 (en) | Mouse device capable of storing data | |
| CN107341064B (en) | Anti-misplug system based on sub circuit board of vehicle variable flow control unit | |
| CN110209433B (en) | Method for identifying concentrators of different models | |
| CN100392764C (en) | Television data storage method | |
| US9633718B1 (en) | Nonvolatile memory device | |
| CN113590153A (en) | Firmware upgrading method, system, equipment and medium for CPLD | |
| CN103870209A (en) | Working mode switching method, memory controller and memory storage device | |
| CN102520878A (en) | Method and system for visiting intelligent secure digital (SD) card | |
| US6405260B2 (en) | Data transmission method and apparatus for interfacing between main system and microcomputer | |
| CN110427070A (en) | A method of improving real-time timepiece chip time data reliability | |
| EP3557422A1 (en) | Method for accessing code sram, and electronic device | |
| CN103777732A (en) | Connector control method, connector and storage storing device | |
| CN216719504U (en) | Reliable storage system of control chip and external memory | |
| TWI430281B (en) | Multi - in - one access device and its access method | |
| TWI521354B (en) | Controlling method for connector, connector and memory storage device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |