CN220492863U - Current low-end sampling circuit and battery - Google Patents
Current low-end sampling circuit and battery Download PDFInfo
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- CN220492863U CN220492863U CN202321898650.3U CN202321898650U CN220492863U CN 220492863 U CN220492863 U CN 220492863U CN 202321898650 U CN202321898650 U CN 202321898650U CN 220492863 U CN220492863 U CN 220492863U
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- 238000005070 sampling Methods 0.000 title claims abstract description 87
- 238000006243 chemical reaction Methods 0.000 claims abstract description 53
- 239000003990 capacitor Substances 0.000 claims description 55
- 230000003321 amplification Effects 0.000 description 3
- 238000003199 nucleic acid amplification method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
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Abstract
The application provides a low-end sampling circuit of electric current and charger. The current low-end sampling circuit comprises: an output circuit and a current collection circuit. The output circuit comprises a third resistor and a conversion chip, a first end of the third resistor is connected with an output end pin of the conversion chip, a second end of the third resistor is grounded, and the conversion chip comprises an operational amplifier. The sampling circuit comprises a sampling resistor, a first resistor and a second resistor, wherein the first end of the sampling resistor is used for being connected with the negative electrode of the charger, the second end of the sampling resistor is used for being connected with the negative electrode of the battery, the first end of the first resistor and the first end of the sampling resistor, the second end of the first resistor and the reverse input end of the operational amplifier are connected, the first end of the second resistor and the second end of the sampling resistor are connected, and the second end of the second resistor and the same-direction input end of the operational amplifier are connected.
Description
Technical Field
The utility model relates to the technical field of batteries, in particular to a current low-end sampling circuit and a charger.
Background
With the rise of electronic products, batteries are increasingly used. When the electric quantity of the electronic product is exhausted, the electronic product needs to be charged through the charger, so that the electronic product can be used normally continuously. When the electronic product is charged, the power supply is connected with the electronic product through the charger, and current flows out from the power supply and flows into the battery of the electronic product through the circuit of the charger.
However, if the current is not sampled from the charger's circuit during charging, the charger's circuit may be damaged when the current exceeds a set value. If the current during charging is not sampled in the charging state, the charging state identification or display cannot be performed, the current during charging cannot be fed back to the MCU (Microcontroller Unit, micro control unit), the MCU cannot detect the charging state, and the MOS (metal oxide semiconductor, metal-oxide-semiconductor) tube switch cannot be effectively and rapidly controlled, so that the circuit of the charger is possibly damaged and the function is invalid, and potential safety hazards are caused.
Disclosure of Invention
The utility model aims to overcome the defects in the prior art and provides a current low-end sampling circuit and a charger which can sample current during charging.
The aim of the utility model is realized by the following technical scheme:
a current low-side sampling circuit, comprising:
the output circuit comprises a third resistor and a conversion chip, wherein the first end of the third resistor is connected with an output end pin of the conversion chip, the second end of the third resistor is grounded, and the conversion chip comprises an operational amplifier;
the sampling circuit comprises a sampling resistor, a first resistor and a second resistor, wherein the first end of the sampling resistor is used for being connected with the negative electrode of a charger, the second end of the sampling resistor is used for being connected with the negative electrode of a battery, the first end of the first resistor is connected with the first end of the sampling resistor, the second end of the first resistor is connected with the reverse input end of the operational amplifier, the first end of the second resistor is connected with the second end of the sampling resistor, and the second end of the second resistor is connected with the same-direction input end of the operational amplifier.
In one embodiment, the current sampling circuit includes a first capacitor, a first end of the first capacitor is connected to a second end of the first resistor, and a second end of the first capacitor is connected to a second end of the second resistor.
In one embodiment, the first capacitor is a variable capacitor or an electrolytic capacitor.
In one embodiment, the output circuit includes a second capacitor, a first end of the second capacitor is connected to the first end of the third resistor, and a second end of the second capacitor is connected to the second end of the third resistor.
In one embodiment, the magnitude of the resistance of the sampling resistor includes any one of 1 milliohm to 10 milliohm.
In one embodiment, the ratio of the resistance of the third resistor to the resistance of the second resistor comprises any one of values 15 to 25.
In one embodiment, the current low-end sampling circuit further includes a third capacitor, a first end of the third capacitor is connected with the power supply pin of the conversion chip, a first end of the third capacitor is used for being connected with an anode of a power supply, and a second end of the third capacitor is grounded.
In one embodiment, at least one of the second resistor and the third resistor is a variable resistor.
In one embodiment, the conversion chip comprises a WA142 chip.
A battery comprising a current low-side sampling circuit as in any one of the embodiments above.
Compared with the prior art, the utility model has at least the following advantages:
when charging, the sampling resistor has current to pass through, the sampling resistor will generate voltage drop, then the voltage drop on the sampling resistor is taken by the conversion chip through the first resistor and the second resistor, and the voltage drop is input into the operational amplifier in the conversion chip for amplification, according to the operationVirtual short of amplifier (V i -V+)/r 2 ＝Vout/r 3 And the virtual short principle v+=v-, is×rs 1 /r 2 ＝Vout/r 3 ，Vout＝(r 3 /r 2 )*Is*rs 1 Wherein V is i V+ is the voltage at the same directional input terminal of the operational amplifier, r 2 Is the resistance value of the second resistor, vout is the voltage of the output terminal pin of the conversion chip, r 3 Is the resistance of the third resistor, V-Is the voltage at the inverting input terminal of the operational amplifier, is the current flowing through the sampling resistor, rs 1 The resistance of the second resistor and the resistance of the third resistor can be adjusted according to a formula to adjust the voltage of the output terminal pin of the conversion chip. Therefore, when the voltage drop is adopted by the conversion chip, after the voltage drop is processed by the operational amplifier in the conversion chip, the output end pin of the conversion chip outputs a level signal to the ADC of the MCU, so that the MCU performs charge identification and display according to the acquired level signal and controls the MOS tube to be opened or closed. Therefore, when the current exceeds a set value, the MUC can timely control the closing of the MOS tube, so that the circuit damage of the charger is avoided, the potential safety hazard is reduced, and the charging identification and display can be performed according to the level signal.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present utility model and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a circuit diagram of a current low-side sampling circuit according to an embodiment.
Detailed Description
In order that the utility model may be readily understood, a more complete description of the utility model will be rendered by reference to the appended drawings. The drawings illustrate preferred embodiments of the utility model. This utility model may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "fixed to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like are used herein for illustrative purposes only and are not meant to be the only embodiment.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this utility model belongs. The terminology used herein in the description of the utility model is for the purpose of describing particular embodiments only and is not intended to be limiting of the utility model. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
The utility model relates to a current low-end sampling circuit. In one embodiment, a current low-side sampling circuit includes: an output circuit and a current collection circuit. The output circuit comprises a third resistor and a conversion chip, a first end of the third resistor is connected with an output end pin of the conversion chip, a second end of the third resistor is grounded, and the conversion chip comprises an operational amplifier. The sampling circuit comprises a sampling resistor, a first resistor and a second resistor, wherein the first end of the sampling resistor is used for being connected with the negative electrode of a charger, the second end of the sampling resistor is used for being connected with the negative electrode of a battery, the first end of the first resistor is connected with the first end of the sampling resistor, the second end of the first resistor is connected with the reverse input end of the operational amplifier, the first end of the second resistor is connected with the second end of the sampling resistor, and the second end of the second resistor is connected with the same-direction input end of the operational amplifier. During charging, the sampling resistor has current passing through it for samplingThe resistor generates voltage drop, then the voltage drop on the sampling resistor is taken by the conversion chip through the first resistor and the second resistor, and the voltage drop is input into an operational amplifier in the conversion chip for amplification, according to the virtual short (V i -V+)/r 2 ＝Vout/r 3 And the virtual short principle v+=v-, is×rs 1 /r 2 ＝Vout/r 3 ，Vout＝(r 3 /r 2 )*Is*rs 1 Wherein V is i V+ is the voltage at the same directional input terminal of the operational amplifier, r 2 Is the resistance value of the second resistor, vout is the voltage of the output terminal pin of the conversion chip, r 3 Is the resistance of the third resistor, V-Is the voltage at the inverting input terminal of the operational amplifier, is the current flowing through the sampling resistor, rs 1 The resistance of the second resistor and the resistance of the third resistor can be adjusted according to a formula to adjust the voltage of the output terminal pin of the conversion chip. Therefore, when the voltage drop is adopted by the conversion chip, after the voltage drop is processed by the operational amplifier in the conversion chip, the output end pin of the conversion chip outputs a level signal to the ADC of the MCU, so that the MCU performs charge identification and display according to the acquired level signal and controls the MOS tube to be opened or closed. Therefore, when the current exceeds a set value, the MUC can timely control the closing of the MOS tube, so that the circuit damage of the charger is avoided, the potential safety hazard is reduced, and the charging identification and display can be performed according to the level signal.
Please refer to fig. 1, which is a circuit diagram of a current low-side sampling circuit according to an embodiment of the present utility model.
The current low-side sampling circuit 10 of an embodiment includes an output circuit and a current sampling circuit. The output circuit comprises a third resistor R3 and a conversion chip U1, wherein a first end of the third resistor R3 is connected with an output end pin of the conversion chip U1, a second end of the third resistor R3 is grounded, and the conversion chip U1 comprises an operational amplifier. The sampling circuit comprises a sampling resistor RS1, a first resistor R1 and a second resistor R2, wherein the first end of the sampling resistor RS1 is used for being connected with a negative electrode P-of a charger, the second end of the sampling resistor is used for being connected with a negative electrode B-of a battery, the first end of the first resistor R1 is connected with the first end of the sampling resistor RS1, the second end of the first resistor R1 is connected with the reverse input end of an operational amplifier, the first end of the second resistor R2 is connected with the second end of the sampling resistor RS1, and the second end of the second resistor R2 is connected with the same-direction input end of the operational amplifier.
In this embodiment, when charging, the sampling resistor RS1 has a current passing through, the sampling resistor RS1 generates a voltage drop, then the conversion chip U1 takes the voltage drop on the sampling resistor RS1 through the first resistor R1 and the second resistor R2, and inputs the voltage drop into the operational amplifier inside the conversion chip U1 for amplification, according to the imaginary short (Vi-v+)/r2=vout/R3 of the operational amplifier, and the imaginary short principle v+=v-, isrs 1/r2=vout/R3, vout= (R3/R2) ×is) Is RS1, where Vi Is the voltage at the first end of the second resistor R2, v+ Is the voltage at the same directional input end of the operational amplifier, R2 Is the resistance value of the second resistor R2, vout Is the voltage at the output end pin of the conversion chip U1, R3 Is the resistance value of the third resistor R3, V-Is the voltage at the reverse input end of the operational amplifier, vout= (R3/R2) Is the current flowing through the sampling resistor RS1, and thus the resistance value of the third resistor R1 can be adjusted according to the formula. Therefore, when the voltage drop is adopted by the conversion chip U1, after the voltage drop is processed by the operational amplifier in the conversion chip U1, the output end pin of the conversion chip U1 outputs a level signal to the ADC of the MCU, so that the MCU performs charging identification and display and controls the opening or closing of the MOS tube according to the acquired level signal. Therefore, when the current exceeds a set value, the MUC can timely control the closing of the MOS tube, so that the circuit damage of the charger is avoided, the potential safety hazard is reduced, and the charging identification and display can be performed according to the level signal.
Referring to fig. 1, in one embodiment, the current sampling circuit includes a first capacitor C1, a first end of the first capacitor C1 is connected to a second end of the first resistor R1, and a second end of the first capacitor C1 is connected to a second end of the second resistor R2. In this embodiment, the first capacitor C1 connects the first resistor R1, the sampling resistor RS1 and the second resistor R2 in parallel, filters the first resistor R1, the sampling resistor RS1 and the second resistor R2, and avoids abrupt changes in voltages of the first resistor R1, the sampling resistor RS1 and the second resistor R2, so that the voltage Vi at the first end of the second resistor R2 and the current Is flowing through the sampling resistor RS1 are more stable, and thus the voltage Vout at the output terminal pin of the conversion chip U1 Is calculated more accurately. Furthermore, the first capacitor C1 is connected in parallel between the non-inverting input terminal of the operational amplifier and the inverting input terminal vinip of the operational amplifier, so that interference of high-frequency ac signals and dc pulse interference signals to the operational amplifier can be avoided.
In one embodiment, the first capacitor C1 is a variable capacitor or an electrolytic capacitor. In this embodiment, when the first capacitor C1 is a variable capacitor, the capacitance of the first capacitor C1 may be adjusted, so that the first capacitor C1 may more flexibly resist the change of the current flowing into the operational amplifier, and the current flowing into the operational amplifier may be more stable. When the first capacitor C1 is an electrolytic capacitor, the capacitance of the unit volume of the first capacitor C1 is large, and when the capacitance requirement is determined, the volume of the first capacitor C1 is small, so that the occupied space of the first capacitor C1 is saved.
Referring to fig. 1, in one embodiment, the output circuit includes a second capacitor C2, a first end of the second capacitor C2 is connected to the first end of the third resistor R3, and a second end of the second capacitor C2 is connected to the second end of the third resistor R3. In this embodiment, the second capacitor C2 is connected in parallel with the third resistor R3, so as to avoid abrupt change of the voltage across the third resistor R3. Moreover, when the voltage on the third resistor R3 is too large, the third resistor R3 is prone to generate heat, so that the resistance value of the third resistor R3 is changed, and the calculation accuracy of the voltage Vout of the output terminal pin of the conversion chip U1 is affected.
Referring to fig. 1, in one embodiment, the resistance of the sampling resistor RS1 includes any value from 1 milliohm to 10 milliohms. In this embodiment, if the resistance of the sampling resistor RS1 Is too small, the current Is error of the sampling resistor RS1 will be larger; if the resistance of the sampling resistor RS1 Is too large, the heating of the sampling resistor RS1 Is large, the resistance of the sampling resistor RS1 Is increased, the current Is flowing through the sampling resistor RS1 Is easy to change, and the voltage Vout of the output terminal pin of the conversion chip U1 Is unstable. Further, the resistance of the sampling resistor RS1 includes any value from 1 milliohm to 5 milliohms. In one embodiment, the resistance of the sampling resistor RS1 may be 1 milliohm, 2 milliohm, or 5 milliohm.
Referring to fig. 1, in one embodiment, the ratio of the resistance of the third resistor R3 to the resistance of the second resistor R2 includes any one of values from 15 to 25. In this embodiment, the resistance of the third resistor R3 and the resistance of the second resistor R2 are determined according to the voltage Vout of the output terminal pin of the conversion chip U1, and since the voltage Vout of the output terminal pin of the conversion chip U1 needs to be amplified, the resistance of the third resistor R3 Is generally set to be greater than the resistance of the second resistor R2 according to the calculation formula vout= (R3/R2) ×is×rs1 of the voltage Vout of the output terminal pin of the conversion chip U1. The larger the ratio of the resistance value of the third resistor R3 to the resistance value of the second resistor R2, the larger the voltage Vout applied to the output terminal pin of the amplifying and converting chip U1. In an embodiment, the ratio of the resistance of the third resistor R3 to the resistance of the second resistor R2 includes any one of 15, 18, 20, 21 and 22.
Referring to fig. 1, in one embodiment, the current low-end sampling circuit 10 further includes a third capacitor C3, a first end of the third capacitor C3 is connected to the power supply pin of the conversion chip U1, a first end of the third capacitor C3 is used for connecting to an anode of a power supply, and a second end of the third capacitor C3 is grounded. In this embodiment, the power supply pin of the conversion chip U1 is configured to be connected to a power supply VCC, the power supply VCC supplies power to the conversion chip U1, the power supply VCC is connected to the third capacitor C3 between the ground, and for a high-frequency interference signal, the high-frequency interference signal flows to the ground through the third capacitor C3, so that the conversion chip U1 is free from the interference of the high-frequency signal, and the third capacitor C3 serves as a bypass capacitor to play a role in filtering the high-frequency signal.
In one embodiment, at least one of the second resistor R2 and the third resistor R3 is a variable resistor. In this embodiment, the voltage Vout of the output terminal pin of the conversion chip U1 is determined according to the ratio of the resistance value of the third resistor R3 to the resistance value of the second resistor R2, and when at least one of the second resistor R2 and the third resistor R3 is a variable resistor, the voltage Vout of the output terminal pin of the conversion chip U1 may be adjusted by adjusting the resistance value of the second resistor R2 and/or the resistance value of the third resistor R3, so that the adjustment of the voltage Vout of the output terminal pin of the conversion chip U1 is more flexible.
In one embodiment, the conversion chip U1 comprises a WA142 chip.
A battery comprising a current low-side sampling circuit as in any one of the embodiments above.
The above examples illustrate only a few embodiments of the utility model, which are described in detail and are not to be construed as limiting the scope of the utility model. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the utility model, which are all within the scope of the utility model. Accordingly, the scope of protection of the present utility model is to be determined by the appended claims.
Claims (10)
1. A current low-side sampling circuit, comprising:
the output circuit comprises a third resistor and a conversion chip, wherein the first end of the third resistor is connected with an output end pin of the conversion chip, the second end of the third resistor is grounded, and the conversion chip comprises an operational amplifier;
the sampling circuit comprises a sampling resistor, a first resistor and a second resistor, wherein the first end of the sampling resistor is used for being connected with the negative electrode of a charger, the second end of the sampling resistor is used for being connected with the negative electrode of a battery, the first end of the first resistor is connected with the first end of the sampling resistor, the second end of the first resistor is connected with the reverse input end of the operational amplifier, the first end of the second resistor is connected with the second end of the sampling resistor, and the second end of the second resistor is connected with the same-direction input end of the operational amplifier.
2. The current low-side sampling circuit of claim 1, wherein:
the current sampling circuit comprises a first capacitor, wherein a first end of the first capacitor is connected with a second end of the first resistor, and a second end of the first capacitor is connected with a second end of the second resistor.
3. The current low-side sampling circuit of claim 2, wherein:
the first capacitor is a variable capacitor or an electrolytic capacitor.
4. The current low-side sampling circuit of claim 1, wherein:
the output circuit comprises a second capacitor, wherein the first end of the second capacitor is connected with the first end of the third resistor, and the second end of the second capacitor is connected with the second end of the third resistor.
5. The current low-side sampling circuit of claim 1, wherein:
the resistance of the sampling resistor comprises any value from 1 milliohm to 10 milliohm.
6. The current low-side sampling circuit of claim 1, wherein:
the ratio of the resistance value of the third resistor to the resistance value of the second resistor includes any one of values 15 to 25.
7. The current low-side sampling circuit of claim 1, wherein:
the current low-end sampling circuit further comprises a third capacitor, a first end of the third capacitor is connected with a power supply pin of the conversion chip, a first end of the third capacitor is used for being connected with an anode of a power supply, and a second end of the third capacitor is grounded.
8. The current low-side sampling circuit of claim 1, wherein:
at least one of the second resistor and the third resistor is a variable resistor.
9. The current low-side sampling circuit of claim 1, wherein:
the conversion chip includes a WA142 chip.
10. A battery comprising a current low-side sampling circuit according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321898650.3U CN220492863U (en) | 2023-07-18 | 2023-07-18 | Current low-end sampling circuit and battery |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321898650.3U CN220492863U (en) | 2023-07-18 | 2023-07-18 | Current low-end sampling circuit and battery |
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| Publication Number | Publication Date |
|---|---|
| CN220492863U true CN220492863U (en) | 2024-02-13 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202321898650.3U Active CN220492863U (en) | 2023-07-18 | 2023-07-18 | Current low-end sampling circuit and battery |
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| CN (1) | CN220492863U (en) |
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2023
- 2023-07-18 CN CN202321898650.3U patent/CN220492863U/en active Active
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