CN220456417U - Packaging device - Google Patents

Abstract

The present application provides a packaging device, which includes a redistribution layer. The redistribution layer includes a first conductor pad and a plurality of first conductor lines. The first conductor pad is provided on one side of the redistribution layer, and the first conductor line is provided on on the first conductor pad; the chip component, the chip component includes a second conductor pad and a plurality of second conductor lines, the second conductor pad is disposed on one side of the chip component, the chip component is disposed below the rewiring layer, the second conductor pad is The first conductor pad is parallel and the second conductor pad is arranged at a position opposite to the first conductor pad. The second conductor line is arranged on the second conductor pad and the second conductor line is in contact with the first conductor line; the first conductor line is on the second conductor pad. The width of the distribution area on one conductor pad is greater than the width of the distribution area of the second conductor line on the second conductor pad. The advantage of this application is that it reduces the probability of cracks, necking, damage, deformation and other problems occurring in the packaging device during the production process, thereby improving the yield rate and reducing the cost.

Description

a packaging device

Technical field

The present application relates to the field of semiconductors, and in particular to a packaging device.

Background technique

Packaging structures such as Fan-Out Chip on Substrate (FOCoS) and FOCoS-B (Fan-Out Chip on Substrate Bridge) are 2.5D/3D stacked packaging structures designed to provide multiple tightly interconnected , fine-pitch (for example, pitch less than 300 μm) bare chips (Dies) provide high-speed transmission interconnect lines, and provide fan-out-level (FO-level) integration solutions for homogeneous/heterogeneous multi-chip products.

Prior art FOCoS and FOCoS-B require heating and external pressure during the manufacturing process. Figure 18 shows a schematic diagram of the force exerted on the packaging device using the prior art during the production process. As shown in Figure 18, external pressure mainly acts on the middle part of the packaging device, causing the packaging device to bend in the vertical direction. The dotted line in Figure 18 schematically shows the direction of bending of the packaging device, and the arrow part indicates the packaging device. The ends will tilt up vertically. FIG. 19 shows a schematic diagram of problems that are likely to occur during the production process of the packaging device using the conventional technology as shown in FIG. 18 . Because the package device does not have enough strength to withstand the pressure it receives during the production process, misalignment occurs between its redistribution layer (RDL) and the chip, and between the RDL and the substrate components, leading to cracks 401 , deformation 402, damage 403 and necking 404 and other problems. This reduces the yield rate, increases production costs, and reduces profits.

In summary, there is a need in the art to provide a packaging device that can overcome the shortcomings of the existing technology.

Utility model content

The present application provides a packaging device that can solve the problems of the prior art. The purpose of this application is achieved through the following technical solutions.

One embodiment of the present application provides a packaging device, which includes: a redistribution layer, the redistribution layer includes a first conductor pad and a plurality of first conductor lines, the first conductor pad is disposed on one side of the redistribution layer, a conductor line is disposed on the first conductor pad; a chip component, the chip component includes a second conductor pad and a plurality of second conductor lines, the second conductor pad is disposed on one side of the chip component, and the chip component is disposed below the rewiring layer, The second conductor pad is parallel to the first conductor pad and the second conductor pad is disposed at a position opposite to the first conductor pad, the second conductor line is disposed on the second conductor pad and the second conductor line is in contact with the first conductor line; The width of the distribution area of a conductor line on the first conductor pad is greater than the width of the distribution area of the second conductor line on the second conductor pad.

In some optional embodiments, according to the packaging device provided by the above-mentioned embodiment of the present application, the plurality of second conductor lines are in contact with part of the plurality of first conductor lines.

In some optional embodiments, according to the packaging device provided by the above-mentioned embodiment of the present application, a plurality of second conductor lines are in contact with the first conductor lines disposed near the central portion of the first conductor pad.

In some optional embodiments, according to the packaging device provided by the above-mentioned embodiment of the present application, the distance in which the first conductor line that is not in contact with the second conductor line extends in the direction of the second conductor pad exceeds the first conductor pad. distance from the second conductor pad.

In some optional embodiments, according to the packaging device provided in the above embodiment of the present application, the packaging device further includes a substrate component, the substrate component includes a third conductor pad and a plurality of third conductor lines, and the third conductor pad is provided On one side of the substrate component, the third conductor line is disposed on the third conductor pad, the substrate component is disposed below the redistribution layer, the third conductor pad is parallel to the first conductor pad and the third conductor pad is disposed on the first conductor pad. At the opposite position, the third conductor line is arranged on the third conductor pad and the third conductor line is in contact with the first conductor line. The width of the distribution area of the third conductor line on the third conductor pad is larger than that of the first conductor line on the first conductor pad. The width of the distribution area.

In some optional embodiments, according to the packaging device provided by the above-mentioned embodiment of the present application, the number of substrate components is greater than 1, grooves are formed between the substrate components, and the chip components are disposed in the grooves.

In some optional embodiments, according to the packaging device provided by the above-mentioned embodiment of the present application, the plurality of first conductor lines are in contact with part of the third conductor lines among the plurality of third conductor lines.

In some optional embodiments, according to the packaging device provided by the above-mentioned embodiment of the present application, a plurality of first conductor lines are in contact with third conductor lines disposed near the central portion of the third conductor pad.

In some optional embodiments, according to the packaging device provided by the above-mentioned embodiment of the present application, the filling material is coated outside the first chip component and filled between the rewiring layer and the chip component and between the rewiring layer and the substrate. Between the components, the filling material covers the first conductor line, the second conductor line and the third conductor line.

In some optional embodiments, according to the packaging device provided by the above-mentioned embodiment of the present application, the filling material is a capillary bottom filling material.

In some optional embodiments, according to the packaging device provided in the above embodiment of the present application, the redistribution layer has a multi-layer structure, and each layer includes a first conductive line layer, a redistribution seed layer, a first conductive pillar and A first dielectric layer and a first conductive line located on top of the package device form a first conductor layer.

In some optional embodiments, according to the packaging device provided in the above embodiment of the present application, the chip component further includes a chip and a fan-out rewiring layer of a multi-layer structure, and each layer of the fan-out rewiring layer of the multi-layer structure Both include a second conductive line layer, a fan-out rewiring seed layer, a second conductive pillar and a second dielectric layer. The chip is located on one side of the fan-out rewiring layer of the multi-layer structure. The second conductor pad and a plurality of second The conductor lines are on the other side of the fan-out redistribution layer of the multilayer structure.

In some optional embodiments, according to the packaging device provided in the above embodiment of the present application, the substrate component has a multi-layer structure, and each layer includes a third conductive circuit layer, a substrate seed layer, a third conductive pillar and a third The dielectric layer and the second conductive trace located at the bottom of the package device form a second conductor layer.

In some optional embodiments, according to the packaging device provided by the above-mentioned embodiment of the present application, a system packaging component is provided on the top of the packaging device. The system packaging component includes electronic components and molding material. The molding material covers the electronic components. Components, electronic components are connected to the first conductor layer on top of the redistribution layer.

The advantage of the packaging device according to the embodiment of the present application is that the use of conductor wires improves the connection strength between the rewiring layer and the chip and between the rewiring layer and the substrate component, thereby reducing the occurrence of cracks and necks in the packaging device during the production process. The probability of occurrence of problems such as shrinkage, breakage and deformation is reduced, thereby increasing the yield and reducing costs.

Description of drawings

Other features, objects and advantages of the present application will become more apparent from the detailed description of non-limiting embodiments of the present application with reference to the following drawings.

Figure 1 shows a schematic diagram of a packaging device according to an embodiment of the present application;

Figure 2 shows an enlarged schematic diagram of a portion marked A in the packaging device according to an embodiment of the present application as shown in Figure 1;

Figure 3 shows an enlarged schematic diagram of a portion marked C in the packaging device according to an embodiment of the present application as shown in Figure 2;

Figure 4 shows an enlarged schematic diagram of a portion marked B in the packaging device according to an embodiment of the present application as shown in Figure 1;

Figure 5 shows an enlarged schematic diagram of a portion marked D in the packaging device according to an embodiment of the present application as shown in Figure 4;

Figure 6 shows a schematic diagram of the manufacturing process of the rewiring layer of the packaging device according to an embodiment of the present application;

Figure 7 shows a schematic diagram of the manufacturing process of a packaging device according to an embodiment of the present application;

Figure 8 shows a schematic diagram of a packaging device according to a second embodiment of the present application;

Figure 9 shows a schematic diagram of a packaging device according to a third embodiment of the present application;

Figure 10 shows a schematic diagram of a packaging device according to a fourth embodiment of the present application;

Figure 11 shows a schematic diagram of a packaging device according to a fifth embodiment of the present application;

Figure 12 shows a schematic diagram of a packaging device according to a sixth embodiment of the present application;

Figure 13 shows a schematic diagram of a packaging device according to a seventh embodiment of the present application;

Figure 14 shows a schematic diagram of a packaging device according to an eighth embodiment of the present application;

Figure 15 shows a schematic diagram of a packaging device according to a ninth embodiment of the present application;

Figure 16 shows a schematic diagram of a packaging device using panel level (PNL, Panel Level) packaging according to an embodiment of the present application;

Figure 17 shows a schematic diagram of a packaging device using wafer level (WL, Wafer Level) packaging according to an embodiment of the present application;

Figure 18 shows a schematic diagram of the force exerted on the packaging device using the prior art during the production process;

FIG. 19 shows a schematic diagram of problems that are likely to occur during the production process of the packaging device using the conventional technology as shown in FIG. 18 .

Labels and component names: 1-rewiring layer, 11-first conductor pad, 12-first conductor line, 13-first conductor layer, 14-first conductive line layer, 15-rewiring seed layer, 16-th A conductive pillar, 17-first dielectric layer, 2-chip component, 21-second conductor pad, 22-second conductor line, 23-second conductive line layer, 24-fan-out rewiring seed layer, 25- Second conductive pillar, 26-second dielectric layer, 27-chip, 3-substrate component, 31-third conductor pad, 32-third conductor line, 33-second conductor layer, 34-third conductive line layer , 35-substrate seed layer, 36-third conductive pillar, 37-third dielectric layer, 4-filling material, 5-system packaging components, 51-electronic components, 52-molding material, 6-groove, 7 -Solder ball, 101-carrier board, 102-release film, 103-first conductor, 104-first seed layer, 105-first photoresist layer, 106-first hole, 107-second seed layer, 108 -Dielectric material, 109-first groove, 110-second conductor, 111-dielectric layer, 112-second photoresist layer, 113-second hole, 114-third seed layer, 115-second concave Slot, 116-third conductor, 201-rewiring layer, 202-first chip component, 203-second chip component, 204-substrate component, 205-filling material, 206-seed layer, 207-electronic component, 208- Molding material, 209-solder ball, 210-carrier board, 211-first component, 212-second component, 213-nozzle, 301-fan-out stacked packaging component, 302-electronic component, 303-filling material, 304 -Thermal conductive sheet, 305-chip component, 306-substrate component, 401-crack, 402-deformation, 403-fracture, 404-necking.

Detailed ways

Specific implementations of the present application will be described below with reference to the accompanying drawings and examples. Through the content recorded in this specification, those skilled in the art can clearly and completely understand the technical solutions, technical problems solved and technical effects produced by the present application. It can be understood that the specific embodiments described here are only used to explain the present application, but not to limit the present application. In addition, for convenience of description, only parts relevant to the present application are shown in the drawings.

It should be readily understood that the meanings of "on", "on" and "on" in this application should be construed in the broadest manner such that "on" Not only means "directly on something," but also "on something" including the presence of intermediate parts or layers in between.

In addition, for convenience of description, spatially relative terms such as “below”, “below”, “lower”, “above”, “upper”, etc. may be used herein. The relationship of one element or component to another element or component as illustrated in the drawings. In addition to the orientation depicted in the figures, spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90° or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The term "layer" as used herein refers to a portion of material that includes a region of thickness. A layer may extend throughout the entire underlying or superstructure, or may have an extent that is less than the extent of the underlying or superstructure. Furthermore, a layer may be a region of a homogeneous or inhomogeneous continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes therebetween. The layers may extend horizontally, vertically and/or along tapered surfaces. The substrate may be a layer, may include one or more layers therein, and/or may have one or more layers on, above and/or below it. A layer can include multiple layers. For example, the semiconductor layers may include one or more doped or undoped semiconductor layers and may be of the same or different materials.

The term "substrate" as used herein refers to a material onto which subsequent layers of material are added. The substrate itself can be patterned. The material added to the top of the substrate can be patterned or can remain unpatterned. Additionally, the substrate may include a variety of semiconductor materials, such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of non-conductive material, such as glass, plastic, sapphire wafer, polyamide fiber (Polyamide, PA), polyimide (Polyimide, PI), epoxy resin (Epoxy), polyp Poly-p-phenylene benzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (PrePreg, prepreg material or semi-cured resin, semi-cured sheet) or ABF (Ajinomoto Build -up Film) etc. As a further alternative, the substrate may have a semiconductor device or circuit formed therein.

The term "redistribution layer (RDL)" used herein may be composed of conductive materials and dielectric materials (Dielectric). It should be noted that the redistribution layer formation technology currently known or developed in the future can be used in the manufacturing process. This disclosure does not specifically limit this. For example, the technology including but not limited to photolithography, electroplating (plating), and electroless plating (Electroless plating) can be used. ) and so on form the rewiring layer. Here, the dielectric material may include organic matter and/or inorganic matter, wherein the organic matter may be, for example: polyamide fiber (Polyamide, PA), polyimide (Polyimide, PI), epoxy resin (Epoxy), polyparaphenylene Poly-p-phenylene benzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (PrePreg, prepreg material or semi-cured resin, semi-cured sheet), ABF (Ajinomoto Build-up Film, etc., and the inorganic substance can be, for example, silicon (Si), glass (glass), ceramic (ceramic), silicon oxide, silicon nitride, tantalum oxide, etc. The conductive material may include a seed layer and a metal layer. Here, the seed layer can be, for example, titanium (Ti), tungsten (W), nickel (Ni), etc., and the metal layer can be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu) or its alloys.

The term "die" as used herein may refer to various types of bare chips (ie, Dies). This disclosure does not specifically limit this. For example, it may include logic function chips, memory chips, communication chips, microprocessor chips, graphics chips, micro-electro-mechanical system (MEMS, Micro-Electro-Mechanical System) chips, radio frequency chips, bare chips or chip scale packages, inserts or Its combination etc.

It should be noted that the structures, proportions, sizes, etc. shown in the drawings of the specification are only used to coordinate with the content recorded in the specification for the understanding and reading of those skilled in the art, and are not used to limit the implementation of the present application. Restrictive conditions, so it has no technical substantive significance. Any structural modifications, changes in proportions, or adjustments in size shall still fall within the scope of this application without affecting the effectiveness and purpose of this application. The technical content disclosed must be within the scope that can be covered. At the same time, terms such as "above", "first", "second" and "a" cited in this specification are only for convenience of description and are not used to limit the scope of the application. Changes or adjustments to the relative relationship, provided there is no substantial change in the technical content, shall also be deemed to be within the implementable scope of this application.

It should also be noted that the longitudinal section corresponding to the embodiment of the present application may be a section corresponding to the direction of the front view, the transverse section may be a section corresponding to the direction of the right view, and the horizontal section may be a section corresponding to the direction of the top view.

In addition, the embodiments and features in the embodiments of the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings and embodiments.

Figure 1 shows a schematic diagram of a packaging device according to an embodiment of the present application. FIG. 2 shows an enlarged schematic diagram of a portion marked A in the packaging device according to an embodiment of the present application as shown in FIG. 1 . FIG. 3 shows an enlarged schematic diagram of a portion marked C in the packaging device according to an embodiment of the present application as shown in FIG. 2 . FIG. 4 shows an enlarged schematic diagram of a portion marked B in the packaging device according to an embodiment of the present application as shown in FIG. 1 . FIG. 5 shows an enlarged schematic diagram of a portion marked D in the packaging device according to an embodiment of the present application as shown in FIG. 4 . As shown in Figures 1-5, the packaging device includes: a redistribution layer 1. The redistribution layer 1 includes a first conductor pad 11 and a plurality of first conductor lines 12. The first conductor pad 11 is provided on one side of the redistribution layer 1. , the first conductor line 12 is provided on the first conductor pad 11; the chip component 2, the chip component 2 includes a second conductor pad 21 and a plurality of second conductor lines 22, the second conductor pad 21 is provided on one side of the chip component 2 , the chip component 2 is disposed below the redistribution layer 1, the second conductor pad 21 is parallel to the first conductor pad 11 and the second conductor pad 21 is disposed at a position opposite to the first conductor pad 11, and the second conductor line 22 is disposed On the second conductor pad 21 and the second conductor line 22 is in contact with the first conductor line 12, the first conductor line 12 and the second conductor line 22 are fixedly connected to the redistribution layer 1 and the chip component 2 by contacting and winding with each other; The width of the distribution area of a conductor line 12 on the first conductor pad 11 is greater than the width of the distribution area of the second conductor line 22 on the second conductor pad 21 .

In some optional embodiments, according to the packaging device provided by the above-mentioned embodiment of the present application, the plurality of second conductor lines 22 are in contact with some of the first conductor lines 12 of the plurality of first conductor lines 12 .

In some optional embodiments, according to the packaging device provided by the above-mentioned embodiment of the present application, a plurality of second conductor lines 22 are in contact with the first conductor lines 12 disposed near the central portion of the first conductor pad 11 . The first conductor line 12 at the edge of the first conductor pad 11 does not contact the second conductor line 22 .

In some optional embodiments, according to the packaging device provided by the above-mentioned embodiment of the present application, the distance in which the first conductor line 12 that is not in contact with the second conductor line 22 extends in the direction of the second conductor pad 21 exceeds the second conductor line 22 . The distance between one conductor pad 11 and the second conductor pad 21.

In some optional embodiments, according to the packaging device provided by the above-mentioned embodiment of the present application, the first conductor line 12 in contact with the second conductor line 22 may be inclined, bent or bent, so that the first conductor line 22 12 is in close contact with the second conductor line 22 and is firmly connected.

In some optional embodiments, according to the packaging device provided by the above-mentioned embodiment of the present application, the packaging device further includes a substrate component 3, and the substrate component 3 includes a third conductor pad 31 and a plurality of third conductor lines 32. The three conductor pads 3 are disposed on one side of the substrate component 3, the third conductor line 32 is disposed on the third conductor pad 31, the substrate component 3 is disposed below the redistribution layer 1, the third conductor pad 31 and the first conductor pad 11 The third conductor pad 31 is parallel and disposed at a position opposite to the first conductor pad 11. The third conductor line 32 is disposed on the third conductor pad 31 and the third conductor line 32 is in contact with the first conductor line 12. The wire 12 and the third conductor wire 32 are in contact and entangled with each other so that the redistribution layer 1 is fixedly connected to the substrate component 3. The width of the distribution area of the third conductor wire 32 on the third conductor pad 31 is larger than that of the first conductor wire 12 on the first conductor pad 31. The width of the distribution area on the conductor pad 11.

In some optional embodiments, according to the packaging device provided by the above-mentioned embodiment of the present application, the number of substrate components 3 is greater than 1, grooves 6 are formed between the substrate components 3, and the chip components 2 are arranged in the grooves 6 .

In some optional embodiments, according to the packaging device provided by the above-mentioned embodiment of the present application, the plurality of first conductor lines 12 are in contact with some of the third conductor lines 32 of the plurality of third conductor lines 32 .

In some optional embodiments, according to the packaging device provided by the above-mentioned embodiment of the present application, the plurality of first conductor lines 12 are in contact with the third conductor lines 32 disposed near the central portion of the third conductor pad 31 . The third conductor line 32 at the edge of the third conductor pad 31 does not contact the first conductor line 12 .

In some optional embodiments, according to the package device provided by the above-mentioned embodiment of the present application, the third conductor line 32 that is not in contact with the first body line extends a distance in the direction of the first conductor pad 11 that exceeds the first The distance between the conductor pad 11 and the third conductor pad 31 .

In some optional embodiments, according to the packaging device provided by the above-mentioned embodiment of the present application, the third conductor line 32 in contact with the first conductor line 12 may be inclined, bent or bent.

In some optional embodiments, according to the packaging device provided by the above-mentioned embodiment of the present application, the filling material 4 is wrapped around the outside of the first chip component 2 and filled between the rewiring layer 1 and the chip component 2 and between the rewiring layer 1 and the chip component 2 . Between the wiring layer 1 and the substrate component 3 , the filling material 4 covers the first conductor line 12 , the second conductor line 22 and the third conductor line 32 .

In some optional embodiments, according to the packaging device provided by the above-mentioned embodiment of the present application, the filling material 4 is a capillary bottom filling material.

As shown in Figure 2, in some optional implementations, according to the packaging device provided by the above-mentioned embodiment of the present application, the rewiring layer 1 has a multi-layer structure, and each layer includes a first conductive circuit layer 14, a rewiring layer 14, and a first conductive circuit layer 14. The seed layer 15, the first conductive pillar 16 and the first dielectric layer 17, and the first conductive trace 14 located on the top of the package device form the first conductor layer 13. The thickness of each layer of the redistribution layer 1 of the multilayer structure is between 5 μm and 20 μm.

In some optional embodiments, according to the packaging device provided in the above embodiment of the present application, the chip component 2 further includes a chip 27 and a fan-out rewiring layer (not labeled) of a multi-layer structure. The fan-out layer of the multi-layer structure Each layer of the rewiring layer includes a second conductive circuit layer 23, a fan-out rewiring seed layer 24, a second conductive pillar 25 and a second dielectric layer 26. The chip 27 is located in one of the fan-out rewiring layers of the multi-layer structure. On one side, the second conductor pad 21 and the plurality of second conductor lines 22 are located on the other side of the fan-out redistribution layer of the multi-layer structure.

As shown in Figure 4, in some optional implementations, according to the packaging device provided by the above-mentioned embodiment of the present application, the substrate component 3 has a multi-layer structure, and each layer includes a third conductive circuit layer 34 and a substrate seed layer. 35. The third conductive pillar 36 and the third dielectric layer 37. The third conductive line 34 located at the bottom of the package device forms the second conductor layer 33. The thickness of each layer of the multilayer structure substrate component 3 is between several micrometers and tens of micrometers.

In some optional embodiments, according to the packaging device provided by the above-mentioned embodiment of the present application, the top of the packaging device is provided with a system packaging component 5. The system packaging component 5 includes electronic components 51 and molding materials 52. The molding The material 52 encapsulates the electronic component 51 , which is connected to the first conductor layer 13 on top of the redistribution layer 1 . The thickness of the system packaging component 5 ranges from hundreds of microns to several millimeters.

In some optional embodiments, according to the packaging device provided by the above-mentioned embodiment of the present application, the packaging device further includes solder balls 7 , and the solder balls 7 are connected to the second conductor layer 33 at the bottom of the substrate component 3 .

In some optional embodiments, according to the packaging device provided by the above-mentioned embodiment of the present application, the size (length and width) of the chip is between 20 μm and 200 μm.

In some optional embodiments, according to the packaging device provided by the above embodiment of the present application, there is a gap filled with the filling material 4 between the substrate component 3 and the redistribution layer 1 , and the width of the gap is between 5 μm and 20 μm. between.

In some optional embodiments, according to the packaging device provided by the above-mentioned embodiment of the present application, the size of the first conductor pad 11, the second conductor pad 21 and the third conductor pad 31 is between 1 μm and 15 μm; The distance between adjacent first conductor pads 11, adjacent second conductor pads 21 and adjacent third conductor points 31 is greater than 1 μm.

In some optional embodiments, according to the package device provided by the above-mentioned embodiment of the present application, the lengths of the first conductor line 12 , the second conductor line 22 and the third conductor are between several nanometers and hundreds of nanometers. .

In some optional embodiments, according to the packaging device provided by the above-mentioned embodiment of the present application, the diameter of the solder ball 7 is between 30 μm and 200 μm, and the spacing between adjacent solder balls 7 is between 50 μm and 400 μm. .

FIG. 6 shows a schematic diagram of the manufacturing process of the redistribution layer of the packaging device according to an embodiment of the present application. As shown in Figure 6, the manufacturing process of the rewiring layer of the package device includes multiple steps:

Step 1001: Provide a carrier board 101, set a release film 102 on the carrier board 101, set a patterned first conductor 103 on the release film, and the first conductor 103 is connected to the release film through the first seed layer 104;

Step 1002: Set up the first photoresist layer 105 covering the first conductor 103;

Step 1003: Etch the first photoresist layer 105 to form a first hole 106, and set a second seed layer 107 on the surface of the first photoresist layer 105 and the first hole 106;

Step 1004: Provide dielectric material 108 on the second seed layer 107;

Step 1005: Etch the dielectric material 108 to form the first groove 109, and electroplat the second conductor 110 in the first hole 106 and at the bottom of the first groove 109;

Step 1006: Remove dielectric material 108;

Step 1007: Set the dielectric layer 111 above the second conductor 110;

Step 1008: Set the second photoresist layer 112 above the dielectric layer 111;

Step 1009: Etch the second photoresist layer 112 to form a second hole 113, and set a third seed layer 114 on the surface of the second photoresist layer 112 and the second hole 113.

Step 1010: dispose dielectric material 108 on the third seed layer 114;

Step 1011: Etch the dielectric material 108 to form the second groove 115, and electroplat the third conductor 116 in the second hole 113 and at the bottom of the second groove 115;

Step 1012: Remove dielectric material 108; and

Step 1013: Form a redistribution layer disposed on the carrier board 101.

Figure 7 shows a schematic diagram of the manufacturing process of a packaging device according to an embodiment of the present application. As shown in Figure 7, the manufacturing process of the packaging device includes multiple steps:

Step 2001: Provide a rewiring layer 201; wherein the rewiring layer 201 includes a carrier board 210, and the rewiring layer 201 can be a rewiring layer obtained according to the manufacturing process shown in Figure 6;

Step 2002: Set the first chip component 202 on the rewiring layer 201;

Step 2003: Set the second chip component 203 on the rewiring layer 201;

Step 2004: Set the substrate component 204 on the redistribution layer 201; there may be multiple substrate components 204;

Step 2005: Inject the filling material 205 through the nozzle 213; the filling material 205 covers the first chip component 202 and the first chip component 203, and the filling material 205 is filled into the space between the first chip component 202 and the first chip component 203 and the rewiring layer 201 The filling material 205 fills the gap between the substrate component 204 and the redistribution layer 201;

Step 2006: Remove the carrier board 210 to form the first component 211;

Step 2007: Turn over the first component 211 and set the seed layer 206 on the rewiring layer 201;

Step 2008 to step 2009: Set electronic components 207 on the seed layer 206;

Step 2010: Use the molding material 208 to cover the electronic component 207 to form the second component 212;

Step 2011: Turn over the second component 212 to place the solder ball 209 on the substrate component 204; and

Step 2012: Cut the second component 212 to form a package device.

An electronic component 51 and a molding material 52 for covering the electronic component are disposed on the top of the packaging device of one embodiment shown in FIG. 1 . In actual applications, different devices or no device can be installed on the top of the packaging device according to requirements. Figure 8 shows a schematic diagram of a packaging device according to a second embodiment of the present application. As shown in FIG. 8 , the electronic components and the molding material used to cover the electronic components are not placed on the top of the packaging device. Figure 9 shows a schematic diagram of a packaging device according to a third embodiment of the present application. As shown in Figure 9, a fan-out stacked packaging component 301 is provided on the top. Figure 10 shows a schematic diagram of a packaging device according to a fourth embodiment of the present application. As shown in FIG. 10 , the packaging device only disposes the electronic component 302 without using the molding material 52 to cover the electronic component 302 . Figure 11 shows a schematic diagram of a packaging device according to a fifth embodiment of the present application. As shown in FIG. 11 , a filling material 303 is used to cover the electronic component 302 on the top of the packaging device. Figure 12 shows a schematic diagram of a packaging device according to a sixth embodiment of the present application. As shown in Figure 12, a thermal conductive sheet 304 is provided on the top of the packaging device.

Figure 1 shows an embodiment of a packaging device in which two chips 2 with different heights are provided and the two chips 2 are placed adjacent to each other. In actual applications, the number, height, size and placement of chips can be adjusted according to needs. Figure 13 shows a schematic diagram of a packaging device according to a seventh embodiment of the present application. As shown in Figure 13, two chips 305 with the same height are provided on the packaging device. Figure 14 shows a schematic diagram of a packaging device according to an eighth embodiment of the present application. As shown in Figure 14, a larger chip 305 is provided on the packaging device. Figure 15 shows a schematic diagram of a packaging device according to a ninth embodiment of the present application. As shown in FIG. 15 , two chips 305 with different heights are arranged separately, and a substrate component 306 is provided between the two chips 305 .

FIG. 16 shows a schematic diagram of a packaging device using panel level (PNL, Panel Level) packaging according to an embodiment of the present application. As shown in Figure 16, the packaging device is rectangular, and the chip 305 is disposed on the packaging device.

FIG. 17 shows a schematic diagram of a packaging device using wafer level (WL, Wafer Level) packaging according to an embodiment of the present application. As shown in Figure 17, the packaging device is circular, and the chip 305 is disposed on the packaging device.

The advantage of the packaging device according to the embodiment of the present application is that the use of conductor wires improves the connection strength between the rewiring layer and the chip and between the rewiring layer and the substrate component, thereby reducing the occurrence of cracks and necks in the packaging device during the production process. The probability of occurrence of problems such as shrinkage, breakage and deformation is reduced, thereby increasing the yield and reducing costs.

While the application has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not intended to limit the application. It will be apparent to those skilled in the art that various changes may be made and equivalent elements may be substituted within the embodiments without departing from the scope of the application as defined by the claims. Differences may exist between the technical representations in this application and actual devices due to manufacturing process variables and the like. There may be other embodiments of the application not specifically illustrated. The description and drawings are to be regarded as illustrative rather than restrictive, and may be modified in accordance with the purpose and spirit of the application, all such modifications being within the scope of the claims. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it should be understood that these operations may be recombined, subdivided, or arranged to form equivalent methods without departing from the teachings of this application. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit the application.

Claims (10)

1. A packaging apparatus, comprising:

a rewiring layer including a first conductor pad disposed on one side of the rewiring layer and a plurality of first conductor lines disposed on the first conductor pad;

a chip part including a second conductor pad and a plurality of second conductor lines, the second conductor pad being disposed at one side of the chip part, the chip part being disposed under the rewiring layer, the second conductor pad being parallel to the first conductor pad and disposed at a position opposite to the first conductor pad, the second conductor line being disposed on the second conductor pad and in contact with the first conductor line;

the width of the distribution area of the first conductor wire on the first conductor pad is larger than that of the distribution area of the second conductor wire on the second conductor pad.

2. The packaging device of claim 1, wherein the plurality of second conductor lines are in contact with a portion of the first conductor lines of the plurality of first conductor lines.

3. The package of claim 2, wherein the plurality of second conductor lines are in contact with first conductor lines disposed proximate a central portion of the first conductor pad.

4. The packaging device of claim 2, wherein the first conductor line that is not in contact with the second conductor line extends in the direction of the second conductor pad a distance exceeding a spacing between the first conductor pad and the second conductor pad.

5. The packaging device of claim 1, further comprising a substrate component including a third conductor pad and a plurality of third conductor lines, the third conductor pad disposed on one side of the substrate component, the third conductor lines disposed on the third conductor pad, the substrate component disposed below the redistribution layer, the third conductor pad being parallel to the first conductor pad and disposed at a position opposite the first conductor pad, the third conductor lines disposed on the third conductor pad and in contact with the first conductor lines, a width of a distribution area of the third conductor lines on the third conductor pad being greater than a width of a distribution area of the first conductor lines on the first conductor pad.

6. The package of claim 5, wherein the number of substrate members is greater than 1, recesses are formed between the substrate members, and the chip members are disposed in the recesses.

7. The packaging device of claim 6, wherein the first plurality of conductor lines are in contact with a portion of the third plurality of conductor lines.

8. The package of claim 7, wherein the plurality of first conductor lines contact a third conductor line disposed proximate a central portion of the third conductor pad.

9. The packaging device of claim 5, further comprising a filler material that encapsulates the first, second and third conductor lines and fills between the rewiring layer and the chip component and between the rewiring layer and the substrate component.

10. The packaging device of claim 9, wherein the filler material is a capillary underfill.