CN220456417U

CN220456417U - Packaging device

Info

Publication number: CN220456417U
Application number: CN202322017313.5U
Authority: CN
Inventors: 吕文隆
Original assignee: Advanced Semiconductor Engineering Inc
Current assignee: Advanced Semiconductor Engineering Inc
Priority date: 2023-07-17
Filing date: 2023-07-28
Publication date: 2024-02-06
Anticipated expiration: 2033-07-28

Abstract

The application provides a packaging device, which comprises a rerouting layer, wherein the rerouting layer comprises a first conductor pad and a plurality of first conductor wires, the first conductor pad is arranged on one side of the rerouting layer, and the first conductor wires are arranged on the first conductor pad; the chip component comprises a second conductor pad and a plurality of second conductor wires, the second conductor pad is arranged on one side of the chip component, the chip component is arranged below the rewiring layer, the second conductor pad is parallel to the first conductor pad, the second conductor pad is arranged at a position opposite to the first conductor pad, and the second conductor wires are arranged on the second conductor pad and are in contact with the first conductor wires; the width of the distribution area of the first conductor wire on the first conductor pad is larger than that of the distribution area of the second conductor wire on the second conductor pad. The application has the advantages that: the occurrence probability of problems such as cracking, necking, breakage, deformation and the like of the packaging device in the production process is reduced, and therefore the yield is improved and the cost is reduced.

Description

Packaging device

Technical Field

The present application relates to the field of semiconductors, and in particular, to a packaging apparatus.

Background

The Fan-out type chip-on-substrate packages (Fan-Out Chip on Substrate, FOCoS) and FOCoS-B (Fan-Out Chip on Substrate Bridge) are 2.5D/3D stacked packages, which are designed to provide high-speed transmission interconnect lines for a plurality of closely interconnected, fine-pitch (e.g., less than 300 μm) Die (Die), and to provide an integration scheme for Fan-out levels (FO-levels) for homogeneous/heterogeneous multi-chip products.

The prior art FOCoS and FOCoS-B require heating and pressure from the outside during the manufacturing process. Fig. 18 shows a schematic diagram of the stress during production using a prior art encapsulation device. As shown in fig. 18, external pressure is mainly applied to the middle portion of the encapsulation means, resulting in the encapsulation means being bent in the vertical direction, the broken line portion in fig. 18 schematically shows the direction in which the encapsulation means is bent, and the arrow portion indicates that the end portion of the encapsulation means is tilted in the vertical direction. Fig. 19 is a schematic view showing a problem that easily occurs in the production process of the packaging apparatus using the prior art as shown in fig. 18. Because the package device does not have sufficient strength to withstand the pressures it receives during production, misalignment between its redistribution layer (RDL, redistribution Layer) and the die, RDL and the substrate components, and problems such as cracking 401, deformation 402, breakage 403, and necking 404 may occur. The method reduces the yield, improves the production cost and reduces the income.

In view of the foregoing, there is a need in the art for a packaging device that overcomes the shortcomings of the prior art.

Disclosure of Invention

The present application provides a packaging device which can solve the problems of the prior art. The aim of the application is achieved by the following technical scheme.

One embodiment of the application provides a packaging device, which comprises a rerouting layer, a packaging layer and a packaging layer, wherein the rerouting layer comprises a first conductor pad and a plurality of first conductor wires, the first conductor pad is arranged on one side of the rerouting layer, and the first conductor wires are arranged on the first conductor pad; the chip component comprises a second conductor pad and a plurality of second conductor wires, the second conductor pad is arranged on one side of the chip component, the chip component is arranged below the rewiring layer, the second conductor pad is parallel to the first conductor pad, the second conductor pad is arranged at a position opposite to the first conductor pad, and the second conductor wires are arranged on the second conductor pad and are in contact with the first conductor wires; the width of the distribution area of the first conductor wire on the first conductor pad is larger than that of the distribution area of the second conductor wire on the second conductor pad.

In some alternative embodiments, the package device provided according to one of the above embodiments of the present application, wherein the plurality of second conductor lines are in contact with a portion of the plurality of first conductor lines.

In some alternative embodiments, a package device is provided according to one of the above embodiments of the present application, wherein the plurality of second conductor lines are in contact with first conductor lines disposed near a central portion of the first conductor pad.

In some alternative embodiments, the package device according to the above-described one embodiment of the present application is provided, wherein the first conductor line that is not in contact with the second conductor line extends in the direction of the second conductor pad by a distance exceeding the spacing between the first conductor pad and the second conductor pad.

In some optional embodiments, the package device provided according to the above one embodiment of the present application, wherein the package device further includes a substrate part, the substrate part includes a third conductor pad and a plurality of third conductor lines, the third conductor pad is disposed on one side of the substrate part, the third conductor line is disposed on the third conductor pad, the substrate part is disposed under the rewiring layer, the third conductor pad is parallel to the first conductor pad and is disposed at a position opposite to the first conductor pad, the third conductor line is disposed on the third conductor pad and is in contact with the first conductor line, and a width of a distribution area of the third conductor line on the third conductor pad is greater than a width of a distribution area of the first conductor line on the first conductor pad.

In some alternative embodiments, the package device provided according to the above-described one embodiment of the present application, wherein the number of the substrate members is greater than 1, grooves are formed between the substrate members, and the chip members are disposed in the grooves.

In some alternative embodiments, the package device provided according to the above-described one embodiment of the present application, wherein the plurality of first conductor lines are in contact with a portion of the plurality of third conductor lines.

In some alternative embodiments, the package device provided according to one of the above embodiments of the present application, wherein the plurality of first conductor lines are in contact with a third conductor line disposed near a central portion of the third conductor pad.

In some alternative embodiments, the package device provided according to the above one embodiment of the present application, wherein the filling material is wrapped around the outside of the first chip part and filled between the rewiring layer and the chip part and between the rewiring layer and the substrate part, and the filling material wraps around the first conductor line, the second conductor line, and the third conductor line.

In some alternative embodiments, the encapsulation device provided according to one of the above embodiments of the present application, wherein the filler material is a capillary underfill.

In some optional embodiments, according to the package device provided in one of the foregoing embodiments of the present application, the redistribution layer is a multilayer structure, and each layer includes a first conductive line layer, a redistribution seed layer, a first conductive pillar, and a first dielectric layer, and the first conductive line located on top of the package device forms a first conductor layer.

In some optional embodiments, the package device provided according to the above one embodiment of the present application, the chip part further includes a chip and a fan-out redistribution layer of a multilayer structure, each of the fan-out redistribution layers of the multilayer structure includes a second conductive line layer, a fan-out redistribution seed layer, a second conductive post, and a second dielectric layer, the chip is located on one side of the fan-out redistribution layer of the multilayer structure, and the second conductor pads and the plurality of second conductor lines are located on the other side of the fan-out redistribution layer of the multilayer structure.

In some alternative embodiments, according to the package device provided in one of the above embodiments of the present application, the substrate component is a multi-layer structure, and each layer includes a third conductive line layer, a substrate seed layer, a third conductive post, and a third dielectric layer, and the second conductive line at the bottom of the package device forms the second conductor layer.

In some alternative embodiments, the package device provided according to one of the above embodiments of the present application, wherein the top of the package device is provided with a system-in-package component comprising an electronic element and a molding material, the molding material encapsulating the electronic element, the electronic element being connected to the first conductor layer on top of the redistribution layer.

The packaging device according to the embodiment of the application has the advantages that: the conductor wires are used for improving the connection strength between the rewiring layer and the chip and between the rewiring layer and the substrate component, so that the occurrence probability of problems such as cracking, necking, breakage and deformation in the production process of the packaging device is reduced, the yield is improved, and the cost is reduced.

Drawings

Other features, objects and advantages of the present application will become more apparent from the detailed description of non-limiting embodiments thereof, which proceeds with reference to the accompanying drawings.

FIG. 1 shows a schematic view of a packaging apparatus according to one embodiment of the present application;

FIG. 2 shows an enlarged schematic view of a portion identified as A in the packaging device according to one embodiment of the present application as shown in FIG. 1;

FIG. 3 shows an enlarged schematic view of a portion identified as C in the packaging device according to one embodiment of the present application as shown in FIG. 2;

FIG. 4 shows an enlarged schematic view of a portion identified as B in the packaging device according to one embodiment of the present application as shown in FIG. 1;

FIG. 5 shows an enlarged schematic view of a portion identified as D in the packaging device according to one embodiment of the present application as shown in FIG. 4;

FIG. 6 illustrates a schematic diagram of a fabrication process of a rewiring layer of a packaged device according to one embodiment of the application;

FIG. 7 illustrates a schematic diagram of a manufacturing process of a packaging device according to one embodiment of the present application;

fig. 8 shows a schematic view of a packaging device according to a second embodiment of the present application;

fig. 9 shows a schematic view of a packaging device according to a third embodiment of the present application;

fig. 10 shows a schematic view of a packaging device according to a fourth embodiment of the present application;

fig. 11 shows a schematic view of a packaging device according to a fifth embodiment of the present application;

fig. 12 shows a schematic view of a packaging device according to a sixth embodiment of the present application;

fig. 13 shows a schematic view of a packaging device according to a seventh embodiment of the present application;

fig. 14 shows a schematic view of a packaging device according to an eighth embodiment of the present application;

fig. 15 shows a schematic view of a packaging device according to a ninth embodiment of the present application;

FIG. 16 shows a schematic diagram of a packaging apparatus using a Panel Level (PNL) package according to an embodiment of the present application;

FIG. 17 shows a schematic diagram of a packaging apparatus using Wafer Level (WL) packaging according to one embodiment of the present application;

FIG. 18 shows a schematic diagram of the force applied during production using a prior art encapsulation device;

fig. 19 is a schematic view showing a problem that easily occurs in the production process of the packaging apparatus using the prior art as shown in fig. 18.

Reference numerals and part names: 1-re-wiring layer, 11-first conductor pad, 12-first conductor line, 13-first conductor layer, 14-first conductive line layer, 15-re-wiring seed layer, 16-first conductive post, 17-first dielectric layer, 2-chip component, 21-second conductor pad, 22-second conductor line, 23-second conductive line layer, 24-fan-out re-wiring seed layer, 25-second conductive post, 26-second dielectric layer, 27-chip, 3-substrate component, 31-third conductor pad, 32-third conductor line, 33-second conductor layer, 34-third conductive line layer, 35-substrate seed layer, 36-third conductive post, 37-third dielectric layer, 4-filler material, 5-system-in-package components, 51-electronic components, 52-molding material, 6-recesses, 7-solder balls, 101-carrier, 102-release film, 103-first conductor, 104-first seed layer, 105-first photoresist layer, 106-first hole, 107-second seed layer, 108-dielectric material, 109-first recess, 110-second conductor, 111-dielectric layer, 112-second photoresist layer, 113-second hole, 114-third seed layer, 115-second recess, 116-third conductor, 201-redistribution layer, 202-first chip component, 203-second chip component, 204-substrate component, 205-fill material, 206-seed layer, 207-electronic components, 208-molding material, 209-solder balls, 210-carrier board, 211-first component, 212-second component, 213-nozzle, 301-fan-out stack package component, 302-electronic component, 303-filler material, 304-thermally conductive sheet, 305-chip component, 306-substrate component, 401-crack, 402-deformation, 403-fracture, 404-necking.

Detailed Description

The following description of the present application is given by way of example with reference to the accompanying drawings, and the technical solutions, problems to be solved and technical effects to be produced will be clearly and completely understood by those skilled in the art from the description of the present application. It is to be understood that the specific embodiments described herein are for purposes of illustration only and are not limiting. In addition, for convenience of description, only parts related to the present application are shown in the drawings.

It should be readily understood that the meanings of "on," "above," and "above" in this application should be interpreted in the broadest sense so that "on" means not only "directly on" but also "on" including intermediate components or layers that exist therebetween.

Further, spatially relative terms, such as "below," "under," "lower," "above," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element or component as illustrated in the figures. In addition to the orientations depicted in the drawings, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 ° or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The term "layer" as used herein refers to a portion of material that includes regions having a certain thickness. The layers may extend over the entire underlying or overlying structure, or may have a degree less than the extent of the underlying or overlying structure. Furthermore, the layer may be a region of homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure or between any pair of horizontal planes therebetween. The layers may extend horizontally, vertically and/or along a tapered surface. The substrate (substrate) may be a layer, may include one or more layers therein, and/or may have one or more layers thereon, and/or thereon. One layer may comprise multiple layers. For example, the semiconductor layer may include one or more doped or undoped semiconductor layers, and may have the same or different materials.

The term "substrate" as used herein refers to a material to which subsequent layers of material are added. The substrate itself may be patterned. The material added to the top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, sapphire wafer, polyamide fiber (PA), polyimide (PI), epoxy (Epoxy), poly-p-phenylene benzobisoxazole, PBO) fiber, FR-4 Epoxy glass laminate, PP (pre, prePreg or semi-cured resin, prePreg) or ABF (Ajinomoto Build-up Film) or the like. Further alternatively, the substrate may have a semiconductor device or a circuit formed therein.

The term "redistribution layer (RDL)" as used herein may be composed of conductive and Dielectric materials (Dielectric). It should be noted that the present disclosure is not limited thereto, and the re-wiring layer may be formed by using currently known or future developed re-wiring layer forming techniques, for example, but not limited to, photolithography, electroplating (plating), electroless plating (Electroless plating), and the like. Here, the dielectric material may include organic and/or inorganic matters, wherein the organic matters may be, for example: polyamide fibers (PA), polyimide (PI), epoxy resins (Epoxy), poly-p-phenylene benzobisoxazole, PBO) fibers, FR-4 Epoxy glass laminates, PP (pre reg, prePreg, or semi-cured resins, prepregs), ABF (Ajinomoto Build-up Film), etc., while the inorganic material may be, for example, silicon (Si), glass, ceramics (ceramic), silicon oxide, silicon nitride, tantalum oxide, etc. The conductive material may include a seed layer and a metal layer. Here, the seed layer may be, for example, titanium (Ti), tungsten (W), nickel (Ni), or the like, and the metal layer may be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or an alloy thereof.

The term "Die" as used herein may be various types of Die (i.e., die). The present disclosure is not particularly limited thereto. For example, logic function chips, memory chips, communication chips, microprocessor chips, graphics chips, microelectromechanical system (MEMS) chips, radio frequency chips, die or chip scale packages, interposers, or combinations thereof, and the like may be included.

It should be noted that, the structures, proportions, sizes, etc. shown in the drawings are merely used in conjunction with the descriptions of the embodiments and should not be construed as limiting the applicable limitations of the present application, so that any modification, variation of proportions, or adjustment of sizes of structures, proportions, etc. which are not intended to affect the efficacy of the present application or the objects achieved, are still within the scope of what is disclosed herein. Also, the terms "upper", "first", "second", and "a" and "an" as used in the present specification are merely for descriptive purposes and are not intended to limit the scope of the utility model in which the utility model may be practiced or their relative relationships may be altered or modified without materially altering the technical context.

It should be further noted that, in the embodiment of the present application, the corresponding longitudinal section may be a section corresponding to a front view direction, the corresponding transverse section may be a section corresponding to a right view direction, and the corresponding horizontal section may be a section corresponding to an upper view direction.

In addition, embodiments and features of embodiments in this application may be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Fig. 1 shows a schematic view of a packaging device according to one embodiment of the present application. Fig. 2 shows an enlarged schematic view of a portion identified as a in the packaging device according to one embodiment of the present application as shown in fig. 1. Fig. 3 shows an enlarged schematic view of a portion identified as C in the encapsulation device according to one embodiment of the present application as shown in fig. 2. Fig. 4 shows an enlarged schematic view of a portion identified as B in the encapsulation device according to one embodiment of the present application as shown in fig. 1. Fig. 5 shows an enlarged schematic view of a portion identified as D in the encapsulation device according to one embodiment of the present application as shown in fig. 4. As shown in fig. 1 to 5, the package device includes a re-wiring layer 1, the re-wiring layer 1 including a first conductor pad 11 and a plurality of first conductor lines 12, the first conductor pad 11 being disposed at one side of the re-wiring layer 1, the first conductor lines 12 being disposed on the first conductor pad 11; a chip part 2, the chip part 2 including a second conductor pad 21 and a plurality of second conductor lines 22, the second conductor pad 21 being disposed at one side of the chip part 2, the chip part 2 being disposed under the rewiring layer 1, the second conductor pad 21 being parallel to the first conductor pad 11 and the second conductor pad 21 being disposed at a position opposite to the first conductor pad 11, the second conductor line 22 being disposed on the second conductor pad 21 and the second conductor line 22 being in contact with the first conductor line 12, the first conductor line 12 and the second conductor line 22 fixedly connecting the rewiring layer 1 with the chip part 2 by being in contact with and wound around each other; the width of the first conductor line 12 in the area of the first conductor pad 11 is greater than the width of the second conductor line 22 in the area of the second conductor pad 21.

In some alternative embodiments, a package is provided according to one of the above embodiments of the present application, wherein the plurality of second conductor lines 22 are in contact with a portion of the plurality of first conductor lines 12.

In some alternative embodiments, a package device is provided according to one of the above embodiments of the present application, wherein the plurality of second conductor lines 22 are in contact with the first conductor lines 12 disposed near the central portion of the first conductor pad 11. The first conductor line 12 at the edge of the first conductor pad 11 is not in contact with the second conductor line 22.

In some alternative embodiments, the package device according to the above-described one embodiment of the present application is provided, wherein the first conductor line 12 which is not in contact with the second conductor line 22 extends in the direction of the second conductor pad 21 by a distance exceeding the spacing between the first conductor pad 11 and the second conductor pad 21.

In some alternative embodiments, a package device is provided according to one of the above embodiments of the present application, wherein the first conductor line 12 contacting the second conductor line 22 may be inclined, bent or folded, thereby bringing the first conductor line 12 into close contact with and firmly connected to the second conductor line 22.

In some alternative embodiments, the packaging device provided according to the above one embodiment of the present application, wherein the packaging device further includes a substrate member 3, the substrate member 3 includes a third conductor pad 31 and a plurality of third conductor lines 32, the third conductor pad 3 is disposed on one side of the substrate member 3, the third conductor line 32 is disposed on the third conductor pad 31, the substrate member 3 is disposed under the rewiring layer 1, the third conductor pad 31 is parallel to the first conductor pad 11 and the third conductor pad 31 is disposed at a position opposite to the first conductor pad 11, the third conductor line 32 is disposed on the third conductor pad 31 and the third conductor line 32 is in contact with the first conductor line 12, the first conductor line 12 and the third conductor line 32 fixedly connect the rewiring layer 1 with the substrate member 3 through mutual contact and winding, and a width of a distribution area of the third conductor line 32 on the third conductor pad 31 is larger than a width of a distribution area of the first conductor line 12 on the first conductor pad 11.

In some alternative embodiments, the package device provided according to the above-described one embodiment of the present application, wherein the number of the substrate members 3 is greater than 1, the grooves 6 are formed between the substrate members 3, and the chip members 2 are disposed in the grooves 6.

In some alternative embodiments, a package device is provided according to one of the above embodiments of the present application, wherein the plurality of first conductor lines 12 are in contact with a portion of the plurality of third conductor lines 32.

In some alternative embodiments, a package device is provided according to one of the above embodiments of the present application, wherein the plurality of first conductor lines 12 are in contact with a third conductor line 32 disposed near a central portion of the third conductor pad 31. The third conductor line 32 at the edge of the third conductor pad 31 is not in contact with the first conductor line 12.

In some alternative embodiments, the package device according to the above-described one embodiment of the present application is provided, wherein the third conductor line 32 that is not in contact with the first body line extends in the direction of the first conductor pad 11 by a distance exceeding the spacing between the first conductor pad 11 and the third conductor pad 31.

In some alternative embodiments, the encapsulation device provided according to one of the above embodiments of the present application, wherein the third conductor line 32 in contact with the first conductor line 12 may be inclined, bent or folded.

In some alternative embodiments, the package device provided according to the above-described one embodiment of the present application, wherein the filler material 4 is wrapped around the outside of the first chip part 2 and filled between the rewiring layer 1 and the chip part 2 and between the rewiring layer 1 and the substrate part 3, the filler material 4 wraps around the first conductor line 12, the second conductor line 22, and the third conductor line 32.

In some alternative embodiments, the encapsulation device provided according to one of the above embodiments of the present application, wherein the filler material 4 is a capillary underfill.

As shown in fig. 2, in some alternative embodiments, the package device provided according to the above-described embodiment of the present application, the redistribution layer 1 is a multi-layer structure, and each layer includes a first conductive trace layer 14, a redistribution seed layer 15, a first conductive pillar 16, and a first dielectric layer 17, where the first conductive trace 14 located on top of the package device forms a first conductive layer 13. The thickness of each layer of the multilayer structured rewiring layer 1 is between 5 μm and 20 μm.

In some alternative embodiments, the chip component 2 further includes a chip 27 and a multi-layer fan-out redistribution layer (not labeled) according to one embodiment of the present application, each of the multi-layer fan-out redistribution layer includes a second conductive trace layer 23, a fan-out redistribution seed layer 24, a second conductive post 25, and a second dielectric layer 26, the chip 27 is located on one side of the multi-layer fan-out redistribution layer, and the second conductor pads 21 and the plurality of second conductor lines 22 are located on the other side of the multi-layer fan-out redistribution layer.

As shown in fig. 4, in some alternative embodiments, the package device provided according to the above-described embodiment of the present application, the substrate part 3 has a multi-layer structure, and each layer includes a third conductive trace layer 34, a substrate seed layer 35, a third conductive post 36, and a third dielectric layer 37, and the third conductive trace 34 located at the bottom of the package device forms the second conductive layer 33. The thickness of each layer of the substrate member 3 of the multilayer structure is between several micrometers and several tens micrometers.

In some alternative embodiments, the package device according to the above-described one embodiment of the present application is provided, wherein the top of the package device is provided with a system package part 5, the system package part 5 comprising an electronic element 51 and a molding material 52, the molding material 52 encapsulating the electronic element 51, the electronic element 51 being connected to the first conductor layer 13 on top of the rewiring layer 1. The thickness of the system-in-package component 5 is between a few hundred micrometers and a few millimeters.

In some alternative embodiments, the package device according to one of the above embodiments of the present application is provided, wherein the package device further comprises solder balls 7, and the solder balls 7 are connected to the second conductor layer 33 at the bottom of the substrate part 3.

In some alternative embodiments, a package device is provided according to one of the above embodiments of the present application, wherein the dimensions (length and width) of the chip are between 20 μm and 200 μm.

In some alternative embodiments, a packaging device is provided according to one of the above embodiments of the present application, wherein a gap filled with the filling material 4 is present between the substrate part 3 and the redistribution layer 1, the gap having a width between 5 μm and 20 μm.

In some alternative embodiments, the package device provided according to the above-described one embodiment of the present application, wherein the first conductor pad 11, the second conductor pad 21, and the third conductor pad 31 have a size between 1 μm and 15 μm; the spacing between adjacent first conductor pads 11, adjacent second conductor pads 21 and adjacent third conductor points 31 is greater than 1 μm.

In some alternative embodiments, a package device is provided according to one of the above embodiments of the present application, wherein the first conductor line 12, the second conductor line 22, and the third conductor line are between a few nanometers and hundreds of nanometers in length.

In some alternative embodiments, a packaging device is provided according to one of the above embodiments of the present application, wherein the solder balls 7 have a diameter between 30 μm and 200 μm, and the pitch between adjacent solder balls 7 is between 50 μm and 400 μm.

Fig. 6 shows a schematic diagram of a fabrication process of a rewiring layer of a packaging device according to an embodiment of the application. As shown in fig. 6, the fabrication process of the rewiring layer of the package device includes a plurality of steps:

step 1001: providing a carrier plate 101, arranging a release film 102 on the carrier plate 101, arranging a patterned first conductor 103 on the release film, and connecting the first conductor 103 with the release film through a first seed layer 104;

step 1002: providing a first photoresist layer 105 covering the first conductor 103;

step 1003: etching the first photoresist layer 105 to form a first hole 106, and disposing a second seed layer 107 on the surfaces of the first photoresist layer 105 and the first hole 106;

step 1004: disposing a dielectric material 108 on the second seed layer 107;

step 1005: etching the dielectric material 108 to form a first recess 109, electroplating a second conductor 110 within the first hole 106 and at the bottom of the first recess 109;

step 1006: removing the dielectric material 108;

step 1007: disposing a dielectric layer 111 over the second conductor 110;

step 1008: disposing a second photoresist layer 112 over the dielectric layer 111;

step 1009: etching the second photoresist layer 112 to form a second hole 113, disposing a third seed layer 114 on the surfaces of the second photoresist layer 112 and the second hole 113,

step 1010: disposing a dielectric material 108 on the third seed layer 114;

step 1011: etching the dielectric material 108 to form a second recess 115, electroplating a third conductor 116 within the second hole 113 and at the bottom of the second recess 115;

step 1012: removing the dielectric material 108; and

step 1013: a rewiring layer provided on the carrier 101 is formed.

Fig. 7 shows a schematic view of a manufacturing process of a packaging device according to an embodiment of the present application. As shown in fig. 7, the manufacturing process of the packaging device includes a plurality of steps:

step 2001: providing a rewiring layer 201; the redistribution layer 201 includes a carrier 210, and the redistribution layer 201 may be a redistribution layer obtained according to the manufacturing process shown in fig. 6;

step 2002: a first chip component 202 is disposed on the rewiring layer 201;

step 2003: a second chip part 203 is provided on the rewiring layer 201;

step 2004: a substrate member 204 is provided on the rewiring layer 201; wherein the substrate member 204 may be plural;

step 2005: injecting the filling material 205 through the nozzle 213; the first chip part 202 and the first chip part 203 are covered by the filling material 205, the filling material 205 fills into the gaps between the first chip part 202 and the first chip part 203 and the rewiring layer 201, and the filling material 205 fills into the gaps between the substrate part 204 and the rewiring layer 201;

step 2006: removing the carrier 210 to form a first component 211;

step 2007: flipping the first component 211 places the seed layer 206 on the redistribution layer 201;

step 2008 to step 2009: disposing an electronic component 207 on the seed layer 206;

step 2010: the second component 212 is formed by covering the electronic element 207 with a molding material 208;

step 2011: flipping the second assembly 212 places solder balls 209 on the substrate member 204; and

step 2012: the second component 212 is diced to form packaged devices.

The top of the encapsulation device of one embodiment shown in fig. 1 is provided with electronic components 51 and a molding compound 52 for covering the electronic components. In practical application, the top of the packaging device can be provided with different devices or no device according to the requirements. Fig. 8 shows a schematic view of a packaging device according to a second embodiment of the present application. As shown in fig. 8, the electronic component and the molding material for covering the electronic component are not provided on the top of the package. Fig. 9 shows a schematic view of a packaging device according to a third embodiment of the present application. As shown in fig. 9, a fan-out stack package assembly 301 is disposed on top of it. Fig. 10 shows a schematic view of a packaging device according to a fourth embodiment of the present application. As shown in fig. 10, the encapsulation device only provides the electronic component 302 without covering the electronic component 302 with the molding material 52. Fig. 11 shows a schematic view of a packaging device according to a fifth embodiment of the present application. As shown in fig. 11, the electronic component 302 is encapsulated with a filler material 303 on top of the encapsulation device. Fig. 12 shows a schematic view of a packaging device according to a sixth embodiment of the present application. As shown in fig. 12, a thermally conductive sheet 304 is provided on top of the package.

Fig. 1 shows an embodiment of a package device in which two chips 2 of different heights are provided and two chips 2 are provided adjacently. In practical application, the number, height, size and setting position of the chips can be adjusted according to the requirements. Fig. 13 shows a schematic view of a packaging device according to a seventh embodiment of the present application. As shown in fig. 13, two chips 305 having the same height are provided on the package. Fig. 14 shows a schematic view of a packaging device according to an eighth embodiment of the present application. As shown in fig. 14, a larger chip 305 is provided on the package. Fig. 15 shows a schematic view of a packaging device according to a ninth embodiment of the present application. As shown in fig. 15, two chips 305 having different heights are separately provided, and a substrate member 306 is provided between the two chips 305.

Fig. 16 shows a schematic diagram of a packaging apparatus using a Panel Level (PNL) package according to one embodiment of the present application. As shown in fig. 16, the package is rectangular, and the chip 305 is disposed on the package.

Fig. 17 shows a schematic diagram of a packaging apparatus using Wafer Level (WL) packaging according to one embodiment of the present application. As shown in fig. 17, the package is circular, and the chip 305 is disposed on the package.

While the present application has been depicted and described with reference to particular embodiments thereof, such depicted and described are not meant to imply a limitation on the present application. It will be apparent to those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof within the embodiments thereof without departing from the scope of the application as defined in the claims. There may be a distinction between technical reproductions in this application and actual equipment due to variables in the manufacturing process, etc. Other embodiments of the present application not specifically described may exist. The specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present application. Although the methods disclosed herein have been described with reference to particular operations being performed in a particular order, it should be understood that these operations may be rearranged, sub-divided, or arranged to form an equivalent method without departing from the teachings of the present application. Thus, unless specifically indicated herein, the order and grouping of operations is not a limitation of the present application.

Claims

1. A packaging apparatus, comprising:

a rewiring layer including a first conductor pad disposed on one side of the rewiring layer and a plurality of first conductor lines disposed on the first conductor pad;

a chip part including a second conductor pad and a plurality of second conductor lines, the second conductor pad being disposed at one side of the chip part, the chip part being disposed under the rewiring layer, the second conductor pad being parallel to the first conductor pad and disposed at a position opposite to the first conductor pad, the second conductor line being disposed on the second conductor pad and in contact with the first conductor line;

the width of the distribution area of the first conductor wire on the first conductor pad is larger than that of the distribution area of the second conductor wire on the second conductor pad.

2. The packaging device of claim 1, wherein the plurality of second conductor lines are in contact with a portion of the first conductor lines of the plurality of first conductor lines.

3. The package of claim 2, wherein the plurality of second conductor lines are in contact with first conductor lines disposed proximate a central portion of the first conductor pad.

4. The packaging device of claim 2, wherein the first conductor line that is not in contact with the second conductor line extends in the direction of the second conductor pad a distance exceeding a spacing between the first conductor pad and the second conductor pad.

5. The packaging device of claim 1, further comprising a substrate component including a third conductor pad and a plurality of third conductor lines, the third conductor pad disposed on one side of the substrate component, the third conductor lines disposed on the third conductor pad, the substrate component disposed below the redistribution layer, the third conductor pad being parallel to the first conductor pad and disposed at a position opposite the first conductor pad, the third conductor lines disposed on the third conductor pad and in contact with the first conductor lines, a width of a distribution area of the third conductor lines on the third conductor pad being greater than a width of a distribution area of the first conductor lines on the first conductor pad.

6. The package of claim 5, wherein the number of substrate members is greater than 1, recesses are formed between the substrate members, and the chip members are disposed in the recesses.

7. The packaging device of claim 6, wherein the first plurality of conductor lines are in contact with a portion of the third plurality of conductor lines.

8. The package of claim 7, wherein the plurality of first conductor lines contact a third conductor line disposed proximate a central portion of the third conductor pad.

9. The packaging device of claim 5, further comprising a filler material that encapsulates the first, second and third conductor lines and fills between the rewiring layer and the chip component and between the rewiring layer and the substrate component.

10. The packaging device of claim 9, wherein the filler material is a capillary underfill.