CN220440403U - Charging circuit, charger and intelligent terminal - Google Patents

Abstract

The application provides a charging circuit, a charger and an intelligent terminal, wherein the charging circuit comprises an interface and a switch assembly; the interface is provided with at least one power supply pin and at least one communication pin group, and the communication pin group is used for transmitting communication data; the switch component is arranged on an electric transmission path between the communication pin group and the power supply pin; the switch component is connected with the processor and is used for being conducted or disconnected according to a control signal issued by the processor. Through the technical scheme, the charging efficiency is improved, and the charging circuit is simple and easy to realize.

Description

Charging circuit, charger and intelligent terminal

Technical Field

The application relates to the technical field of charging, in particular to a charging circuit, a charger and an intelligent terminal.

Background

In the field of charging technology, charging efficiency is generally improved by a dedicated charger and charging wire. In some schemes, in order to improve the charging efficiency, the charger and the charging line generally reduce the impedance of the power pin VBUS and the ground pin GND in the charging circuit as much as possible, which requires that the power pin VBUS and the ground pin GND be widened as much as possible, and even the wiring of the corresponding connection of the two pins be widened as much as possible.

In the process of designing and implementing the present application, the inventors found that at least the following problems exist: the wiring space on the motherboard in the charging device is limited, and it is difficult to realize the required pin and wiring width. Therefore, it is currently difficult to arrange the pins and the wiring widths required for high charging efficiency in a limited wiring space, and the charging power is limited due to the aggravation of heat generation caused by the high charging efficiency.

The foregoing description is provided for general background information and does not necessarily constitute prior art.

Disclosure of Invention

To above-mentioned technical problem, this application provides a charging circuit, charger and intelligent terminal, can improve charging efficiency, and charging circuit is simple easy to realize.

The application provides a charging circuit, including: the interface is provided with at least one power supply pin and at least one communication pin group, and the communication pin group is used for transmitting communication data; the switch assembly is arranged on an electric transmission path between the communication pin group and the power supply pin; the switch component is connected with the processor and used for being connected or disconnected according to a control signal issued by the processor.

Optionally, the switch assembly includes a MOS tube, a control end of the MOS tube is connected to the processor, one of an input end and an output end of the MOS tube is connected to the power supply pin, and the other is connected to the communication pin set.

Optionally, the communication pin group includes at least two communication pins, and at least one communication pin is connected with the MOS tube.

Optionally, the power supply pin includes a power supply pin and a ground pin; the switch component comprises a first MOS tube and a second MOS tube; the communication pin group comprises a first communication pin group and a second communication pin group; the power supply pin and the first communication pin group are connected with the first MOS tube; the grounding pin and the second communication pin group are connected with the second MOS tube.

Optionally, the switch assembly includes a chip, the power supply pin and the communication pin group are connected with a first pin of the chip, and a second pin of the chip is connected with the processor.

Optionally, the chip is provided with a third MOS transistor, a control end of the third MOS transistor is connected to the processor, one of an input end and an output end of the third MOS transistor is connected to the power supply pin, the other is connected to the communication pin group, and/or the chip is provided with a timing controller, and a pin of the chip is connected to the timing controller.

Optionally, the power supply pin includes a power supply pin and a ground pin; the chip comprises a first chip and a second chip; the communication pin group comprises a first communication pin group and a second communication pin group; the power supply pin and the pins of the first communication pin group are connected with the first chip; the grounding pin and the pins of the second communication pin group are connected with the second chip.

Optionally, the switch assembly includes a triode, a base of the triode is connected with the processor, one of a collector and an emitter of the triode is connected with the power supply pin, and the other is connected with the communication pin group.

Optionally, the switch assembly includes a switch, a first diode and a second diode connected in parallel to one of the power supply pin and the communication pin set; the switch includes a first end and a second end, the first end being connected with the other of the power pin and the communication pin set; the switch is connected with the processor, and the second end is connected with the first diode and/or the second end is connected with the second diode through a control signal of the processor.

Optionally, the current directions of the first diode and the second diode are opposite.

Optionally, the interface further includes a protocol pin, where the protocol pin is connected to the processor, and is used to establish a communication connection between the processor and the external device when the interface plugs into the external device.

Optionally, the processor and the switch component are connected through a GPIO port.

The application provides a charger, including the charging circuit as above.

The application provides an intelligent terminal, including the charging circuit and/or the charger as above.

As described above, the charging circuit of the present application includes an interface provided with at least one power supply pin and at least one communication pin group, and a switch assembly provided on an electrical transmission path between the communication pin group and the power supply pin; the switch component is turned on or off according to a control signal issued by the processor, so that the conduction or disconnection of an electric transmission path between the communication pin group and the corresponding power supply pin is controlled. When in charging, the electric transmission path formed by the communication pin group and the corresponding power supply pins is used as a charging loop, which is equivalent to using the data transmission channel as the charging loop, so that the impedance of the charging loop can be reduced, the overcurrent capacity is increased, the heating is reduced while the charging efficiency is improved, the influence on the charging power is reduced, and the utilization rate of the data transmission channel can be increased; in addition, the charging circuit does not need to increase the width of pins and wires required for charging, and is simple and easy to realize.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application. In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, and it will be obvious to those skilled in the art that other drawings can be obtained from these drawings without inventive effort.

Fig. 1 is a schematic hardware structure of a mobile terminal implementing various embodiments of the present application;

fig. 2 is a schematic structural diagram of a charging circuit according to a first embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of a plug outlet and a socket of a Type-C interface based on USB3.0 protocol;

fig. 4 is a schematic structural diagram of a current transmission path established between a charger and an intelligent terminal according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of a charging circuit according to a second embodiment of the present disclosure;

fig. 6 is an equivalent schematic diagram of a charging circuit of a charger according to an embodiment of the present application;

fig. 7 is an equivalent schematic diagram of a charging circuit of an intelligent terminal according to an embodiment of the present application;

fig. 8 is a schematic structural diagram of a charging circuit according to a third embodiment of the present disclosure;

fig. 9 is an equivalent schematic diagram of a charging circuit of another charger according to the embodiment of the present application;

fig. 10 is an equivalent schematic diagram of a charging circuit of another intelligent terminal according to an embodiment of the present application;

fig. 11 is a schematic structural diagram of a charging circuit according to a fourth embodiment of the present disclosure;

fig. 12 is a schematic structural diagram of a charging circuit according to a fourth embodiment of the present application.

The realization, functional characteristics and advantages of the present application will be further described with reference to the embodiments, referring to the attached drawings. Specific embodiments thereof have been shown by way of example in the drawings and will herein be described in more detail. These drawings and the written description are not intended to limit the scope of the inventive concepts in any way, but to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as detailed in the accompanying claims.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the element defined by the phrase "comprising one … …" does not exclude the presence of additional identical elements in a process, method, article, or apparatus that comprises the element, and alternatively, elements having the same name in different embodiments of the present application may have the same meaning or may have different meanings, a particular meaning of which is to be determined by its interpretation in this particular embodiment or further in connection with the context of this particular embodiment.

It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, these information should not be limited by these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope herein. The word "if" as used herein may be interpreted as "at … …" or "at … …" or "responsive to a determination", depending on the context. Furthermore, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and/or "including" specify the presence of stated features, steps, operations, elements, components, items, categories, and/or groups, but do not preclude the presence, presence or addition of one or more other features, steps, operations, elements, components, items, categories, and/or groups. The terms "or," "and/or," "including at least one of," and the like, as used herein, may be construed as inclusive, or meaning any one or any combination. For example, "including at least one of: A. b, C "means" any one of the following: a, A is as follows; b, a step of preparing a composite material; c, performing operation; a and B; a and C; b and C; a and B and C ", again as examples," A, B or C "or" A, B and/or C "means" any of the following: a, A is as follows; b, a step of preparing a composite material; c, performing operation; a and B; a and C; b and C; a and B and C). An exception to this definition will occur only when a combination of elements, functions, steps or operations are in some way inherently mutually exclusive.

It should be understood that, although the steps in the flowcharts in the embodiments of the present application are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited in order and may be performed in other orders, unless explicitly stated herein. Moreover, at least some of the steps in the figures may include multiple sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, the order of their execution not necessarily occurring in sequence, but may be performed alternately or alternately with other steps or at least a portion of the other steps or stages.

The words "if", as used herein, may be interpreted as "at … …" or "at … …" or "in response to a determination" or "in response to a detection", depending on the context. Similarly, the phrase "if determined" or "if detected (stated condition or event)" may be interpreted as "when determined" or "in response to determination" or "when detected (stated condition or event)" or "in response to detection (stated condition or event), depending on the context.

It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.

In the following description, suffixes such as "module", "component", or "unit" for representing elements are used only for facilitating the description of the present application, and are not of specific significance per se. Thus, "module," "component," or "unit" may be used in combination.

The intelligent terminal may be implemented in various forms. For example, the smart terminals described in the present application may include smart terminals such as cell phones, tablet computers, notebook computers, palm computers, personal digital assistants (Personal Digital Assistant, PDA), portable media players (Portable Media Player, PMP), navigation devices, wearable devices, smart bracelets, pedometers, and stationary terminals such as digital TVs, desktop computers, and the like.

The following description will be given taking a mobile terminal as an example, and those skilled in the art will understand that the configuration according to the embodiment of the present application can be applied to a fixed type terminal in addition to elements particularly used for a moving purpose.

Referring to fig. 1, which is a schematic hardware structure of a mobile terminal implementing various embodiments of the present application, the mobile terminal 100 may include: an RF (Radio Frequency) unit 101, a WiFi module 102, an audio output unit 103, an a/V (audio/video) input unit 104, a sensor 105, a display unit 106, a user input unit 107, an interface unit 108, a memory 109, a processor 110, and a power supply 111. Those skilled in the art will appreciate that the mobile terminal structure shown in fig. 1 is not limiting of the mobile terminal and that the mobile terminal may include more or fewer components than shown, or may combine certain components, or a different arrangement of components.

The following describes the components of the mobile terminal in detail with reference to fig. 1:

the radio frequency unit 101 may be used for receiving and transmitting signals during the information receiving or communication process, specifically, after receiving downlink information of the base station, processing the downlink information by the processor 110; and, the uplink data is transmitted to the base station. Typically, the radio frequency unit 101 includes, but is not limited to, an antenna, at least one amplifier, a transceiver, a coupler, a low noise amplifier, a duplexer, and the like. In addition, the radio frequency unit 101 may also communicate with networks and other devices via wireless communications. The wireless communication may use any communication standard or protocol including, but not limited to, GSM (Global System of Mobile communication, global system for mobile communications), GPRS (General Packet Radio Service ), CDMA2000 (Code Division Multiple Access, 2000, CDMA 2000), WCDMA (Wideband Code Division Multiple Access ), TD-SCDMA (Time Division-Synchronous Code Division Multiple Access, time Division synchronous code Division multiple access), FDD-LTE (Frequency Division Duplexing-Long Term Evolution, frequency Division duplex long term evolution), TDD-LTE (Time Division Duplexing-Long Term Evolution, time Division duplex long term evolution), and 5G, among others.

WiFi belongs to a short-distance wireless transmission technology, and a mobile terminal can help a user to send and receive e-mails, browse web pages, access streaming media and the like through the WiFi module 102, so that wireless broadband Internet access is provided for the user. Although fig. 1 shows a WiFi module 102, it is understood that it does not belong to the necessary constitution of a mobile terminal, and can be omitted entirely as required within a range that does not change the essence of the invention.

The audio output unit 103 may convert audio data received by the radio frequency unit 101 or the WiFi module 102 or stored in the memory 109 into an audio signal and output as sound when the mobile terminal 100 is in a call signal reception mode, a talk mode, a recording mode, a voice recognition mode, a broadcast reception mode, or the like. Also, the audio output unit 103 may also provide audio output (e.g., a call signal reception sound, a message reception sound, etc.) related to a specific function performed by the mobile terminal 100. The audio output unit 103 may include a speaker, a buzzer, and the like.

The a/V input unit 104 is used to receive an audio or video signal. The a/V input unit 104 may include a graphics processor (Graphics Processing Unit, GPU) 1041 and a microphone 1042, the graphics processor 1041 processing image data of still pictures or video obtained by an image capturing device (e.g., a camera) in a video capturing mode or an image capturing mode. The processed image frames may be displayed on the display unit 106. The image frames processed by the graphics processor 1041 may be stored in the memory 109 (or other storage medium) or transmitted via the radio frequency unit 101 or the WiFi module 102. The microphone 1042 can receive sound (audio data) via the microphone 1042 in a phone call mode, a recording mode, a voice recognition mode, and the like, and can process such sound into audio data. The processed audio (voice) data may be converted into a format output that can be transmitted to the mobile communication base station via the radio frequency unit 101 in the case of a telephone call mode. The microphone 1042 may implement various types of noise cancellation (or suppression) algorithms to cancel (or suppress) noise or interference generated in the course of receiving and transmitting the audio signal.

The mobile terminal 100 also includes at least one sensor 105, such as a light sensor, a motion sensor, and other sensors. Optionally, the light sensor includes an ambient light sensor and a proximity sensor, optionally, the ambient light sensor may adjust the brightness of the display panel 1061 according to the brightness of ambient light, and the proximity sensor may turn off the display panel 1061 and/or the backlight when the mobile terminal 100 moves to the ear. As one of the motion sensors, the accelerometer sensor can detect the acceleration in all directions (generally three axes), and can detect the gravity and direction when stationary, and can be used for applications of recognizing the gesture of a mobile phone (such as horizontal and vertical screen switching, related games, magnetometer gesture calibration), vibration recognition related functions (such as pedometer and knocking), and the like; as for other sensors such as fingerprint sensors, pressure sensors, iris sensors, molecular sensors, gyroscopes, barometers, hygrometers, thermometers, infrared sensors, etc. that may also be configured in the mobile phone, the detailed description thereof will be omitted.

The display unit 106 is used to display information input by a user or information provided to the user. The display unit 106 may include a display panel 1061, and the display panel 1061 may be configured in the form of a liquid crystal display (Liquid Crystal Display, LCD), an Organic Light-Emitting Diode (OLED), or the like.

The user input unit 107 may be used to receive input numeric or character information and to generate key signal inputs related to user settings and function control of the mobile terminal. Alternatively, the user input unit 107 may include a touch panel 1071 and other input devices 1072. The touch panel 1071, also referred to as a touch screen, may collect touch operations thereon or thereabout by a user (e.g., operations of the user on the touch panel 1071 or thereabout by using any suitable object or accessory such as a finger, a stylus, etc.) and drive the corresponding connection device according to a predetermined program. The touch panel 1071 may include two parts of a touch detection device and a touch controller. Optionally, the touch detection device detects the touch azimuth of the user, detects a signal brought by touch operation, and transmits the signal to the touch controller; the touch controller receives touch information from the touch detection device, converts it into touch point coordinates, and sends the touch point coordinates to the processor 110, and can receive and execute commands sent from the processor 110. Further, the touch panel 1071 may be implemented in various types such as resistive, capacitive, infrared, and surface acoustic wave. The user input unit 107 may include other input devices 1072 in addition to the touch panel 1071. Alternatively, other input devices 1072 may include, but are not limited to, one or more of a physical keyboard, function keys (e.g., volume control keys, switch keys, etc.), a trackball, mouse, joystick, etc., as specifically not limited herein.

Alternatively, the touch panel 1071 may overlay the display panel 1061, and when the touch panel 1071 detects a touch operation thereon or thereabout, the touch panel 1071 is transferred to the processor 110 to determine the type of touch event, and the processor 110 then provides a corresponding visual output on the display panel 1061 according to the type of touch event. Although in fig. 1, the touch panel 1071 and the display panel 1061 are two independent components for implementing the input and output functions of the mobile terminal, in some embodiments, the touch panel 1071 may be integrated with the display panel 1061 to implement the input and output functions of the mobile terminal, which is not limited herein.

The interface unit 108 serves as an interface through which at least one external device can be connected with the mobile terminal 100. For example, the external devices may include a wired or wireless headset port, an external power (or battery charger) port, a wired or wireless data port, a memory card port, a port for connecting a device having an identification module, an audio input/output (I/O) port, a video I/O port, an earphone port, and the like. The interface unit 108 may be used to receive input (e.g., data information, power, etc.) from an external device and transmit the received input to one or more elements within the mobile terminal 100 or may be used to transmit data between the mobile terminal 100 and an external device.

Memory 109 may be used to store software programs as well as various data. The memory 109 may mainly include a storage program area and a storage data area, and alternatively, the storage program area may store an operating system, an application program required for at least one function (such as a sound playing function, an image playing function, etc.), and the like; the storage data area may store data (such as audio data, phonebook, etc.) created according to the use of the handset, etc. In addition, memory 109 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other volatile solid-state storage device.

The processor 110 is a control center of the mobile terminal, connects various parts of the entire mobile terminal using various interfaces and lines, and performs various functions of the mobile terminal and processes data by running or executing software programs and/or modules stored in the memory 109 and calling data stored in the memory 109, thereby performing overall monitoring of the mobile terminal. Processor 110 may include one or more processing units; preferably, the processor 110 may integrate an application processor and a modem processor, the application processor optionally handling mainly an operating system, a user interface, an application program, etc., the modem processor handling mainly wireless communication. It will be appreciated that the modem processor described above may not be integrated into the processor 110.

The mobile terminal 100 may further include a power source 111 (e.g., a battery) for supplying power to the respective components, and preferably, the power source 111 may be logically connected to the processor 110 through a power management system, so as to perform functions of managing charging, discharging, and power consumption management through the power management system.

Although not shown in fig. 1, the mobile terminal 100 may further include a bluetooth module or the like, which is not described herein.

Based on the above-mentioned mobile terminal hardware structure, various embodiments of the present application are presented.

First embodiment

Referring to fig. 2, fig. 2 is a schematic structural diagram of a charging circuit according to a first embodiment, where the charging circuit according to the embodiment of the present application includes: an interface 12 and a switch assembly 13.

The switch assembly 13 is used as a control type or controlled type electronic component, and needs to receive and execute corresponding on or off according to a control signal, wherein the control signal can be generated and issued by a processor in an electronic device such as an intelligent terminal suitable for the charging circuit, the charging circuit can also comprise a processor 11, or the electronic device such as the intelligent terminal suitable for the charging circuit is provided with the processor 11, and the switch assembly 13 is directly or indirectly connected with the processor 11.

The interface 12 is provided with at least one power supply pin 121 and at least one communication pin set 122, the power supply pin 121 being used for supplying current and the communication pin set 122 being used for transmitting communication data. The switch assembly 13 is disposed on the electrical path between each communication pin set 122 and the corresponding power supply pin 121.

The switch assembly 13 is connected to the processor 11, and is configured to be turned on or off according to a control signal issued by the processor 11, so as to control the on or off of an electrical transmission path between each communication pin group 122 and the corresponding power supply pin 121.

In this embodiment, during charging, the electrical transmission path where the communication pin group 122 and the corresponding power supply pin 121 are located is used as a charging circuit, which is equivalent to using a data transmission channel as the charging circuit, so that the impedance of the charging circuit can be reduced, and the overcurrent capability can be increased. The charging efficiency is improved, the heat generation is reduced, the influence on the charging power is reduced, and the utilization rate of the data transmission channel can be increased. And the charging circuit is simple and easy to realize without increasing the widths of pins and corresponding wires required for charging.

In one embodiment, the switch assembly 13 defaults to off in a default state or an initial state (which may be that no control signal issued by the processor 11 is received); if the switch component 13 receives a first control signal issued by the processor 11, the switch component is turned on; if the switch component 13 receives the second control signal issued by the processor 11, the switch component is turned off. The processor 11 may be a CPU (Central Processing Unit ) or an MCU (Microcontroller Unit, micro control unit).

Alternatively, the number of communication pin sets 122 and the number of power supply pins 121 may be adapted according to the type of charging interface 12. Optionally, referring to fig. 3, the upper diagram is a schematic structural diagram of a plug outlet of the Type-C interface 12 based on the USB3.0 protocol, and the lower diagram is a schematic structural diagram of a socket end of the Type-C interface 12; the Type-C interface 12 is provided with 2 communication pin sets 122, which are respectively a first communication pin set including pin TX1- (also known as pin TXP 1), pin TX1+ (also known as pin TXP 2), pin RX1- (also known as pin RXP 1), pin RX1+ (also known as pin RXP 2), and a second communication pin set including pin TX2- (also known as pin TXN 1), pin TX2+ (also known as pin TXN 2), pin RX2- (also known as pin RXN 1), pin RX2+ (also known as pin RXN 2). The power supply pins 121 of the Type-C interface 12 are four power supply pins VBUS and four ground pins GND, respectively. One transmission channel of the Type-C interface 12 includes a power pin VBUS, a ground pin GND, and a pair of input/output pins, such as pins TX 1-and RX1-. In the Type-C interface 12 of the Type shown in fig. 3, the names, functions and arrangement order of the pins (also called pin pins) can be referred to in the prior art, and are not described herein.

Optionally, the interface 12 may further comprise a protocol pin (not shown in fig. 2) in communication with the processor 11 for establishing a communication connection between the processor 11 and an external device (e.g. a smart terminal) based on a communication protocol when the interface 12 is plugged into the external device. Alternatively, in a Type-C interface 12 of the Type shown in FIG. 3, the protocol pins may be pin SUB1 and pin SUB2.

The switch assembly 13 is added in the charging loop, and the default state of the switch assembly 13 is off. After the intelligent terminal and the charger are connected, the intelligent terminal and the charger are identified through a charging protocol, after the communication handshake, the processor 11 issues control signals to each switch component 13, for example, in a scene that the processor 11 and the switch components 13 are connected through General-purpose input/output (GPIO) ports, the control signals are GPIO signals; the switch assembly 13 is conductive to conduct the electrical transmission paths between pins TX1-, TX2-, RX1-, and RX 2-respectively with the corresponding power supply pin VBUS, and to conduct the electrical transmission paths between pins TX1+, TX2+, RX1+, and RX2+ respectively with the corresponding ground pin GND. In this regard, the present application may be regarded as indirectly increasing the widths of the power supply pin VBUS and the ground pin GND, and the corresponding wiring, so as to reduce the dc resistance of the entire charging circuit, and achieve the purpose of improving the overcurrent capability and the charging efficiency.

As shown in connection with fig. 4, the charging is an action of establishing a current transmission path between the charger 1 and the smart terminal 2, and thus the charging circuit may be provided to the charger 1 and/or the smart terminal 2.

Optionally, taking the example that the charger 1 is provided with the charging circuit, firstly, a charging head of the charger 1 is plugged with a power supply, two ends of a charging wire of the charger 1 are respectively provided with an interface 12, the interface 12 at one end of the charging wire is connected with the charging head, and the interface 12 at the other end is connected with the intelligent terminal 2. The Type-C interface 12 based on the USB3.0 protocol may support a low version of the USB2.0 protocol, so that a data transmission channel may be established between the charger 1 and the intelligent terminal 2 based on the USB2.0 protocol and invoking a corresponding pin, where the data transmission channel is at least used for a communication handshake and a communication connection between the processor 11 of the charger 1 and the processor 11 of the intelligent terminal 2. After the communication connection is successful, the charger 1 and the intelligent terminal 2 (the respective processor 11) respectively control the respective switch components 13 to be switched to the on state, and then the intelligent terminal 2 enters the charging state.

The processor 11 of the charger 1 may be provided in the charging head, or may be provided in the charging wire by multiplexing the existing main board of the charging head, for example, in a small chip built in the end of the charging wire. The processor 11 of the intelligent terminal 2 may be an existing motherboard or a motherboard with a recharging port.

Second embodiment

Referring to fig. 5, fig. 5 is a schematic structural diagram of a charging circuit according to a second embodiment, where the charging circuit of the present embodiment includes: processor 11, interface 12 including power supply pin 121 and communication pin set 122, and MOS transistor 13. That is, the present embodiment realizes the switch assembly 13 by a MOS transistor. Alternatively, the charging circuit may be provided without the processor 11, and the processor 11 may be provided in an electronic device such as an intelligent device to which the charging circuit is applied.

Optionally, a control end of the MOS transistor 13 is connected to the processor 11, one of an input end and an output end of the MOS transistor 13 is connected to the power supply pin 121, and the other is connected to the communication pin set 122.

Alternatively, in the scenario shown in fig. 5, the MOS transistor 13 is an N-type MOS transistor, the control end of the MOS transistor 13 is the gate electrode g, one of the input end and the output end of the MOS transistor 13 is the source electrode s, and the other is the drain electrode d. Alternatively, as shown in fig. 6, when the charging circuit is disposed in the charger 1, the source electrode s of the MOS transistor 13 is used as an input end and connected to a corresponding pin of the communication pin group 122, and the drain electrode d of the MOS transistor 13 is used as an output end and connected to a corresponding power supply pin 121. Alternatively, as shown in fig. 7, when the charging circuit is disposed in the intelligent terminal 2, the source electrode s of the MOS transistor 13 is used as an input end and connected to the corresponding power supply pin 121, and the drain electrode d of the MOS transistor 13 is used as an output end and connected to the corresponding pin of the communication pin set 122.

With continued reference to fig. 6, the charger 1 is provided with a Type-C interface 12 based on the USB3.0 protocol, and the Type-C interface 12 may be provided with 24 pins, namely 12 pins A1-a 12 on one side and 12 pins B1-B12 on the other side. The names, actions and arrangement order of the pins can be referred to in the prior art, and are not described herein.

The communication pin set 122 of the Type-C interface 12 includes a first communication pin set and a second communication pin set. Optionally, the first communication pin group includes pins TXP1 and RXP1, pins TXP2 and RXP2; the second communication pin group includes pins TXN1 and RXN1, and pins TXN2 and RXN2. The power supply pins 121 of the Type-C interface 12 are four power supply pins VBUS and four ground pins GND, respectively.

In each communication pin group 122, each pin is connected to an output end (i.e., drain electrode d) of the same MOS transistor 13. As shown in fig. 6, the charging circuit is provided with 8 MOS transistors 13, respectively denoted by Q1 to Q8. The 8 MOS transistors 13 may be divided into a first MOS transistor 13 and a second MOS transistor 13, optionally, MOS transistors Q8, Q2, Q1, and Q3 are respectively referred to as a first MOS transistor 13, and MOS transistors Q4, Q6, Q5, and Q7 are respectively referred to as a second MOS transistor 13. The power supply pin VBUS and the pins of the first communication pin group are connected with the first MOS tube 13; the ground pin GND and the pins of the second communication pin group are connected to the second MOS transistor 13. Each first MOS tube 13 is a MOS tube with the same type or the same specification, each second MOS tube 13 is a MOS tube with the same type or the same specification, and parameters such as channels of the MOS tubes with the same type or the same specification are the same, so that the method is beneficial to batch design and production.

Optionally, the pin TXP1 is connected to a source electrode of the MOS transistor Q8, a drain electrode of the MOS transistor Q8 is connected to a power supply pin VBUS, and a gate electrode of the MOS transistor Q8 is connected to the processor 11 through a GPIO port. The pin TXN1 is connected with a source electrode of the MOS tube Q4, a drain electrode of the MOS tube Q4 is connected with a grounding pin GND, and a gate electrode of the MOS tube Q4 is connected with the processor 11 through a GPIO port. The pin RXN2 is connected with the source electrode of the MOS tube Q5, the drain electrode of the MOS tube Q5 is connected with a grounding pin GND, and the gate electrode of the MOS tube Q5 is connected with the processor 11 through the GPIO port. The pin RXP2 is connected with the source electrode of the MOS tube Q1, the drain electrode of the MOS tube Q1 is connected with a power supply pin VBUS, and the gate electrode of the MOS tube Q1 is connected with the processor 11 through a GPIO port. The pin RXP1 is connected with the source electrode of the MOS tube Q2, the drain electrode of the MOS tube Q2 is connected with a power supply pin VBUS, and the gate electrode of the MOS tube Q2 is connected with the processor 11 through the GPIO port. The pin RXN1 is connected with a source electrode of the MOS tube Q6, a drain electrode of the MOS tube Q6 is connected with a grounding pin GND, and a gate electrode of the MOS tube Q6 is connected with the processor 11 through a GPIO port. The pin TXN2 is connected with the source electrode of the MOS tube Q7, the drain electrode of the MOS tube Q7 is connected with a grounding pin GND, and the gate electrode of the MOS tube Q7 is connected with the processor 11 through the GPIO port. The pin TXP2 is connected with the source electrode of the MOS tube Q3, the drain electrode of the MOS tube Q3 is connected with a power supply pin VBUS, and the gate electrode of the MOS tube Q3 is connected with the processor 11 through the GPIO port.

Optionally, the communication pins on the same side may share a ground pin GND, optionally, the pins TXN1 and RXN2 share a ground pin GND, and the pins RXN1 and TXN2 share a ground pin GND. Alternatively, the 8 MOS transistors Q1 to Q8 may share one GPIO port and be connected to the processor 11.

During charging, the processor 11 issues a control signal through the GPIO port to control the conduction of the MOS transistors Q1 to Q8, the conduction of an electric transmission path between the pin TXP1 and the power supply pin VBUS, and the conduction of an electric transmission path between the pin TXN1 and the ground pin GND; an electrical transmission path between the pin RXN2 and the ground pin GND is conductive, and an electrical transmission path between the pin RXP2 and the power supply pin VBUS is conductive; an electrical transmission path between the pin RXP1 and the power supply pin VBUS is conductive, and an electrical transmission path between the pin RXN1 and the ground pin GND is conductive; the electrical transmission path between pin TXN2 and ground pin GND is conductive and the electrical transmission path between pin TXP2 and power pin VBUS is conductive. Here, the data transmission channel is used as a charging loop.

Referring to fig. 7, in a scenario in which the charging circuit is disposed in the intelligent terminal 2, the intelligent terminal 2 is provided with a Type-C interface 12 based on the USB3.0 protocol, the Type-C interface 12 is provided with 42 pins, and names, functions and arrangement sequences of the pins can refer to the prior art, which is not repeated herein. The charging circuit may also be provided with 8 MOS transistors 13, respectively numbered Q9 to Q16. The 8 MOS transistors 13 may be divided into a first MOS transistor 13 and a second MOS transistor 13, optionally, MOS transistors Q9, Q11, Q10, and Q12 are respectively referred to as a first MOS transistor 13, and MOS transistors Q13, Q15, Q14, and Q16 are respectively referred to as a second MOS transistor 13. The power supply pin VBUS and the pins of the first communication pin group are connected with the first MOS tube 13; the ground pin GND and the pins of the second communication pin group are connected to the second MOS transistor 13.

The pin TXP1 is connected with a source electrode of the MOS tube Q9, a drain electrode of the MOS tube Q9 is connected with a power supply pin VBUS, and a gate electrode of the MOS tube Q9 is connected with the processor 11 through a GPIO port; the pin TXN2 is connected with a source electrode of the MOS tube Q13, a drain electrode of the MOS tube Q13 is connected with a ground pin GND, and a gate electrode of the MOS tube Q13 is connected with the processor 11 through a GPIO port; the pin TXN1 is connected with a source electrode of the MOS tube Q14, a drain electrode of the MOS tube Q14 is connected with a ground pin GND, and a gate electrode of the MOS tube Q14 is connected with the processor 11 through a GPIO port; the pin TXP2 is connected with the source electrode of the MOS tube Q10, the drain electrode of the MOS tube Q10 is connected with a power supply pin VBUS, and the gate electrode of the MOS tube Q10 is connected with the processor 11 through a GPIO port; the pin RXP1 is connected with a source electrode of the MOS tube Q11, a drain electrode of the MOS tube Q11 is connected with a power supply pin VBUS, and a gate electrode of the MOS tube Q11 is connected with the processor 11 through a GPIO port; the pin RXN2 is connected with a source electrode of the MOS tube Q15, a drain electrode of the MOS tube Q15 is connected with a ground pin GND, and a gate electrode of the MOS tube Q15 is connected with the processor 11 through a GPIO port; the pin RXN1 is connected with a source electrode of the MOS tube Q16, a drain electrode of the MOS tube Q16 is connected with a ground pin GND, and a gate electrode of the MOS tube Q16 is connected with the processor 11 through a GPIO port; the pin RXP2 is connected with the source electrode of the MOS tube Q12, the drain electrode of the MOS tube Q12 is connected with a power supply pin VBUS, and the gate electrode of the MOS tube Q12 is connected with the processor 11 through the GPIO port. Alternatively, the communication pins on the same side may share a ground pin GND, for example, pin TXN1 and pin RXN2 share a ground pin GND, and pin RXN1 and pin TXN2 share a ground pin GND. The 8 MOS transistors Q9 to Q16 may share one GPIO port and be connected to the processor 11.

During charging, the processor 11 issues a control signal through the GPIO port to control the MOS transistors Q9 to Q16 to be turned on, and each communication pin is turned on with an electrical transmission path between the corresponding power supply pin VBUS or ground pin GND, where the data transmission channel is used as a charging loop.

In other scenarios, different from those shown in fig. 6 and fig. 7, in the single communication pin group 122, a plurality of pins may be set to be connected with the same MOS tube 13, so that the number of MOS tubes 13 may be reduced, the occupation space of electronic components is further reduced, and the charging circuit is simpler and easier to implement.

Third embodiment

Referring to fig. 8, fig. 8 is a schematic diagram of a charging circuit according to a third embodiment, and the charging circuit of the present embodiment also includes a processor 11 and an interface 12 including a power supply pin 121 and a communication pin set 122. Alternatively, the charging circuit may be provided without the processor 11, and the processor 11 may be provided in an electronic device such as an intelligent device to which the charging circuit is applied. In this embodiment, the switch assembly 13 includes a chip 13, pins corresponding to the power supply pins 121 and the communication pin group 122 are connected to a first pin of the chip 13, and a second pin of the chip 13 is connected to the processor 11. The first pin may be a data transmission pin of the chip 13, and the second pin may be an enable pin, which is also called a control signal input terminal or an enable control terminal, and is used for transmitting control signals only but not communication data, wherein the communication data is transmitted by the data transmission pin of the chip 13.

At least two control elements 131 and at least two pins are integrated on a single chip 13, and may therefore also be referred to as an integrated chip. The number of control members 131 and pins may be determined according to the actual scene adaptation, for example, in the scene shown in fig. 8, each chip 13 includes 4 control members 131 and 12 pins (respectively numbered 1 to 12).

Each control member 131 may be provided with three ports, namely, a control end E, an input end Y and an output end Z, where the control end E is connected to the GPIO port through a pin of the chip 13, so as to be connected to the processor 11, the input end Y is connected to a corresponding power supply pin 121, and the output end Z is connected to a pin corresponding to the communication pin set 122.

Referring to fig. 9, in a scenario where the charging circuit is disposed in the charger 1, the charging circuit may also be provided with 2 chips 13, which are a first chip U1 and a second chip U2, respectively.

The charger 1 includes a first communication pin group and a second communication pin group. Optionally, the first communication pin group includes pins TXP1 and RXP1, pins TXP2 and RXP2; the second communication pin group includes pins TXN1 and RXN1, and pins TXN2 and RXN2.

The power supply pin VBUS and the pins of the first communication pin group are connected with the first chip U1; the ground pin GND and the pins of the second communication pin group are both connected to the second chip U2.

In one embodiment, as shown in fig. 9, the power pin VBUS is connected to pins 9 to 12 of the first chip U1, so as to connect the input terminals Y of the control elements 131 on the first chip U1; the pin TXP1 is connected with the pin 3 of the first chip U1, the pin RXP1 is connected with the pin 1 of the first chip U1, the pin TXP2 is connected with the pin 7 of the first chip U1, and the pin RXP2 is connected with the pin 5 of the first chip U1 so as to be respectively connected with the output ends Z of the corresponding control pieces 131; the control end E of each control piece 131 on the first chip U1 is connected with the GPIO ports through pins 2, 4, 6 and 8 of the first chip U1 respectively, so as to be connected with the processor 11 of the charger 1; the ground pin GND is connected to pins 1, 3, 5, 7 of the second chip U2, so as to connect the output terminals Z of the respective control elements 131 on the second chip U2; the pin RXN1 is connected with the pin 9 of the second chip U2, the pin TXN1 is connected with the pin 10 of the second chip U2, the pin RXN2 is connected with the pin 11 of the second chip U2, and the pin TXN2 is connected with the pin 12 of the second chip U2 so as to be respectively connected with the input end Y of the corresponding control piece 131; the control end E of each control member 131 on the second chip U2 is connected to the GPIO port through pins 2, 4, 6, 8 of the second chip U2, respectively, so as to be connected to the processor 11 of the charger 1.

In an embodiment, as shown in fig. 10, in a scenario where the charging circuit is disposed in the intelligent terminal 2, the charging circuit may also be provided with 2 chips 13, which are a first chip U3 and a second chip U4, respectively.

The intelligent terminal 2 includes a first communication pin group and a second communication pin group. Optionally, the first communication pin group includes pins TXP1 and RXP1, pins TXP2 and RXP2; the second communication pin group includes pins TXN1 and RXN1, and pins TXN2 and RXN2.

The power supply pin VBUS is connected with pins 9-12 of the first chip U3, so that the power supply pin VBUS is connected with the input end Y of each control piece 131 on the first chip U3; the pin TXP1 is connected with the pin 3 of the first chip U3, the pin RXP1 is connected with the pin 1 of the first chip U3, the pin TXP2 is connected with the pin 7 of the first chip U3, and the pin RXP2 is connected with the pin 5 of the first chip U3 so as to be respectively connected with the output ends Z of the corresponding control pieces 131; the control end E of each control piece 131 on the first chip U3 is connected with the GPIO ports through pins 2, 4, 6 and 8 of the first chip U3 respectively, so as to be connected with the processor 11 of the intelligent terminal 2; the ground pin GND is connected to pins 1, 3, 5, 7 of the second chip U4, so as to connect the output terminals Z of the respective control elements 131 on the second chip U4; the pin RXN2 is connected with the pin 9 of the second chip U2, the pin TXN2 is connected with the pin 10 of the second chip U2, the pin TXN1 is connected with the pin 11 of the second chip U2, and the pin RXN1 is connected with the pin 12 of the second chip U2 so as to be respectively connected with the input end Y of the corresponding control piece 131; the control end E of each control piece 131 on the second chip U4 is connected with the GPIO ports through pins 2, 4, 6 and 8 of the second chip U4 respectively, so as to be connected with the processor 11 of the intelligent terminal 2.

In an embodiment, the chip 13 may be provided with a MOS transistor, and in order to distinguish from the first MOS transistor 13 and the second MOS transistor 13, the MOS transistor herein may be referred to as a third MOS transistor, and the control element 131 is formed by the third MOS transistor. For example, the gate electrode of the N-type third MOS transistor may be the control end E of the control element 131, the source electrode of the N-type third MOS transistor may be the input end Y of the control element 131, and the drain electrode of the N-type third MOS transistor may be the output end Z of the control element 131.

In another embodiment, the chip 13 may be provided with a timing controller, and the pins of the chip 13 are connected to the timing controller, and the timing controller is connected to the GPIO ports through the corresponding pins of the chip 13, so as to be connected to the processor 11. The timing controller may be used to transmit the control signal issued by the processor 11 for a predetermined period of time, so that the above-described control of on and off can be achieved.

Fourth embodiment

Referring to fig. 11, fig. 11 is a schematic diagram of a charging circuit according to a fourth embodiment, and the difference is that, based on the description of any of the foregoing embodiments, the switch assembly 13 of the present embodiment includes a transistor, a base B of the transistor is connected to the processor, one of a collector C and an emitter E of the transistor is connected to the power supply pin 121, and the other is connected to the communication pin set 122.

Alternatively, in the case where the charging circuit is provided in the charger 1 of the foregoing second and third embodiments, for example, the emitter E of each transistor is connected to each pin of the communication pin group 122, and the collector C of each transistor is connected to the corresponding power supply pin VBUS and ground pin GND.

Alternatively, in the case where the charging circuit is provided in the smart terminal 2 of the foregoing second and third embodiments, for example, the emitter E of each transistor is connected to the power supply pin VBUS and the ground pin GND, and the collector C of each transistor is connected to each pin of the communication pin group 122.

During charging, the processor 11 issues a control signal through the GPIO port to control the transistors to be turned on, and the electrical transmission path between each communication pin and the corresponding power pin VBUS or ground pin GND is turned on, where the data transmission channel is used as a charging loop.

Optionally, the switch assembly 13 of the present embodiment includes a switch 132, a first diode 133 and a second diode 134. The switch 132 may be an alternative switch, including a first end and a second end. The first diode 133 and the second diode 134 are connected in parallel between the power supply pin 121 and the communication pin group 122. The current directions of the first diode 133 and the second diode 134 are opposite, i.e., the anode of the first diode 133 is connected to the power supply pin 121, and the cathode of the second diode 134 is connected to the power supply pin 121.

One ends of the first diode 133 and the second diode 134 are connected to one of the power supply pin 121 and the communication pin group 122, a first end of the switch 132 is connected to the other of the power supply pin 121 and the communication pin group 122, the switch 132 is connected to the processor 11, and the second end is connected to the first diode 133 or the second end is connected to the second diode 132 according to a control signal of the processor 11.

Optionally, if the switch 132 receives the first control signal sent by the processor 11, the second end is connected to the first diode 133; if the switch 132 receives the second control signal from the processor 11, the second terminal is connected to the second diode 132. It can be seen that only one diode is connected between the first diode 133 and the second diode 134 at the same time, and when the current direction between the power supply pin 121 and the communication pin group 122 is from the positive pole to the negative pole of the connected diode, the diode conducts the electrical transmission path between the power supply pin 121 and the communication pin group 122, and the switch assembly 13 is in a conducting state; when the current between the power supply pin 121 and the communication pin group 122 flows from the negative electrode to the positive electrode of the turned-on diode, the resistance of the diode is infinite, and it can be regarded that the electric transmission path between the power supply pin 121 and the communication pin group 122 is disconnected, and the switch assembly 13 is in the off state.

Referring to fig. 12, when charging, the processor 11 issues a control signal to the switch 132 through the GPIO port, and for the scenario in which the charging circuit is disposed in the intelligent terminal 2, the charging current direction is from the power supply pin 121 toward the communication pin group 122, and if the processor 11 controls the second end of the switch 132 to be connected to the cathode of the first diode 133, the switch component 13 is in a conductive state; if the processor 11 controls the second terminal of the switch 132 to be connected to the cathode of the second diode 134, the switch assembly 13 is in an off state.

For the case that the charging circuit is disposed in the charger 1, the charging current is directed from the communication pin group 122 to the power supply pin 121, and if the second end of the control switch 132 of the processor 11 is connected to the cathode of the first diode 133, the switch assembly 13 is in an off state; if the processor 11 controls the second terminal of the switch 132 to be connected to the cathode of the second diode 134, the switch assembly 13 is in a conductive state.

The embodiment of the application also provides a charger, which comprises the charging circuit in any of the previous embodiments.

The embodiment of the application also provides an intelligent terminal, which comprises the charging circuit in any one of the embodiments.

The embodiment of the application also provides a chip comprising the charging circuit in any of the above embodiments.

Therefore, at least one of the charger, the intelligent terminal and the chip has the beneficial effects of the charging circuit of the corresponding embodiment.

It can be understood that the above scenario is merely an example, and does not constitute a limitation on the application scenario of the technical solution provided in the embodiments of the present application, and the technical solution of the present application may also be applied to other scenarios. For example, as one of ordinary skill in the art can know, with the evolution of the system architecture and the appearance of new service scenarios, the technical solutions provided in the embodiments of the present application are equally applicable to similar technical problems.

The foregoing embodiment numbers of the present application are merely for describing, and do not represent advantages or disadvantages of the embodiments.

The units in the device of the embodiment of the application can be combined, divided and pruned according to actual needs.

In this application, the same or similar term concept, technical solution, and/or application scenario description will generally be described in detail only when first appearing, and when repeated later, for brevity, will not generally be repeated, and when understanding the content of the technical solution of the present application, etc., reference may be made to the previous related detailed description thereof for the same or similar term concept, technical solution, and/or application scenario description, etc., which are not described in detail later.

In this application, the descriptions of the embodiments are focused on, and the details or descriptions of one embodiment may be found in the related descriptions of other embodiments.

The technical features of the technical solutions of the present application may be arbitrarily combined, and for brevity of description, all possible combinations of the technical features in the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the present application.

The foregoing description is only of the preferred embodiments of the present application, and is not intended to limit the scope of the claims, and all equivalent structures or equivalent processes using the descriptions and drawings of the present application, or direct or indirect application in other related technical fields are included in the scope of the claims of the present application.

Claims (10)

1. A charging circuit, comprising:

the interface is provided with at least one power supply pin and at least one communication pin group, and the communication pin group is used for transmitting communication data;

the switch assembly is arranged on an electric transmission path between the communication pin group and the power supply pin; the switch component is connected with the processor and used for being connected or disconnected according to a control signal issued by the processor.

2. The charging circuit of claim 1, wherein the switch assembly comprises a MOS transistor, a control terminal of the MOS transistor is connected to the processor, one of an input terminal and an output terminal of the MOS transistor is connected to the power supply pin, and the other is connected to the communication pin set.

3. The charging circuit of claim 2, wherein the power pin comprises a power pin and a ground pin; the switch component comprises a first MOS tube and a second MOS tube; the communication pin group comprises a first communication pin group and a second communication pin group;

the power supply pin and the first communication pin group are connected with the first MOS tube; the grounding pin and the second communication pin group are connected with the second MOS tube.

4. The charging circuit of claim 1, wherein the switch assembly comprises a chip, the power pin and the set of communication pins are connected to a first pin of the chip, and a second pin of the chip is connected to the processor.

5. The charging circuit as claimed in claim 4, wherein the chip is provided with a third MOS transistor _， The control end of the third MOS tube is connected with the processor, one of the input end and the output end of the third MOS tube is connected with the power supply pin, and the other is connected with the communication pin group; and/or the number of the groups of groups,

The chip is provided with a time sequence controller, and pins of the chip are connected with the time sequence controller.

6. The charging circuit of claim 4, wherein the power pin comprises a power pin and a ground pin; the chip comprises a first chip and a second chip; the communication pin group comprises a first communication pin group and a second communication pin group;

the power supply pin and the first communication pin group are connected with the first chip; the grounding pin and the second communication pin group are connected with the second chip.

7. The charging circuit of any one of claims 1 to 6, wherein the switch assembly comprises a triode, a base of the triode being connected to the processor, one of a collector and an emitter of the triode being connected to the supply pin, the other being connected to the communication pin set; and/or the number of the groups of groups,

the switch assembly includes a switch, a first diode, and a second diode connected in parallel to one of the supply pin and the communication pin set; the switch includes a first end and a second end, the first end being connected with the other of the power pin and the communication pin set; the switch is connected with the processor, and the second end is connected with the first diode and/or the second end is connected with the second diode through a control signal of the processor.

8. The charging circuit of any one of claims 1 to 6, wherein the interface further comprises a protocol pin connected to the processor for establishing a communication connection between the processor and an external device when the interface is plugged into the external device.

9. A charger comprising a charging circuit as claimed in any one of claims 1 to 8.

10. An intelligent terminal comprising a charging circuit as claimed in any one of claims 1 to 8.