CN220439617U - Chip layout structure and memory integrated chip - Google Patents

Abstract

The utility model discloses a chip layout structure and a memory integrated chip, which comprises: the chip carrier comprises a chip carrier body, a plurality of mesh areas and a plurality of first I/O units, wherein the mesh areas and the first I/O units are arranged on the chip carrier body, the first I/O units are arranged on one side of the mesh areas and correspond to the mesh areas, the first I/O units comprise the first I/O units, the first I/O units are arranged in a straight line, and the first I/O units are arranged on two opposite sides of the chip carrier body. According to the chip layout and storage integrated chip, the input and output units related to the mesh are arranged and distributed adjacent to the mesh, so that the effect of saving the using area of the chip is achieved.

Description

Chip layout structure and memory integrated chip

Technical Field

The utility model relates to the technical field of chip processing, in particular to a chip layout structure and a memory integrated chip.

Background

In large-scale integrated circuit design, the chip area is large, a plurality of modules exist on the chip, if the module layout is unreasonable, the chip area utilization rate is low, wherein the interface layout has an especially large influence on the utilization rate of the ultra-large-scale integrated circuit design, and the traditional I/O layout is distributed around the chip.

Disclosure of Invention

The utility model aims to provide a chip layout structure and a memory integrated chip so as to save the use area of the chip.

In order to achieve the above object, according to one aspect of the present utility model, there is provided a chip layout structure comprising: the chip carrier, a plurality of mesh areas and a plurality of first I/O units, wherein the plurality of mesh areas and the plurality of first I/O units are arranged on the chip carrier,

the first I/O unit is arranged on one side of the mesh area and corresponds to the mesh area, the first I/O unit comprises a plurality of first I/Os which are arranged into a straight line, and the first I/O units are arranged on two opposite sides of the chip carrier.

Optionally, a PLL area and a second I/O unit are also included, wherein the PLL area and the second I/O unit are both disposed on the chip carrier,

the PLL area and the second I/O unit are arranged in the middle of the chip carrier, the second I/O unit is arranged on one side of the PLL area and corresponds to the PLL area, the second I/O unit comprises a plurality of second I/Os which are arranged in a straight line, and a plurality of mesh areas are arranged on two sides of the area where the PLL area and the second I/O unit are located.

Optionally, the mesh area includes at least one sub-module, and the shape of the sub-module is irregular.

Optionally, the method further comprises an EFUSE area and a third I/O unit, wherein the EFUSE area is arranged in the middle of the chip carrier, the third I/O unit corresponds to the EFUSE area, the EFUSE area is arranged on one side of the PLL area, and the third I/O unit corresponding to the EFUSE area is arranged on one side of the EFUSE area.

Optionally, the plurality of mesh areas include a first mesh area and a second mesh area adjacent to the first mesh area, and the arrangement of the sub-modules in the first mesh area and the arrangement of the sub-modules in the second mesh area are axisymmetric with a central axis between the first mesh area and the second mesh area.

Optionally, each of the first I/os corresponds to a sub-module closest to the first I/O.

Optionally, the method further includes that the wiring resistance between the second I/O unit and the PLL is smaller than the resistance requirement of the PLL, and the wiring resistance between the third I/O unit and the EFUSE is smaller than the resistance requirement of the EFUSE, wherein the wiring resistance= (azimuth resistance value×wiring length/wiring width).

Optionally, the chip carrier further comprises a fourth I/O unit, wherein the fourth I/O unit is arranged in the middle of the chip carrier, and comprises a plurality of fourth I/Os which are arranged in a straight line with the first I/Os.

Optionally, the method further comprises at least one first bleeder circuit and at least one second bleeder circuit, the first bleeder circuit is arranged between the second I/O unit and the PLL, the second bleeder circuit is arranged between the third I/O unit and the EFUSE area, the number of the first bleeder circuits is determined according to the number of power supplies supplying the PLL, and the number of the second bleeder circuits is determined according to the number of power supplies supplying the EFUSE.

According to another aspect of the present utility model, there is provided a memory integrated chip including a logic chip and a memory chip having the chip layout structure as described above, the logic chip and the memory chip being packaged in a 3D stack package.

According to the chip layout structure and the memory integrated chip, the input and output units related to the mesh are arranged and distributed adjacent to the mesh, so that the effect of saving the using area of the chip is achieved. Further, by the distributed design of the plurality of IO units, the area of the area required by the second I/O unit 140 is reduced, meanwhile, the power consumption and noise of the chip are reduced, and the time sequence performance of the chip is improved.

Drawings

FIG. 1 is a schematic diagram of a chip layout structure according to some embodiments of the present utility model;

FIG. 2 is a schematic diagram of a layout of a PLL area and a second I/O cell in accordance with some embodiments of the present utility model;

FIG. 3 is a schematic diagram of an EFUSE domain and third I/O cell layout according to some embodiments of the utility model;

fig. 4 is a schematic structural diagram of a mesh layout according to some embodiments of the present utility model;

fig. 5 is a schematic structural diagram of a memory integrated chip according to some embodiments of the utility model.

Detailed Description

Fig. 1 is a schematic structural diagram of a chip layout structure according to some embodiments of the present application, where the chip shown in fig. 1 includes: a chip carrier, a plurality of mesh areas, a first I/O unit 120, a PLL area 130, and a second I/O unit 140, wherein the plurality of mesh areas, the first I/O unit 120, the PLL area 130, and the second I/O unit 140 are all disposed on the chip carrier, wherein,

the first I/O units 120 are in one-to-one correspondence with the mesh area, the first I/O units 120 are disposed on one side of the mesh area, the first I/O units 120 include a plurality of first I/os 121, the plurality of first I/os 121 are arranged in a straight line, and the first I/O units 120 are disposed on two opposite sides of the chip carrier.

The chip in this embodiment of the present application includes a control chip and a logic chip, as shown in fig. 1, there are 4 mesh areas on the chip carrier, where the first I/O units 120 adjacent to the mesh areas are mainly used for inputting and outputting signals, where two first I/O units 120 are disposed on edge portions at a line a as shown in the drawing, and the other two first I/O units 120 are disposed on edge portions at a line B as shown in the drawing, where the line a and the line B are two opposite sides of the chip carrier, each mesh includes a plurality of sub-modules 111, i.e. blocks, the logic circuits and the control modules of the first I/O121 are placed in the corresponding sub-modules 111, and each I/O is distributed around the chip in a shortest distance, so that the I/O units in the prior art need to reach the mesh through a long distance, and the occupied area of the chip is relatively large.

Fig. 2 is a schematic structural diagram of layout of a PLL area 130 and a second I/O unit 140 according to some embodiments of the present application, as shown in fig. 2, the PLL (phase locked loop, chip delay locked loop) area 130 and the second I/O unit 140 are disposed in the middle of the chip carrier, the second I/O unit 140 corresponds to the PLL area 130, the second I/O unit 140 is disposed on one side of the PLL area 130, the second I/O unit 140 includes a plurality of second I/os 141, the plurality of second I/os 141 are aligned, and a plurality of mesh areas are disposed on both sides of the PLL area 130 and the area where the second I/O unit 140 is located.

According to some embodiments of the present application, as shown in fig. 1, PLL area 130 is an area on a chip carrier for setting a PLL, PLL area 130 is set in the center of the chip carrier, because the area of the chip is large, in the prior art, I/O is set on the periphery of the chip carrier, so that the area of the chip is increased, and meanwhile, a large noise is generated.

Fig. 2 is a schematic structural diagram of a layout of a PLL area 130 and a second I/O unit 140 according to some embodiments of the present application, as shown in fig. 2, at least one Clamp210, that is, at least one first bleeder circuit, is disposed between the PLL area 130 and the second I/O unit 140, the Clamp210 has an ESD (Electro-Static discharge) function, and the second I/O unit 140 is subjected to electrostatic protection, where the number of the Clamp210 is determined according to the number of power supplies for supplying power to the PLL area 130, and the Clamp210 is used for simulating a high-voltage power supply for supplying power to the PLL.

According to a specific embodiment of the present application, the power supply is provided to the PLL through the second I/O unit 140 and then through Clamp, and the power supply has three sets of power supplies, namely, 1 set of analog voltage VDDHV, 2 sets of digital voltages VDDREF and vddppost, and a total of 3 clamps 210 need to be added between each power supply and ground.

On one hand, the PLL is sensitive to noise, so that independent I/O layout can play a role in isolating digital noise, on the other hand, the PLL is high in power supply requirement, and the I/O for supplying power to the PLL is placed on the side of the PLL, so that the power supply wiring resistance can be effectively reduced, the voltage drop is reduced, and sufficient voltage is provided for the PLL.

The trace resistance between the second I/O unit 140 and the PLL is smaller than the resistance requirement of the PLL, trace resistance= (azimuth resistance value x trace length/trace width).

According to some embodiments of the chip layout structure of the present application, as shown in fig. 1, the chip layout structure further includes an EFUSE160 area disposed in a middle portion of the chip carrier and a third I/O unit 170, wherein the third I/O unit 170 corresponds to the EFUSE area 160, the EFUSE area 160 is disposed on a second side of the PLL area 130, and the third I/O unit 170 corresponding to the EFUSE area 160 is disposed on one side of the EFUSE area.

In this application, EFUSE160 is a one-time programmable memory, for the I/O of EFUSE160 is also placed beside EFUSE, the requirement of EFUSE160 for power supply is very high, the power supply supplies power to EFUSE through third I/O unit 170, and if third I/O unit 170 is far away from EFUSE, the routing resistance between third I/O unit 170 and EFUSE is very large, so that a very large voltage drop is generated, the requirement of power supply to EFUSE cannot be met, and distributing third I/O unit 170 on the edge of EFUSE can effectively reduce the routing resistance of power supply, reduce the voltage drop, and provide sufficient voltage for EFUSE.

FIG. 3 is a schematic diagram of the layout of an EFUSE field 160 and a third I/O cell 170 according to some embodiments of the present application, the EFUSE power supply comprising 2 sets of power supplies and 1 GND. I/O of EFUSE signal and placement of power supply need to satisfy the wiring resistance < resistance requirement of EFUSE, where wiring resistance= (azimuth resistance value×wiring length/wiring width).

In this embodiment of the present application, at least one second bleeder circuit 310 is also included, the second bleeder circuit 310 being disposed between the third I/O cell 170 and the EFUSE region 160, the number of second bleeder circuits 310 being determined by the number of power supplies supplying EFUSE, as two bleeder circuits 310 are shown in fig. 2.

In this embodiment of the present application, the third I/O unit 170 includes a plurality of third I/Os 171, the plurality of first I/Os being arranged in a line.

According to some embodiments of the chip layout structure of the present application, as shown in fig. 1, the chip layout structure further includes a fourth I/O unit, where the fourth I/O unit is disposed in the middle of the chip, and the fourth I/O unit includes a plurality of fourth I/os 151, where the fourth I/os 151 are aligned with the first I/os.

In this application, the first I/O unit 120 is used for input and output of signals, and is used to supply power to the PLL with the second I/O unit, the third I/O unit 170 is used to supply power to the EFUSE, the fourth I/O unit may be used for input of an external clock signal and/or a reset signal, and the fourth I/O unit is electrically connected to the PLL and the mesh.

According to some embodiments of the present application, as shown in fig. 1, the mesh area includes a plurality of sub-modules, the plurality of mesh areas includes a first mesh area 110 and a second mesh area 180 adjacent to the first mesh area 110, the arrangement of the sub-modules in the first mesh area 110 and the arrangement of the sub-modules in the second mesh area 180 are axisymmetric with a central axis C between the first mesh area 110 and the second mesh area 180, further, the present application further includes a third mesh area 190, the arrangement of the sub-modules in the first mesh area 110 and the arrangement of the sub-modules in the third mesh area 190 are axisymmetric with a central axis D between the first mesh area 110 and the third mesh area 190, the arrangement size, shape and arrangement position of the sub-modules in each two adjacent meshes are axisymmetric, wherein the size and shape of the sub-modules are divided according to the data flow of the chip, when designing the chip, after designing one of the meshes, the other meshes can simplify the layout design of the chip according to the symmetry and the multiplexing layout of the mesh design, and the layout of the multiplexing layout of the chip design can be increased, and the layout of the chip design can be simplified.

In this embodiment of the present application, the line a, the line B, the central axis C, and the central axis D are provided for explaining the positional relationship between the I/O cells and the mesh region, and the line a, the line B, the central axis C, and the central axis D are not present in the chip layout structure.

In the application, the mesh may be used to perform a workload proof operation, such as an ETH operation, and according to the requirement of the operand, the chip may selectively use one or more meshes to complete the operation, the Block may be in an irregular shape, and each mesh side is placed with a first I/O unit 120 related to the Block, and the first I/O121 corresponds to a submodule closest to the Block, where the submodule exists in the mesh area, so that the distance between the first I/O121 and the submodule can be reduced.

Fig. 4 is a schematic structural diagram of a mesh layout according to some embodiments of the present application, where the mesh in fig. 4 is a mesh with a bus structure, and a hierarchical logic relationship of division when the chip layout structure is designed is as follows: the top layer includes four meshes, one mesh includes 8 blocks, as shown in fig. 4, and a mesh area includes at least a plurality of computing units 430, that is, ALUs, a plurality of arbiters, a plurality of routers 450, that is, routers, and a plurality of crossbar, that is, crossbar, where each sub-module includes at least one of the four foregoing, and, taking four meshes as an example, the four meshes all perform the workload proof operation in the same way. Wherein, the setting of the Block size is comprehensively considered according to three aspects:

1. depending on the memory chip capacity. The integrated memory chip adopts a 3DIC packaging mode, the memory chip and the logic chip are packaged together in a 3D stacking mode, so that the chip size is completely consistent with the memory chip, namely the DRAM size, the memory chip capacity is 8T, each mesh is divided into 2T, 8 sub-blocks of the mesh are divided into 2T memory units, the memory chip capacity is 6144 memory units, 64 ALUs are arranged in each mesh, 24 memory units can be directly accessed by one ALU, 64 x 24 = 1536 memory units are occupied by each mesh area, and the memory units occupied by each block are integral multiples of 24.

2. The block area is considered according to the magnitude of the transistor, because of the limitation of the EDA tool, if the magnitude of the transistor is too large, the processing upper limit of the EDA tool is exceeded, the layout design of the chip layout structure cannot be completed, and the comprehensive consideration basically sets about 300 ten thousand standard units per block.

3. According to resource consideration, a plurality of bus interactions exist between blocks, the design of the memory integrated chip related to the application is a fully-connected mode, the fully-connected mode means that each ALU can access each memory unit of the memory chip, the fully-connected mode is realized, the control of a hierarchical crossbar mode is adopted, the crossbar of each mesh is divided into 2 layers of crossbar441 and crossbar442, a large number of interaction buses exist between blocks, a large number of pins, namely ports, are required to be placed on the boundary of the blocks, and whether the pins can be placed in space or not is required to be considered in the size of the boundary of the blocks.

Fig. 5 is a schematic structural diagram of a memory chip according to some embodiments of the present application, where the memory chip includes a logic chip 510 and a memory chip 520 with the layout structure described above, and the logic chip 510 and the memory chip 520 are packaged in a 3D stack package manner.

The integrated memory chip adopts a 3DIC packaging mode, and the 3DIC is a near-memory operation, so that the memory access speed can be effectively improved.

The integrated memory chip needs to be added with TSV (through silicon via) and HB (hybrid bonding), wherein the TSV has the function of punching the back of the logic chip to the logic chip and the memory chip to access input and output signals and supply power, and the HB has the function of bonding the signals and the power supply interaction interface between the logic chip and the memory chip.

The TSV is mainly used for chip power supply, the logic chip and the storage chip adopt M power domains together, the TSV is uniformly inserted into the whole chip, and a Clamp with an ESD (Electro-Static discharge) function is required to be added between each power supply and the ground, so that the Clamp is uniformly inserted into the chip according to the power supply requirement, and the Clamp is required to be placed near the TSV of the corresponding power supply, so that a chip device can be effectively protected.

Those skilled in the art will readily appreciate that the embodiments disclosed satisfy the stated advantages. After reading the above specification, one of ordinary skill in the art will be able to make various changes, equivalents, and various other embodiments as broadly disclosed herein. Accordingly, the protection sought herein is to be limited only by the interpretation of the claims as set forth in the following claims and their equivalents.

Claims (5)

1. A chip layout structure, comprising: the device comprises a chip carrier, a plurality of mesh areas and a plurality of first I/O units, wherein the plurality of mesh areas and the plurality of first I/O units are arranged on the chip carrier, the first I/O units are arranged on one side of the mesh areas and correspond to the mesh areas, the first I/O units comprise a plurality of first I/Os, the plurality of first I/Os are arranged in a straight line, and the first I/O units are arranged on two opposite sides of the chip carrier;

the chip layout structure further comprises a PLL area and a second I/O unit, wherein the PLL area and the second I/O unit are arranged on the chip carrier, the PLL area and the second I/O unit are arranged in the middle of the chip carrier, the second I/O unit is arranged on one side of the PLL area and corresponds to the PLL area, the second I/O unit comprises a plurality of second I/Os, the plurality of second I/Os are arranged in a straight line, a plurality of mesh areas are arranged on two sides of the area where the PLL area and the second I/O unit are located, wiring resistance between the second I/O unit and the PLL is smaller than the resistance requirement of the PLL, wiring resistance between the third I/O unit and the EFUSE is smaller than the resistance requirement of the EFUSE, and wiring resistance= (azimuth resistance is the length/width of the wiring);

the chip layout structure also comprises an EFUSE area and a third I/O unit, wherein the EFUSE area is arranged in the middle of the chip carrier, the third I/O unit corresponds to the EFUSE area, the EFUSE area is arranged at one side of the PLL area, and the third I/O unit corresponding to the EFUSE area is arranged at one side of the EFUSE area;

the chip layout structure further comprises at least one first bleeder circuit and at least one second bleeder circuit, wherein the first bleeder circuit is arranged between the second I/O unit and the PLL, the second bleeder circuit is arranged between the third I/O unit and the EFUSE area, the number of the first bleeder circuits is determined according to the number of power supplies for powering the PLL, and the number of the second bleeder circuits is determined according to the number of power supplies for powering the EFUSE;

the chip layout structure also comprises a fourth I/O unit, wherein the fourth I/O unit is arranged in the middle of the chip carrier and comprises a plurality of fourth I/Os, and the fourth I/Os and the first I/Os are arranged in a straight line.

2. The chip layout structure according to claim 1, wherein the mesh region includes at least one sub-module.

3. The chip layout structure according to claim 1, wherein the plurality of mesh regions includes a first mesh region and a second mesh region adjacent to the first mesh region, and the arrangement of the sub-modules inside the first mesh region and the arrangement of the sub-modules inside the second mesh region are axisymmetric with respect to a central axis between the first mesh region and the second mesh region.

4. The chip layout structure of claim 2 wherein each of the first I/os corresponds to a nearest sub-module.

5. A memory integrated chip, comprising a logic chip and a memory chip having the chip layout structure according to any one of claims 1 to 4, wherein the logic chip and the memory chip are packaged in a 3D stack package.