CN116490925A

CN116490925A - Memory circuit architecture

Info

Publication number: CN116490925A
Application number: CN202180079495.XA
Authority: CN
Inventors: D·李; R·比拉达; B·马纳卡姆·维蒂尔; 陈薄弘; A·保罗; S·松; S·库什瓦哈; R·R·彻科拉; D·扬
Original assignee: Qualcomm Inc
Current assignee: Qualcomm Inc
Priority date: 2020-12-29
Filing date: 2021-12-08
Publication date: 2023-07-25
Also published as: KR20230125203A; US11600307B2; WO2022146643A1; US11908537B2; EP4272213A1; BR112023012153A2; US20230178118A1; TW202230352A; US20220208232A1

Abstract

A semiconductor device includes: a memory circuit having a plurality of quadrants disposed at corners of the memory circuit and surrounding the bank control assembly; wherein a first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input-output circuits configured to access the first bit cell core, the first quadrant being defined by a rectangular boundary surrounding portions of two perpendicular edges of the memory circuit; wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input-output circuits, the second set of input-output circuits configured to access the second bit cell core, the second quadrant being adjacent to the first quadrant, wherein a boundary between the first quadrant and the second quadrant defines a first axis about which the first quadrant and the second quadrant are symmetrical.

Description

Memory circuit architecture

Cross Reference to Related Applications

The present application claims priority and benefit from U.S. patent application Ser. No. 17/136616, filed on 12/29 in 2020, the disclosure of which is incorporated herein by reference in its entirety for all purposes as if fully set forth herein.

Technical Field

The present application relates generally to memory circuits and, more particularly, to memory circuit architectures and methods of using such memory circuits.

Background

Conventional computing devices (e.g., smartphones, tablet computers, etc.) may include a system on a chip (SOC) having a processor and other operating circuitry. The SOC may also include Random Access Memory (RAM) implemented as static Random Access Memory (RAM) (SRAM), dynamic RAM (DRAM), and various Read Only Memories (ROM). The RAM may be implemented within a processor, such as a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), or external to the processor.

Currently, some CPU architectures use many instances of wide input output (I/O) memory operating at 3GHz and at greater than 3 GHz. However, wide I/O implementations at high frequencies may affect memory performance due to resistive-capacitive (RC) effects. One approach is to break up larger memory circuit instances into smaller memory circuit instances, which may reduce some RC effects and may provide acceptable performance for 3GHz and above. However, this approach may also duplicate hardware, thus resulting in leakage losses and area losses. Furthermore, such a solution may use wiring tracks to merge memories, and these wiring tracks themselves may create some amount of RC effect.

Another proposal is to use a repeater (repeater) to support multiple memory circuits arranged horizontally within a single instance. However, the repeater may experience lower speeds and may not be suitable for 3GHz implementations in some cases. Further, such an implementation may increase the complexity of the word line wiring.

Accordingly, there is a need in the art for more memory architectures to achieve a better tradeoff between performance, power, and area (PPA) in systems that use memory.

Disclosure of Invention

Various embodiments provide a memory architecture that provides better performance, power, and area (PPA) than existing systems. Embodiments include a memory circuit having quadrants disposed at corners of the memory circuit and surrounding a bank control assembly. The bank control component may receive instructions and addresses, pre-decode the addresses, and control the row decoder to access specific word lines within the memory core for read and write accesses. The bank control component may include a global bank controller, a local bank controller, and/or portions thereof. The global bank controller and the local bank controller are discussed in more detail below with respect to FIG. 1. The memory circuit may be symmetrical about an axis (e.g., an x-axis or a horizontal axis) that is parallel to the word lines in the quadrant. In addition, some devices may also be symmetrical about the y-axis. Some embodiments include methods of using memory circuits having the architecture.

According to one embodiment, a semiconductor device includes: a memory circuit having a plurality of quadrants disposed at corners of the memory circuit and surrounding the bank control assembly; wherein a first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input-output circuits configured to access the first bit cell core, the first quadrant being defined by a rectangular boundary surrounding portions of two perpendicular edges of the memory circuit; and wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input-output circuits, the second set of input-output circuits configured to access the second bit cell core, the second quadrant being adjacent to the first quadrant, wherein a boundary between the first quadrant and the second quadrant defines a first axis, the first quadrant and the second quadrant being symmetrical about the first axis. For example, a second quadrant of the plurality of quadrants may be symmetrical about the first quadrant horizontal axis; and a third quadrant of the plurality of quadrants may be symmetrical about the first quadrant vertical axis.

According to another embodiment, there is provided a method of operating a semiconductor device, the method including: performing an input-output operation on the memory circuit, including receiving an enable signal directed to a first quadrant of a plurality of quadrants, the plurality of quadrants being disposed at corners of the memory circuit and surrounding the bank control component; wherein a first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input-output circuits configured to access the first bit cell core, the first quadrant being defined by a rectangular boundary surrounding portions of two perpendicular edges of the memory circuit; wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input-output circuits, the second set of input-output circuits configured to access the second bit cell core, the second quadrant being adjacent to the first quadrant, wherein a boundary between the first quadrant and the second quadrant defines a first axis, the first quadrant and the second quadrant being symmetrical about the first axis; wherein performing an input-output operation on the memory circuit comprises: the pre-decoding is performed at the bank control component and the word line drivers in the row decoder are activated in accordance with the pre-decoding.

According to another embodiment, a system on a chip (SOC) includes: a Random Access Memory (RAM) device comprising a plurality of quadrants arranged around corners of a rectangular shape of the RAM device; wherein a first quadrant of the plurality of quadrants is defined by a first boundary surrounding portions of two perpendicular edges of the RAM device; wherein a second quadrant of the plurality of quadrants is symmetrical about the first quadrant horizontal axis; and wherein a third quadrant of the plurality of quadrants is symmetrical about the first quadrant vertical axis.

According to another embodiment, a system on a chip (SOC) includes: a memory circuit having a plurality of quadrants disposed at corners of the memory circuit and surrounding a means for pre-decoding address signals; wherein a first quadrant of the plurality of quadrants includes a first set of input-output circuits configured to access the first data storage component and a first means for storing data, the first quadrant defined by a rectangular boundary surrounding portions of two perpendicular edges of the memory circuit; wherein a second quadrant of the plurality of quadrants includes a second means for storing data and a second set of input-output circuits configured to access the second data storage means, wherein a boundary between the first quadrant and the second quadrant defines a first axis, the first quadrant and the second quadrant being symmetrical about the first axis.

According to another embodiment, a semiconductor device includes: a memory circuit having a plurality of quadrants disposed at corners of the memory circuit and surrounding the bank control assembly; wherein a first quadrant of the plurality of quadrants includes a first bit cell core, the first quadrant being defined by a rectangular boundary surrounding portions of two perpendicular edges of the memory circuit; and wherein a second quadrant of the plurality of quadrants includes a second bit cell core, the second quadrant being adjacent to the first quadrant, wherein a boundary between the first quadrant and the second quadrant defines a first axis, the first quadrant and the second quadrant being symmetrical about the first axis.

Drawings

FIG. 1 is a simplified diagram illustrating an example memory circuit according to one embodiment.

FIG. 2 is a diagram of an example memory circuit of FIG. 1, according to one embodiment.

FIG. 3 is an exploded view of a quadrant in the example memory circuit of FIG. 2, according to one embodiment.

FIG. 4 is an illustration of an example memory circuit according to one embodiment.

FIG. 5 is an exploded view of a quadrant in the example memory circuit of FIG. 4.

FIG. 6 is an illustration of an example column with input-output circuitry, such as in the example memory circuit of FIG. 1, according to one embodiment.

FIG. 7 is a diagram of an example signal that may be used with the embodiment of FIG. 1.

FIG. 8 is a diagram of an example system on a chip (SOC) in which memory circuits having memory circuits such as those shown in FIGS. 1-7 may be constructed, according to one embodiment.

FIG. 9 is a diagram of a method of using the memory circuit of FIGS. 1-7, according to one embodiment.

Detailed Description

Various embodiments provided herein include a memory architecture that provides better performance, power, and area (PPA) balancing than other solutions. Example architectures include folded architectures that are symmetrical about an axis parallel to word lines in a memory bit cell core. An example architecture includes quadrants arranged around a bank control component that provides control for each of the quadrants. Some examples may also be symmetrical about an axis perpendicular to the direction of the word line, providing at least two axes of symmetry.

Continuing with the example, the architecture may include a first quadrant including a first bitcell core and a first set of input-output circuits that service the first bitcell core. The first quadrant may be defined by a rectangular boundary that encloses portions of two perpendicular edges of the memory circuit. For example, the quadrant in the upper left corner may include within its rectangular boundary the vertical edge of the memory circuit to the left of the memory circuit and the horizontal edge of the memory circuit to the upper side of the memory circuit. The directional adjectives (left, right, up and down) used to describe the quadrants will be described in more detail below with respect to fig. 1. Such directional adjectives are used for ease of understanding and are not intended to limit the memory circuit to positioning according to any particular coordinate system.

The memory circuit may also include a second quadrant including a second bit cell core and a second set of input-output circuits configured to access the second bit cell core. The second quadrant is adjacent to the first quadrant, and a boundary (boundary) between the first and second quadrants defines a first axis about which the first and second quadrants are symmetrical. For example, the first quadrant may include an upper left quadrant and the second quadrant may include a lower left quadrant. In another example, the first quadrant may include an upper right quadrant and the second quadrant may include a lower right quadrant. In any case, the first quadrant and the second quadrant are symmetrical about their shared boundary.

The architecture may also include a third quadrant including a third set of input-output circuits and a third bit cell core. The third quadrant may be symmetrical to the first quadrant along a second axis perpendicular to the first axis. For example, if the first and second quadrants are symmetrical about a first axis, the first and third quadrants may be symmetrical about a second axis. The fourth quadrant may also be symmetrical with respect to the second axis.

In some implementations, the first and second quadrants may be separated from the third and fourth quadrants by row decoders and shared bank control components, such as a Global Bank Controller (GBC). Thus, the first and third quadrants may share a row decoder block, and the second and fourth quadrants may share a row decoder block. The GBC may include various circuits, such as pre-decoding circuitry operable to select individual row decoding circuits within a row decoder block.

Further, some examples may include methods of operating a memory circuit, wherein the memory circuit is constructed in accordance with the architecture described above. For example, a method may include performing a read or write operation on a memory circuit, including receiving an enable signal directed to one of four quadrants. In some examples, the enable signal may be a 4-bit left-right enable (LREN 4) signal, the 4-bit left-right enable (LREN 4) signal corresponding to a specification that may be used with some Central Processing Units (CPUs) that conform to ARM Register Transfer Level (RTL) technology. In some examples, LREN4 includes 4 bits (e.g., LREN4<3>, LREN4<2>, LREN4<1>, and LREN4<0 >) and each of the different quadrants receives a respective LREN4 bit that determines whether a bit cell core within the quadrant is enabled to perform a read or write operation. However, the scope of embodiments is not limited to any particular enable signal specification.

Various embodiments may include advantages over other systems. One advantage includes space efficiency. For example, some embodiments may include four quadrants sharing a centrally located GBC. In contrast, some other systems may include a first bit cell core and a second bit cell core that share a bank control component, and a third bit cell core and a fourth bit cell core that share another bank control component. By reducing the number of bank control components (e.g., one to two) used to control the bitcell core, various embodiments may benefit from space savings.

Reducing the number of bank control components may provide advantages over space savings. For example, it is often expected that a bank control component will use power and will even have some amount of leakage. Thus, reducing the number of bank control components may reduce dynamic read and write power as well as leakage power.

Furthermore, and as described above, some other systems may use repeater circuitry to horizontally link memory bit cell cores within the same iteration (iteration) of the memory circuitry. In particular, such other systems may construct the bitcell core horizontally outward so that the external bitcell core may use repeater circuitry. In contrast, the various embodiments described herein use devices with four quadrants built around the central bank control block, and the number of repeater circuits may be omitted or at least reduced as compared to other architectures. Thus, the various embodiments described herein may be more suitable for higher frequency (e.g., 3GHz and above) performance, including some applications using LREN4 enable signals.

FIG. 1 is a simplified diagram illustrating an example memory circuit 100 according to one embodiment. Memory circuit 100 includes four memory cores 101-104. The memory cores 101-104 include a plurality of memory bit cells (memory elements) arranged in rows (words) and columns (bits). At least one bit cell is at the intersection of each row and each column. The scope of embodiments is not limited to any size of memory cores 101-104, as any suitable size of memory cores may be adapted according to the principles described herein.

Memory circuit 100 also includes Global Input Output (GIO) 121-124. Global inputs and outputs 121, 122 provide data paths into and out of memory circuit 100 for both read and write operations. In this example, each of the memory cores 101-104 is shown as having 40 input data paths and 40 output data paths, although the scope of the embodiments may include multiple data paths that are scaled appropriately. Further, in this example, each of the memory cores 101-104 is shown as having 64 word lines, although the scope of the embodiments may include any suitable number. In other words, the architecture herein may be applicable to memory circuits having any suitable number of lines and bit lines. A given GIO may include input latches for control signals and data signals, output logic, and the like.

GIOs 121-124 also include local (local) data paths (LDPs). LDP may include a sense amplifier operable to sense a digital 1 or digital 0 read from a particular memory bitcell during a read operation. LDP may also include read and write multiplexing, bit line charging and reset circuitry, write drivers, write assist circuitry, and the like.

The Global Bank Controller (GBC) 120 receives control instructions and addresses, pre-decodes those addresses, and controls the row decoders 110, 111 through the Local Bank Controllers (LBCs) 125, 126 to access specific word lines within the memory cores 101-104 for both read and write accesses. In some implementations, the GBC 120 may include timing control logic such as clock triggering, self-timing pulse width control, and latching for clock signal generation. GBC 120 may also include operational mode decision logic (which may determine a read mode or a write mode), input signal latching for data signals and control signals, sleep and power-up logic, and the like.

Each of the local bank controllers 125, 126 may include an extension of address pre-decoding and an extension for decoding and driving global signals into each of the GIOs 121-124. Looking at LREN signals LREN <0> - <3>, each LREN signal is received at GBC 120 and is used to generate a corresponding control signal for each of GIOs 121-124, and then data from each bitcell core 101-104 may be read and written through the respective GIOs 121-124. GBC 120 controls the read or write state of each bitcell core 101-104.

Each of the row decoders 110, 111 includes a plurality of individual word line drivers selected by a pre-decoded signal (not shown) output from the respective LBC 125, 126. In one example, the memory circuit 100 includes a time-shared memory architecture in which cores 101, 102 may be read or written during the same period of the clock signal, and cores 103, 104 may be read or written during the same period of the clock signal. In some embodiments, each of cores 101-104 may be read or written during the same period of the clock signal, depending on the state of the corresponding LREN pin. Each of the row decoders 110, 111 comprises a plurality of selectable word line drivers in which a word line having a first index may be driven. Cores 101 and 102 are driven by word lines from decoder 110, and cores 103 and 104 are driven by word lines from decoder 111.

Referring now to fig. 2, fig. 2 is a diagram of a memory circuit 100, but is shown in a different scale than in fig. 1 to illustrate how the memory circuit 100 may be implemented on a semiconductor substrate. Fig. 2 helps illustrate quadrants within memory circuit 100. Fig. 3 is an exploded version of fig. 2, and it omits row decoders 110, 111, local bank controllers 125, 126, and GBC 120. Fig. 3 is provided to facilitate the illustration of the four quadrants of fig. 2, in particular, fig. 3 includes two quadrants at the top (quadrants 201, 202) and two quadrants at the bottom (quadrants 203, 204).

In fig. 2, a dashed box is drawn around a first quadrant 202, the first quadrant 202 comprising a set of bit cell cores 102 and input-output circuits, the set comprising local data paths and GIOs 122. Quadrant 201 is defined by rectangular boundaries surrounding portions of vertical edges 205, 206 as shown in fig. 3. Edges 205, 206 represent physical edges of memory circuit 100, and edges 205, 206 are expected to provide boundaries between circuits of memory circuit 100 and circuits of other devices (separate from memory circuit 100) when built on a semiconductor substrate.

Quadrant 203 includes a set of bit cell cores 103 and input-output circuits, including local data paths and GIOs 123. Quadrant 202 is physically adjacent to quadrant 203, and the boundary between quadrants 202, 203 defines an axis about which quadrants 202, 203 are symmetrical. In this example, the axis of symmetry between quadrants 202, 203 is the x-axis, which is parallel to the direction of the word lines in the bitcell cores 102, 103. Although quadrants 202, 203 are physically adjacent to each other at their respective GIOs 122, 123, the circuitry in GIO 122 is not in electrical communication (i.e., they are electrically isolated) with the circuitry in GIO 123.

Looking now at quadrants 201, 204, they share a relationship similar to the symmetrical relationship of quadrants 202, 203. In particular, quadrants 201, 204 are also symmetrical about a horizontal axis, which is also an axis parallel to the direction of the word lines in the bitcell cores 101, 104. Continuing with the example of fig. 2, row decoders 110, 111 are also symmetrical about a horizontal axis separating quadrants 201 and 202 from quadrants 203, 204. In this example, the portion that is asymmetric about the axis is a central portion that includes local bank controllers 125, 126 and global bank control 120. Thus, in addition to LBCs 125, 126 and GBC 120, memory circuit 100 itself is symmetrical about a horizontal axis separating quadrants 201 and 202 from quadrants 203 and 204.

Continuing with the example of fig. 2, symmetry also exists along a vertical axis passing through the middle of the row decoders 110, 111. Examples of vertical axes include axes perpendicular to the word lines or parallel to bit lines within the bitcell cores 101-104. Thus, the row decoders 110, 111 may be internally symmetrical about this axis, and the quadrants 201, 204 may be symmetrical with the quadrants 202, 203 about the same vertical axis.

As an example of vertical axis symmetry, the circuitry in each of the components of the quadrant is symmetrical about the y-axis. For example, the input output circuit 207 configured to access the bitcell core 101 is noted, and it is repeated multiple times within the GIO 121. The input-output circuitry 207 may be vertically axisymmetric with any similar circuitry in the GIO 122, such as input-output circuitry 208. And as an example of horizontal axis symmetry, the input-output circuit 207 may also be symmetrical with the input-output circuit 209. And these are merely examples because of the symmetry present in the circuit. For example, the word lines, bit lines, and bit cells in bit cell core 102 are symmetrical about the same component horizontal axis in bit cell core 103 and symmetrical about the same component vertical axis in bit cell core 101. Again, the exceptions to symmetry are LBCs 125, 126 and GBC 120, which in this example may be asymmetric.

For example, the GBC 120 may include an irregular shape with more or different circuits on the right side than on the left side and vice versa or more or different circuits above the centerline below the centerline Fang Bi and vice versa. In one example, the pre-decoding circuit may not benefit from symmetry and thus may be built on silicon in a manner that serves the purpose of reducing silicon area, but may not necessarily be symmetrical about the x-axis or the y-axis. In another example, the LBCs 125, 126 may not be physically separate from the GBC 120 and, alternatively, may be functional components within the GBC 120. LBCs 125, 126 may also be constructed for the purpose of reducing the amount of silicon area, but need not be symmetrical about the x-axis or the y-axis. However, the scope of embodiments does not exclude systems in which the GBC 120 or LBC 125, 126 may be symmetrical about a particular axis.

FIG. 4 is an illustration of an example memory circuit 400 according to one embodiment. Fig. 5 is an exploded view of an example memory circuit 400, omitting row decoders 410, 411, LBCs 125, 126, and GBCs 120.

The embodiment of fig. 4 adjusts the symmetry principles of the embodiment of fig. 2 within different architectures. For example, the embodiment of FIG. 4 divides each of the bitcell cores 401-404 into two sub-portions. Looking first at the bitcell core 401, it is divided into sub-portions 401a and 401b. The same is true for the other bitcell cores 402-404. Looking first at the bit cell core 401, the sub-portions 401a and 401b are separated from each other by the local data path circuitry 431. Examples of components within local data path circuitry 431 may include sense amplifiers, multiplexers, bit line reset and precharge devices, write drivers, and the like.

Looking at bit cell core 402, it is divided into sub-portions 402a and 402b, with sub-portions 402a and 402b separated by local data path circuitry 432. The bit cell core 403 is divided into two sub-portions 403a and 403b, the sub-portions 403a and 403b being separated by a local data path circuit arrangement 433. Similarly, bit cell core 404 is split into two sub-portions 404a and 404b, with sub-portions 404a and 404b separated by local data path circuitry 434. Local data path circuitry 434 and local data path circuitry 433 are both in communication with local bank controller 126. Similarly, local data path circuitry 431 and local data path circuitry 432 are in communication with local bank controller 125.

Each of the four quadrants 451-454 includes a respective GIO 421-424. Quadrants 451 and 452 are symmetrical about the drawn horizontal axis relative to quadrants 454 and 453, with GIOs 421, 422 physically adjacent to GIOs 424, 423. For example, the components of local data path circuitry 431 are symmetrical to the horizontal axis of the components of local data path circuitry 434, as are the corresponding components of local data path circuitry 432, 433. Similarly, the word lines, bit lines, and other support circuitry within memory bitcell core 401 are symmetrical about the same axis as the word lines, bit lines, and other support circuitry within memory bitcell core 404. As are the bitcell cores 402 and 403. Furthermore, GIO 421 and GIO 424 are horizontally axis symmetric, and GIO 422 and GIO 433 are also the same.

The embodiments of fig. 4 and 5 show symmetry about a vertical axis (y-axis) extending through the center of GBC 120. For example, the row decoders 410, 411 may also be internally symmetric about the vertical axis, although the LBCs 125, 126 and GBCs 120 may not have internal symmetry. In other words, and as described above, LBCs 125, 126 and GBC 120 may be internally asymmetric. Continuing with this example, quadrant 451 can be symmetrical about the quadrant 452 vertical axis, and quadrant 454 can be symmetrical with the quadrant 453 vertical axis.

Fig. 6 is another illustration of a memory circuit 100 according to one embodiment. Fig. 6 illustrates the arrangement of input pins and output pins in the various quadrants, and particular attention is paid to a column 610 of input and output pins within the quadrants 202, 203. More specifically, column 610 exists within GIOs 122, 123. Quadrants 201-204 are shown in FIGS. 2-3.

The example of fig. 6 includes two sets of input pins and output pins in column 610—one set of input pins and one set of output pins for quadrant 202, and another set of input pins and output pins for quadrant 203. The set of input pins for quadrant 202 starts with index 0 (e.g., din [0,1 ]), as does the set of output pins for quadrant 202 (e.g., dout [0,1 ]). For quadrant 203, the set of input pins starts with index 40 (e.g., din [40,41 ]), as does the set of output pins (e.g., dout [40,41 ]).

Since fig. 6 shows the column on the left, this example will continue through the left for convenience. Between columns 610 and 620, there are also 18 other columns, which 18 other columns are indicated by ellipses for ease of illustration. Immediately to the left of the illustrated column 610, there is another column (not shown) having sets of output pins Dout [2,3] and [42,43] and sets of input pins Din [2,3] and [42,43]. The left-most left column 620 would include: dout [38,39], din [78,79] and Dout [78,79]. The right hand quadrants 201, 204 include Din and Dout indexes 80-159 in a total of twenty columns represented by columns 630 and 640, with the columns between 630 and 640 represented by ellipses for ease of illustration. Thus, each quadrant has 40 input pins and 40 output pins, and the total pins in memory circuit 100 are 160 inputs and 160 outputs (i.e., 160I/Os).

Of course, the specific numbers given in the embodiment of fig. 6 are merely examples. In fact, the implementation of FIG. 6 corresponds to ARM RTL LREN4 128 by 160 memory, where 128 is the number of word lines and 160 is the number of I/Os. Other embodiments may scale the number of input pins and output pins appropriately, and may employ any Register Transfer Level (RTL) or other technique.

Note in fig. 6 that the pin density within a column doubles. For example, column 610 includes two data input pins and two data output pins. In contrast, some other example systems may include only a single data input pin and a single data output pin in a given column. One advantage of the embodiment of fig. 6 is that it can reduce the amount of semiconductor area in the horizontal dimension by using less input/output pin area.

Fig. 7 is a diagram of the layout and signals of the middle column of the memory circuit 100 of fig. 1-3 and 6, according to one embodiment. For ease of illustration, FIG. 7 omits the bitcell memory cores 101-104.

The example of FIG. 7 includes four LREN4 signals LREN <0> - <3>, which are received by GBC 120 from outside the memory circuit. For example, a processor core (not shown) may generate an LREN signal to control accessibility of the respective quadrant. The write enable (wen) signal controls the reading and writing of the memory device 100.

For each of the bitcell memory cores 101-104, the GBC 120 also includes a respective write clock (wclk) and a respective clock (bclk) for latching data in the signal. Continuing with this example, row decoder 110 and LBC 125 correspond to memory bit cell cores 101, 102, and row decoder 111 and LBC 126 correspond to memory bit cell cores 103, 104. Although not shown here, the GIOs 121-124 may receive data to be written and may output the read data, and the GBC 120 may also receive addresses for reading and writing and instructions for performing reading and writing.

The GBC 120 receives the address and performs pre-decoding, where the pre-decoded signal may be used to select a particular word line driver (not shown) at the row decoder 110, 111. The pre-decoded signals are shown as ra_len, ra_ ren, ra, rb, rc in fig. 7. The signals ra_len and ra_ren are used as core selection signals and determine whether the respective cores 101-104 are to be read or written or are not to be operated at all. The signals ra, rb, rc turn on a particular word line driver in the core selected by the core select signal. The GBC 120 includes logic to translate addresses into appropriate pre-decode signals and provide that particular pre-decode signal to the corresponding row decoder 110, 111 to select word line drivers in one or more of the bit cell memory cores 101-104. Those pre-decoded signals pass through the LBCs 125, 126 as they are, or may be modified by the LBCs 125, 126.

The GBC 120 also generates clocks for the LBCs 125, 126, and these clocks are shown in fig. 7 as LBC _clk. Signal wen is write enable, rclk is the read clock, and gsen is the sense amplifier signal used to control the gain at the sense amplifier in the local data path.

The LBCs 125, 126 generate signals, including a sense enable signal se, to enable one or more sense amplifiers (not shown) in the local data path. The sense enable signal se may be left or right to address a local data path in quadrant 202, 203 or quadrant 201, 204. The same is true for other signals marked left or right (l or r), which are appropriately addressed to quadrants 202, 203 or quadrants 201, 204. Other signals generated by LBCs 125, 126 also control components (signals pre_n, wm, mn) within the local data path.

The layout shown in fig. 7 differs from the bank control in the existing solution. For example, GBC 120 controls two different LBCs 125, 126 and a total of four memory bit cell cores 101-104. This is made apparent by the GBC 120 routing signals to each of the LBCs 125, 126, with some of those signals being left or right, indicating one of the two memory bit cell cores served by each of the LBCs 125, 126. In contrast, other systems that associate a bank control component with two or more memory bit cell cores are less complex and do not distinguish between multiple cores at each LBC, as each LBC can only support a single memory bit cell core at most.

In some cases, the penalty (penalty) of increasing the number of transistors in a bank controller to serve four cores instead of two cores may be less than the penalty caused by using two different bank controllers. Thus, an advantage of some embodiments is that the memory circuit 100, 400 may include the GBC 120, the GBC 120 occupying less semiconductor area and using less dynamic power and experiencing less leakage power than another system having multiple bank controllers for the same number of memory bit cell cores.

Further, another advantage of some embodiments is that the memory circuit 100, 400 may conform to the following protocol: the protocol uses four different enable signals and four different memory bit cell cores (e.g., LREN 4) while being treated as a single macro element during design time. In contrast, some systems including less than four memory bit cell cores may have to use multiple macro-elements to combine during design time to support protocols such as LREN 4. Thus, some embodiments may simplify the design time of some designs.

Further, it should be noted that the scope of embodiments is not limited to any particular protocol, such as LREN 4. Rather, various embodiments may employ any technique to increase or decrease the number of enable signals or use different types of enable signals.

Various embodiments described herein may be suitable for use in a system on a chip (SOC). Examples of the SOC include a semiconductor chip having a plurality of processing devices therein, including a Graphics Processing Unit (GPU), a Central Processing Unit (CPU), a modem unit, a camera unit, and the like. In some examples, the SOC may be included within a chip package, mounted on a printed circuit board, and disposed within a portable device such as a smart phone or tablet computer. However, the scope of embodiments is not limited to chips implemented within tablet computers or smart phones, as other applications are possible.

FIG. 8 is an illustration of an example SOC 800, according to one embodiment. In this example, the SOC 800 is implemented on a semiconductor die, and it includes a plurality of system components 810-890. Specifically, in this example, SOC 800 includes CPU 810, with CPU 810 being a multi-core general purpose processor having four processor cores (core 0-core 3). Of course, the scope of embodiments is not limited to any particular number of cores, as other embodiments may include two cores, eight cores, or any other suitable number of cores in CPU 810. SOC 800 also includes other system components such as a first Digital Signal Processor (DSP) 840, a second DSP 850, a modem 830, a GPU 820, a video subsystem 860, a Wireless Local Area Network (WLAN) transceiver 870, and a Video Front End (VFE) subsystem 880.

SOC 800 also includes RAM memory circuitry 890. In this example, RAM memory circuit 890 may include one or more memory circuits corresponding to the architecture described above with respect to fig. 1-7. The embodiments described herein may be adapted for use in any RAM memory circuit. For example, in this example, SOC 800 may include a separate RAM memory circuit 890, and other RAM components may be present in other processing units, such as GPU 820, modem unit 130, DSPs 140, 150, etc. Those RAM cells may also be adapted according to the architecture described above with respect to fig. 1-7.

As described above, SOC 800 may include a CPU 810 having a plurality of cores 0-3, and one or more of those cores may execute computer readable code that provides the functionality of an operating system kernel. Further, an example operating system kernel may include memory management logic that may perform read and write operations to various memory circuits, such as the RAM memory circuits described herein. Accordingly, the principles described with respect to fig. 1-7 and 9 may be implemented in SOC 800, and more particularly, the circuits and methods shown in fig. 1-7 and 9 may be implemented in SOC 800 or other chips to provide memory read and write functions. For example, an operating system kernel with memory management logic may generate signals described in fig. 1 and 7, such as lren, wclk, etc., to perform read or write operations.

A flowchart of an example method 900 of performing reads and writes is illustrated in fig. 9, according to one embodiment. In one example, method 900 is performed by any of the memory circuits shown in fig. 1-7. In some examples, a memory management unit, either internal or external to the CPU or GPU, includes processing circuitry that executes computer-readable instructions to perform read or write operations to RAM memory circuitry by controlling the GBC (e.g., GBC 120 of fig. 1 and 4). For example, logic in the CPU or GPU may send address and control signals to the GBC to cause the GBC to read or write data. Examples of control signals may include left and right enable signals, such as may be in compliance with LREN4.

At act 910, a method includes performing a first read or write operation. Act 910 may include receiving a first enable signal directed to a first quadrant of a plurality of quadrants. In the example of fig. 1-3, the first enable signal may include LREN <0>, LREN <0> being received by GIO 122 at quadrant 202. While the enable signal may be received by the GIO 122, it may be passed to a bank control component such as the GBC 120.

Act 910 may also include receiving address signals and data in the case of a write operation. For example, the address signal may indicate a particular address to which the data should be saved. The bank controller may pre-decode the address signals to select one or more word line drivers in the memory bit cell core of the quadrant based on the pre-decoded signals.

In some examples, act 910 may include receiving an address signal in the case of a read operation. Again, the bank control circuitry may pre-decode the address signals to select one or more word line drivers in the memory bit cell core of the quadrant based on the pre-decoded signals.

At act 920, the method includes performing a second read or write operation. Act 920 may include receiving a second enable signal directed to a second quadrant of the plurality of quadrants. In the examples of fig. 1-3, the second enable signal may include any of LREN <1-3> corresponding to any of the respective quadrants 203, 201, and 204.

As with act 910, act 920 may include: the method includes receiving address signals and control signals, pre-decoding those address signals, and reading or writing data by selecting one or more word line drivers within a memory bit cell core within a quadrant selected by a particular enable signal.

The scope of the embodiments is not limited to the specific actions shown in fig. 9. Rather, other embodiments may add, omit, rearrange, or modify one or more actions. In one example, acts 910 and 920 may overlap in time because memory circuits 100, 400 may perform read and write operations simultaneously in multiple quadrants. Thus, act 910 may be performed for a first quadrant, while act 920 may be performed for a second quadrant. In fact, by utilizing four quadrants simultaneously, the architecture of the memory circuits 100, 400 may allow up to four read/write operations to be performed simultaneously. However, it is not required that any particular number of quadrants must be read or written during any particular clock cycle.

Further, embodiments may repeat acts 910 and/or 920 in some of the quadrants at each clock cycle or at least in subsequent non-consecutive cycles. In other words, method 900 may include reading or writing any one or more quadrants during a particular clock cycle, then reading or writing any one or more quadrants during a next clock cycle, and so on. The actions of method 900 may be performed a number of times as appropriate to read or write the requested data. When a word line is driven, it allows a byte of data to be read from memory, where the byte of data is written to or read from a physical location in the memory circuit that corresponds to a logical location known to the CPU, GPU, or other processing device. Multiple clock cycles may be used to read or write multiple bytes of data, with as many clock cycles as appropriate for the size of the read or write request, and this is true for each of the quadrants.

Example embodiment

Embodiment 1. A semiconductor device includes:

a memory circuit having a plurality of quadrants disposed at corners of the memory circuit and surrounding a bank control component;

Wherein a first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input-output circuits configured to access the first bit cell core, the first quadrant defined by a rectangular boundary surrounding portions of two perpendicular edges of the memory circuit;

wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input-output circuits configured to access the second bit cell core, the second quadrant being adjacent to the first quadrant, wherein a boundary between the first quadrant and the second quadrant defines a first axis, the first quadrant and the second quadrant being symmetrical about the first axis.

Embodiment 2. The semiconductor device of embodiment 1 wherein the boundary line is parallel to the direction of the word line in the first bit cell core.

Embodiment 3. The semiconductor device according to embodiment 1 or embodiment 2, further comprising:

a third quadrant of the plurality of quadrants, the third quadrant including a third bit cell core and a third set of input-output circuits configured to access the third bit cell core, the third quadrant being symmetrical to the first quadrant along a second axis, the second axis being perpendicular to a direction of word lines in the first bit cell core.

Embodiment 4. The semiconductor device according to embodiment 3, further comprising:

a row decoder is disposed between the first quadrant and the third quadrant and adjacent to the bank control component.

Embodiment 5. The semiconductor device according to embodiment 3 or embodiment 4, further comprising:

a fourth quadrant of the plurality of quadrants, the fourth quadrant including a fourth bit cell core and a fourth set of input-output circuits configured to access the fourth bit cell core, the fourth quadrant being adjacent to the third quadrant and symmetrical to the third quadrant along the first axis.

Embodiment 6. The semiconductor device according to embodiment 5, further comprising:

a row decoder is disposed between the second quadrant and the fourth quadrant and adjacent to the bank control component.

Embodiment 7. The semiconductor device of any of the preceding embodiments wherein the first set of input-output circuits and the second set of input-output circuits are laid out adjacent to each other in the semiconductor device, further wherein the first set of input-output circuits is electrically isolated from the second set of input-output circuits.

Embodiment 8. The semiconductor device of any of the preceding embodiments, wherein the first quadrant further comprises:

an additional bit cell core separated from the first bit cell core by a set of sense amplifiers configured to access the additional bit cell core.

Embodiment 9. The semiconductor device of any of the preceding embodiments, wherein the bank control component comprises pre-decoding circuitry configured to access each of the plurality of quadrants.

Embodiment 10. The semiconductor device of any of the preceding embodiments wherein the memory circuit is in communication with four left and right enable signals from outside the memory circuit.

Embodiment 11. A method of operating a semiconductor device, the method comprising:

performing an input-output operation on a memory circuit, including receiving an enable signal directed to a first quadrant of a plurality of quadrants, the plurality of quadrants being arranged at corners of the memory circuit and surrounding a bank control component;

wherein the first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input-output circuits configured to access the first bit cell core, the first quadrant defined by a rectangular boundary surrounding portions of two perpendicular edges of the memory circuit;

Wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input-output circuits configured to access the second bit cell core, the second quadrant being adjacent to the first quadrant, wherein a boundary between the first quadrant and the second quadrant defines a first axis about which the first quadrant and the second quadrant are symmetric;

wherein performing the input-output operation on the memory circuit comprises: a pre-decoding is performed at the bank control component, and a word line driver in a row decoder is activated in accordance with the pre-decoding.

Embodiment 12. The method of embodiment 11, further comprising:

wherein the input-output operation includes a read operation or a write operation.

Embodiment 13. The method of embodiment 11 or embodiment 12, further comprising:

additional input-output operations are performed at the second bitcell core.

Embodiment 14. The method of any of embodiments 11-13, further comprising a third quadrant, wherein the third quadrant comprises a third bit cell core and a third set of input-output circuits configured to access the third bit cell core, the third quadrant being separated from the first quadrant by the row decoder, wherein a second axis is perpendicular to the first axis, and wherein the first quadrant and the third quadrant are symmetrical about the second axis.

Embodiment 15. The method of embodiment 14, further comprising:

additional input-output operations are performed at the third bitcell core.

Embodiment 16. The method of embodiment 15 wherein the input output operations and the additional input output operations are performed simultaneously.

Embodiment 17. The method of embodiment 15 wherein performing the additional input-output operations comprises:

an additional enable signal directed to the third quadrant is received.

Embodiment 18. The method of embodiment 15 wherein performing the additional input-output operations comprises:

the word line drivers in the row decoder are activated in accordance with the pre-decoding.

Embodiment 19. A system on a chip (SOC) comprising:

a Random Access Memory (RAM) device comprising a plurality of quadrants arranged around corners of a rectangular shape of the RAM device;

wherein a first quadrant of the plurality of quadrants is defined by a first boundary surrounding portions of two perpendicular edges of the RAM device;

wherein a second quadrant of the plurality of quadrants is symmetrical about the first quadrant horizontal axis; and is also provided with

Wherein a third quadrant of the plurality of quadrants is symmetrical about the first quadrant vertical axis.

Embodiment 20. The SOC of embodiment 19, further comprising a bank control device, each of the plurality of quadrants sharing the bank control device, wherein the bank control device is internally asymmetric.

Embodiment 21. The SOC of embodiment 19 or embodiment 20, wherein the first quadrant includes a first set of input-output circuits and a first bit cell core.

Embodiment 22. The SOC of any of embodiments 19-21 wherein the second quadrant is adjacent to the first quadrant, and wherein a boundary between the first and second quadrants defines a first axis about which the first and second quadrants are symmetrical.

Embodiment 23. The SOC of any of embodiments 19-22 wherein the first quadrant and the third quadrant are separated by a row decoder having a plurality of word line drivers, wherein the first quadrant and the third quadrant are symmetrical about a vertical axis bisecting the row decoder.

Embodiment 24. The SOC of any of embodiments 19-23 wherein a fourth quadrant of the plurality of quadrants is symmetrical about the third quadrant horizontal axis.

Embodiment 25. The SOC of embodiment 24, wherein the fourth quadrant is separated from the second quadrant by a row decoder, wherein the second quadrant and the fourth quadrant are symmetrical about a vertical axis bisecting the row decoder.

Embodiment 26. A system on a chip (SOC) comprising:

a memory circuit having a plurality of quadrants arranged at corners of the memory circuit and surrounding a means for pre-decoding address signals;

wherein a first quadrant of the plurality of quadrants includes a first set of input-output circuits configured to access the first data storage means and a first means for storing data, the first quadrant defined by a rectangular boundary surrounding portions of two perpendicular edges of the memory circuit;

wherein a second quadrant of the plurality of quadrants includes a second set of input-output circuits and a second means for storing data, the second set of input-output circuits configured to access the second data storage means, wherein a boundary between the first quadrant and the second quadrant defines a first axis, the first quadrant and the second quadrant being symmetrical about the first axis.

Embodiment 27. The SOC of embodiment 26, wherein the first data storage includes a first bit cell core having a first plurality of memory elements.

Embodiment 28. The SOC of embodiment 26 or embodiment 27, wherein the second data storage component includes a second bit cell core having a second plurality of memory elements.

Embodiment 29. The SOC of any one of embodiments 26-28, wherein the means for pre-decoding address signals includes a global bank controller in communication with each of the quadrants.

Embodiment 30. The SOC of embodiment 29, wherein the global bank controller is internally asymmetric.

Embodiment 31. The SOC of any of embodiments 26-30 wherein a third quadrant of the plurality of quadrants includes a third set of input-output circuits configured to access the third data storage component and a third component for storing data, wherein the first and third quadrants are symmetric about a second axis bisecting a row decoder disposed between the first and third quadrants.

Embodiment 32. The SOC of embodiment 31, wherein the second axis is perpendicular to the direction of the word lines in the first quadrant.

Embodiment 33. The SOC of any one of embodiments 26-32, wherein the first axis is parallel to a direction of a word line in the first quadrant.

Embodiment 34. The SOC of any of embodiments 26-33 wherein the first set of input-output circuits and the second set of input-output circuits are laid out adjacent to each other in the SOC, further wherein the first set of input-output circuits is electrically isolated from the second set of input-output circuits.

Embodiment 35. The SOC of any one of embodiments 26-34, wherein the memory circuit is in communication with four or more enable signals from outside the memory circuit.

Embodiment 36. The SOC of any of embodiments 26-34 wherein the first quadrant has input pins and output pins arranged in a plurality of columns, each column having two input pins and two output pins.

Embodiment 37. A semiconductor device includes:

Wherein a first quadrant of the plurality of quadrants includes a first bit cell core, the first quadrant defined by a rectangular boundary surrounding portions of two perpendicular edges of the memory circuit;

wherein a second quadrant of the plurality of quadrants includes a second bit cell core, the second quadrant being adjacent to the first quadrant, wherein a boundary between the first quadrant and the second quadrant defines a first axis, the first quadrant and the second quadrant being symmetrical about the first axis.

Embodiment 38. The semiconductor device of embodiment 1 wherein the boundary line is parallel to a direction of a word line in the first bit cell core.

Embodiment 39 the semiconductor device according to embodiment 1 or embodiment 2, further comprising:

a third quadrant of the plurality of quadrants, the third quadrant including a third bit cell core, the third quadrant being symmetrical to the first quadrant along a second axis, the second axis being perpendicular to a direction of a word line in the first bit cell core.

Embodiment 40. The semiconductor device according to embodiment 39, further comprising:

Embodiment 41 the semiconductor device according to embodiment 39 or embodiment 40, further comprising:

a fourth quadrant of the plurality of quadrants, the fourth quadrant including a fourth bit cell core, the fourth quadrant being adjacent to the third quadrant and symmetrical to the third quadrant along the first axis.

As will now be appreciated by those skilled in the art, and depending on the particular application at hand, many modifications, substitutions, and variations may be made to the materials, apparatus, arrangements, and methods of use of the apparatus of the present disclosure without departing from the spirit and scope of the present disclosure. In view of this, the scope of the present disclosure should not be limited to the particular embodiments shown and described herein (as they are merely a few examples of the disclosure), but rather should be fully commensurate with the scope of the appended claims and their functional equivalents.

Claims

1. A semiconductor device, comprising:

wherein a first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input-output circuits configured to access the first bit cell core, the first quadrant defined by a rectangular boundary surrounding portions of two perpendicular edges of the memory circuit; and is also provided with

2. The semiconductor device of claim 1, wherein the boundary is parallel to a direction of a word line in the first bit cell core.

3. The semiconductor device of claim 1, further comprising:

4. The semiconductor device according to claim 3, further comprising:

5. The semiconductor device according to claim 3, further comprising:

6. The semiconductor device of claim 5, further comprising:

7. The semiconductor device of claim 1, wherein the first set of input-output circuits and the second set of input-output circuits are adjacent to each other in the semiconductor device, further wherein the first set of input-output circuits is electrically isolated from the second set of input-output circuits.

8. The semiconductor device of claim 1, wherein the first quadrant further comprises:

9. The semiconductor device of claim 1, wherein the bank control component comprises a pre-decode circuitry configured to access each of the plurality of quadrants.

10. The semiconductor device of claim 1, wherein the memory circuit is in communication with four left and right enable signals from outside the memory circuit.

11. A method of operating a semiconductor device, the method comprising:

Wherein performing the input-output operation on the memory circuit comprises: pre-decoding is performed at the bank control component and a word line driver in a row decoder is activated in accordance with the pre-decoding.

12. The method of claim 11, further comprising:

13. The method of claim 11, further comprising:

additional input-output operations are performed at the second bitcell core.

14. The method of claim 11, further comprising a third quadrant, wherein the third quadrant comprises a third set of input-output circuits and a third bit cell core, the third set of input-output circuits configured to access the third bit cell core, the third quadrant separated from the first quadrant by the row decoder, wherein a second axis is perpendicular to the first axis, and wherein the first and third quadrants are symmetrical about the second axis.

15. The method of claim 14, further comprising:

additional input-output operations are performed at the third bitcell core.

16. The method of claim 15, wherein the input-output operation and the additional input-output operation are performed simultaneously.

17. The method of claim 15, wherein performing the additional input-output operation comprises:

an additional enable signal directed to the third quadrant is received.

18. The method of claim 15, wherein performing the additional input-output operation comprises:

19. A system on a chip (SOC) comprising:

20. The SOC of claim 19, further comprising a bank control component, each quadrant of the plurality of quadrants sharing the bank control component, wherein the bank control component is internally asymmetric.

21. The SOC of claim 19, wherein the first quadrant includes a first set of input-output circuits and a first bit cell core.

22. The SOC of claim 19, wherein the second quadrant is adjacent to the first quadrant, and wherein a boundary between the first and second quadrants defines a first axis about which the first and second quadrants are symmetrical.

23. The SOC of claim 19, wherein the first quadrant and the third quadrant are separated by a row decoder having a plurality of word line drivers, wherein the first quadrant and the third quadrant are symmetrical about a vertical axis bisecting the row decoder.

24. The SOC of claim 19, wherein a fourth quadrant of the plurality of quadrants is symmetrical about the third quadrant horizontal axis.

25. The SOC of claim 24, wherein the fourth quadrant is separated from the second quadrant by a row decoder, wherein the second quadrant and the fourth quadrant are symmetrical about a vertical axis bisecting the row decoder.

26. A system on a chip (SOC) comprising:

27. The SOC of claim 26, wherein the first data storage component comprises a first bit cell core having a first plurality of memory elements.

28. The SOC of claim 27, wherein the second data storage component comprises a second bitcell core having a second plurality of memory elements.

29. The SOC of claim 26, wherein the means for pre-decoding address signals comprises a global bank controller in communication with each of the quadrants.

30. The SOC of claim 29, wherein the global bank controller is internally asymmetric.

31. The SOC of claim 29, wherein a third quadrant of the plurality of quadrants includes a third set of input-output circuits and a third means for storing data, the third set of input-output circuits configured to access the third data storage means, wherein the first and third quadrants are symmetrical about a second axis that bisects a row decoder disposed between the first and third quadrants.

32. The SOC of claim 31, wherein the second axis is perpendicular to a direction of a word line in the first quadrant.

33. The SOC of claim 26, wherein the first axis is parallel to a direction of a word line in the first quadrant.

34. The SOC of claim 26, wherein the first set of input-output circuits and the second set of input-output circuits are laid out adjacent to each other in the SOC, further wherein the first set of input-output circuits is electrically isolated from the second set of input-output circuits.

35. The SOC of claim 26, wherein the memory circuit is in communication with four left and right enable signals from outside the memory circuit.

36. The SOC of claim 26, wherein the first quadrant has input pins and output pins arranged in a plurality of columns, each column having two input pins and two output pins.

37. A semiconductor device, comprising:

wherein a first quadrant of the plurality of quadrants includes a first bit cell core, the first quadrant defined by a rectangular boundary surrounding portions of two perpendicular edges of the memory circuit; and is also provided with

38. The semiconductor device of claim 37, wherein the boundary is parallel to a direction of a word line in the first bit cell core.

39. The semiconductor device of claim 37, further comprising:

40. The semiconductor device of claim 39, further comprising:

41. The semiconductor device of claim 39, further comprising: