CN220419440U - Repetition frequency pulse power supply waveform acquisition circuit - Google Patents
Repetition frequency pulse power supply waveform acquisition circuit Download PDFInfo
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- CN220419440U CN220419440U CN202322008775.0U CN202322008775U CN220419440U CN 220419440 U CN220419440 U CN 220419440U CN 202322008775 U CN202322008775 U CN 202322008775U CN 220419440 U CN220419440 U CN 220419440U
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Abstract
The utility model belongs to the technical field of repeated frequency pulse power supply discharge current acquisition, and aims to provide a repeated frequency pulse power supply waveform acquisition circuit which comprises a data processing module and a plurality of data acquisition modules which are respectively and electrically connected with the data processing module; the data processing module comprises a digital signal processor and a first communication circuit electrically connected with the digital signal processor; each data acquisition module comprises a singlechip integrated control circuit, a data acquisition unit and a second communication circuit, wherein the data acquisition unit and the second communication circuit are respectively and electrically connected with the singlechip integrated control circuit, the singlechip integrated control circuit is electrically connected with the digital signal processor through the second communication circuit, the data acquisition unit comprises an analog conditioning circuit, an A/D conversion circuit and a data buffer circuit which are sequentially and electrically connected, and the data buffer circuit is electrically connected with the singlechip integrated control circuit. The utility model is beneficial to reducing the repeated development of the circuit and improving the development and maintenance efficiency of the repetition frequency pulse power supply.
Description
Technical Field
The utility model belongs to the technical field of discharge current acquisition of a repetition frequency pulse power supply, and particularly relates to a repetition frequency pulse power supply waveform acquisition circuit.
Background
The repetition frequency pulse power supply works at the repetition frequency, and the discharge current of the repetition frequency pulse power supply needs to be collected through a collecting circuit so as to judge whether each discharge loop of the repetition frequency pulse power supply is normal or not. However, in using the prior art, the inventors found that there are at least the following problems in the prior art: the acquisition circuit in the prior art needs to design corresponding hardware circuits according to the number of the discharge circuits, so that the acquisition circuit has a complex structure, a long development period and inconvenience in later replacement and maintenance.
Disclosure of Invention
In order to solve the technical problems at least to a certain extent, the utility model provides a repetition frequency pulse power supply waveform acquisition circuit.
In order to achieve the above purpose, the present utility model adopts the following technical scheme:
the repetition frequency pulse power supply waveform acquisition circuit comprises a data processing module and a plurality of data acquisition modules which are respectively and electrically connected with the data processing module; the data processing module comprises a digital signal processor and a first communication circuit electrically connected with the digital signal processor; each data acquisition module comprises a single chip microcomputer integrated control circuit, a data acquisition unit and a second communication circuit, wherein the data acquisition unit and the second communication circuit are respectively and electrically connected with the single chip microcomputer integrated control circuit, the single chip microcomputer integrated control circuit is electrically connected with the digital signal processor through the second communication circuit, the data acquisition unit comprises an analog conditioning circuit, an A/D conversion circuit and a data buffer circuit which are sequentially and electrically connected, and the data buffer circuit is electrically connected with the single chip microcomputer integrated control circuit.
In one possible design, the SCM integrated control circuit adopts a TMS320F28335 type microcontroller and peripheral circuits thereof.
In one possible design, the first communication circuit and the second communication circuit each employ an RS485 communication circuit.
In one possible design, the first communication circuit and the second communication circuit each employ an ADM2582EBRWZ-REEL7 type isolated RS485 driver and its peripheral circuitry.
In one possible design, the analog conditioning circuit includes OPA2197 type operational amplifier U19, current signal acquisition interface XS2, resistor R50, resistor R53, resistor R54, capacitor C85, capacitor C91, resistor R49, capacitor C78, resistor R46, resistor R55, capacitor C80, capacitor C81, capacitor C86, resistor R47, resistor R48, resistor R51, capacitor C92, resistor R52, capacitor C93, and TVS diode TVS1; wherein the pin 2 of the operational amplifier U19 is electrically connected with one terminal of the current signal acquisition interface XS2 through a resistor R49, a capacitor C91 and a resistor R50 in sequence, the pin 3 of the operational amplifier U19 is electrically connected with the other terminal of the current signal acquisition interface XS2 through a resistor R55, the joint point of the resistor R55 and the current signal acquisition interface XS2 is grounded, the capacitor C85 is connected with the capacitor C91 in parallel, one end of the resistor R53 is electrically connected with the joint point of the capacitor C91 and the resistor R50, the other end of the resistor R53 is electrically connected with the other terminal of the current signal acquisition interface XS2, one end of the resistor R54 is electrically connected with the joint point of the resistor R49 and the capacitor C91, the other end of the resistor R54 is electrically connected with the other terminal of the current signal acquisition interface XS2, the pin 2 of the operational amplifier U19 is also electrically connected with the pin 1 of the operational amplifier U19 through a capacitor C78 and a resistor R46 respectively, the 8 pin of the operational amplifier U19 is grounded through a capacitor C8, the 8 pin of the operational amplifier U19 is electrically connected with a +5V power supply, the 1 pin of the operational amplifier U19 is grounded through a capacitor C86 and a resistor R47 in sequence, a capacitor C81 is connected with a capacitor C82 in parallel, the 6 pin of the operational amplifier U19 is grounded through a resistor R51 and a TVS diode TVS1 in sequence, a capacitor C92 is connected with the resistor R51 in parallel, the 6 pin of the operational amplifier U19 is also electrically connected with a joint point of the capacitor C86 and the resistor R47 through a resistor R48, the 5 pin of the operational amplifier U19 is grounded through a resistor R52, the 4 pin of the operational amplifier U19 is electrically connected with a-5V power supply, and the 7 pin of the operational amplifier U19 is electrically connected with an A/D conversion circuit of a corresponding data acquisition unit as an output end of the analog conditioning circuit.
In one possible design, the a/D conversion circuit employs an LTC1412CG type AD converter and its peripheral circuits.
In one possible design, the data buffer circuit includes nand gates U24A and CH424 type data buffers, a first input end of the nand gate U24A is electrically connected with an output end of the a/D conversion circuit, a second input end of the nand gate U24A is electrically connected with the single-chip microcomputer integrated control circuit, an output end of the nand gate U24A is electrically connected with the data buffers, and the data buffers are electrically connected with the single-chip microcomputer integrated control circuit.
In one possible design, in each data acquisition module, a plurality of groups of data acquisition units are provided, and each group of data acquisition units is electrically connected with the singlechip integrated control circuit.
The beneficial effects of the utility model are concentrated in that:
1) According to the utility model, a modularized design thought is adopted, the data acquisition circuit is subjected to modularized design, circuit collocation can be rapidly carried out according to the acquisition quantity requirements of different repetition frequency pulse power supply discharge loops, free collocation combination of the data acquisition modules is realized, repeated development of the circuits is reduced, and meanwhile, the development and maintenance efficiency of the repetition frequency pulse power supply is improved.
2) In the utility model, the digital signal processors in the data acquisition module and the data processing module and the digital signal processor and the preset centralized control extension set of the repeated frequency pulse power supply are connected through the isolated RS485 bus, so that the influence of the data processing module on the repeated frequency pulse power supply is reduced while high-speed data acquisition and uploading are realized, and the working stability of the repeated frequency pulse power supply and the centralized control extension set is further ensured.
Drawings
FIG. 1 is a control block diagram of a repetition frequency pulse power waveform acquisition circuit in an embodiment;
FIG. 2 is a control block diagram of a data acquisition module in an embodiment;
FIG. 3 is a schematic circuit diagram of a data processing module in an embodiment;
FIG. 4 is a schematic circuit diagram of a single-chip integrated control circuit in an embodiment;
FIG. 5 is a schematic circuit diagram of the first communication circuit or the second communication circuit in an embodiment;
FIG. 6 is a schematic circuit diagram of an analog conditioning circuit in an embodiment;
FIG. 7 is a schematic circuit diagram of an A/D conversion circuit in an embodiment;
fig. 8 is a circuit schematic of a data buffer circuit in an embodiment.
Detailed Description
In order to more clearly illustrate the embodiments of the present utility model or the technical solutions in the prior art, the present utility model will be briefly described below with reference to the accompanying drawings and the description of the embodiments or the prior art, and it is obvious that the following description of the structure of the drawings is only some embodiments of the present utility model, and other drawings can be obtained according to these drawings without inventive effort to a person skilled in the art. It should be noted that the description of these examples is for aiding in understanding the present utility model, but is not intended to limit the present utility model.
Example 1:
as shown in fig. 1 and 2, the present embodiment provides a repetition frequency pulse power waveform acquisition circuit, which includes a data processing module and a plurality of data acquisition modules electrically connected to the data processing module respectively; as shown in fig. 3, the data processing module includes a digital signal processor and a first communication circuit electrically connected to the digital signal processor; each data acquisition module comprises a single chip microcomputer integrated control circuit, a data acquisition unit and a second communication circuit, wherein the data acquisition unit and the second communication circuit are respectively and electrically connected with the single chip microcomputer integrated control circuit, the single chip microcomputer integrated control circuit is electrically connected with the digital signal processor through the second communication circuit, the data acquisition unit comprises an analog conditioning circuit, an A/D conversion circuit and a data buffer circuit which are sequentially and electrically connected, and the data buffer circuit is electrically connected with the single chip microcomputer integrated control circuit.
In this embodiment, in each data acquisition module, the data acquisition units are provided with a plurality of groups, and the plurality of groups of data acquisition units are electrically connected with the single-chip microcomputer integrated control circuit. Specifically, in this embodiment, the plurality of sets of data acquisition units include a plurality of analog conditioning circuits, a plurality of a/D conversion circuits respectively disposed in one-to-one correspondence with the plurality of analog conditioning circuits, and a plurality of data buffer circuits respectively disposed in one-to-one correspondence with the plurality of a/D conversion circuits.
According to the embodiment, a modularized design idea is adopted, a data acquisition circuit is subjected to modularized design, circuit collocation can be rapidly carried out according to the acquisition quantity requirements of different repetition frequency pulse power supply discharge loops, free collocation combination of data acquisition modules is realized, repeated development of the circuits is reduced, and meanwhile development and maintenance efficiency of the repetition frequency pulse power supply is improved.
It should be understood that in this embodiment, the power modules are disposed in the plurality of data acquisition modules, and the power modules are configured to supply power to the modules such as the single chip microcomputer integrated control circuit, the analog conditioning circuit, the a/D conversion circuit, the data buffer circuit, and the second communication circuit in the data acquisition modules, where the power circuit of the data acquisition module adopts a voltage-reducing and voltage-stabilizing mode of "isolation transformer+linear voltage stabilizer", and the power circuit outputs smaller ripple waves, so as to ensure that the discharge current acquired by the data acquisition module is more accurate.
As shown in FIG. 4, the SCM integrated control circuit adopts a TMS320F28335 type microcontroller and peripheral circuits thereof. It should be noted that, the TMS320F28335 type microcontroller is connected to the data output interfaces of the data buffer circuits in the plurality of data acquisition units through the data bus, so as to read the data of the plurality of acquisition channels, and communicates with the data processing module through the second communication circuit, so as to upload the acquired data of the single data acquisition module to the data processing module.
In this embodiment, the first communication circuit and the second communication circuit both adopt RS485 communication circuits. The device is arranged in such a way that the plurality of data acquisition modules are electrically connected with a digital signal processor in the data processing module through an RS485 bus based on the second communication circuit, and the digital signal processor is used for collecting data acquired by all the data acquisition modules through the RS485 bus and uploading the data to a preset repeated frequency pulse power supply centralized control extension through the first communication circuit.
In this embodiment, the digital signal processors in each data acquisition module and the data processing module, and the digital signal processor and the preset centralized control extension set of the repetition frequency pulse power supply are all connected through the isolated RS485 bus, so that the influence of the data processing module on the repetition frequency pulse power supply is reduced while high-speed data acquisition and uploading are realized, and further the stability of the repetition frequency pulse power supply and the centralized control extension set in operation is ensured.
As shown in fig. 5, the first communication circuit and the second communication circuit both adopt an ADM2582EBRWZ-REEL7 type isolated RS485 driver and peripheral circuits thereof. It should be noted that, the second communication circuit is used for connecting serial port pins TXDC and RXDC of the TMS320F28335 type microcontroller in the single-chip microcomputer integrated control circuit, so as to convert the TTL serial port signal into an RS485 serial port signal, and connect the data processing module through the RS485 bus, so as to realize the communication between the plurality of data acquisition modules and the data processing module.
As shown in fig. 6, the analog conditioning circuit includes OPA2197 type operational amplifier U19, current signal collecting interface XS2, resistor R50, resistor R53, resistor R54, capacitor C85, capacitor C91, resistor R49, capacitor C78, resistor R46, resistor R55, capacitor C80, capacitor C81, capacitor C86, resistor R47, resistor R48, resistor R51, capacitor C92, resistor R52, capacitor C93 and TVS diode TVS1; wherein the pin 2 of the operational amplifier U19 is electrically connected with one terminal of the current signal acquisition interface XS2 through a resistor R49, a capacitor C91 and a resistor R50 in sequence, the pin 3 of the operational amplifier U19 is electrically connected with the other terminal of the current signal acquisition interface XS2 through a resistor R55, the joint point of the resistor R55 and the current signal acquisition interface XS2 is grounded, the capacitor C85 is connected with the capacitor C91 in parallel, one end of the resistor R53 is electrically connected with the joint point of the capacitor C91 and the resistor R50, the other end of the resistor R53 is electrically connected with the other terminal of the current signal acquisition interface XS2, one end of the resistor R54 is electrically connected with the joint point of the resistor R49 and the capacitor C91, the other end of the resistor R54 is electrically connected with the other terminal of the current signal acquisition interface XS2, the pin 2 of the operational amplifier U19 is also electrically connected with the pin 1 of the operational amplifier U19 through a capacitor C78 and a resistor R46 respectively, the 8 pin of the operational amplifier U19 is grounded through a capacitor C8, the 8 pin of the operational amplifier U19 is electrically connected with a +5V power supply, the 1 pin of the operational amplifier U19 is grounded through a capacitor C86 and a resistor R47 in sequence, a capacitor C81 is connected with a capacitor C82 in parallel, the 6 pin of the operational amplifier U19 is grounded through a resistor R51 and a TVS diode TVS1 in sequence, a capacitor C92 is connected with the resistor R51 in parallel, the 6 pin of the operational amplifier U19 is also electrically connected with a joint point of the capacitor C86 and the resistor R47 through a resistor R48, the 5 pin of the operational amplifier U19 is grounded through a resistor R52, the 4 pin of the operational amplifier U19 is electrically connected with a-5V power supply, and the 7 pin of the operational amplifier U19 is electrically connected with an A/D conversion circuit of a corresponding data acquisition unit as an output end of the analog conditioning circuit.
In this embodiment, the analog conditioning circuit further includes a diode D6, a diode D7, a diode D8, and a diode D9, the 2 pin of the operational amplifier U19 is electrically connected to the +5v power supply through the diode D6, the 2 pin of the operational amplifier U19 is further electrically connected to the-5V power supply through the diode D7 and the diode D9 in sequence, and the diode D8 is connected in parallel with the diode D7.
Specifically, the current signal to be collected is divided into a signal range of minus 5 to +5V by a voltage dividing circuit formed by a resistor R50 and a resistor R53, the divided measured signal is coupled to the other side of the capacitor by a coupling capacitor C85 and a coupling capacitor C91 and is connected to the 1-channel negative input end of the OPA2197 type operational amplifier U19 by a current limiting resistor R49, and the measured current signal is finally output into an analog signal AIN1 by an integrating circuit and a voltage follower circuit formed by the operational amplifier, each resistor and each capacitor and is input into an analog signal input pin of the A/D conversion circuit. The clamping circuit formed by the diode D6, the diode D7, the diode D8 and the diode D9 clamps the input detected signal within the range of-5 to +5V, so that the damage to the back electrode circuit caused by the over-high voltage of the high-voltage pulse generated at the detection signal end is avoided.
As shown in fig. 7, the a/D conversion circuit employs an LTC1412CG type AD converter and its peripheral circuits.
Specifically, in the a/D conversion circuit, the detected analog signal AIN1 is connected to the analog signal input positive electrode ain+ of the a/D converter through a filter circuit composed of a resistor R44 and a capacitor C79, the analog signal input negative electrode AIN of the a/D converter is grounded through a resistor R45, the CONVST pin of the a/D converter is connected to the acquisition frequency signal XF0, the input analog signal is converted into a digital signal, and the digital signal is output through parallel ports D0 to D11, and the output data is updated according to the acquisition frequency XF0, in this example, the input acquisition frequency is 200kHz.
As shown in fig. 8, the data buffer circuit includes a nand gate U24A and a CH424 type data buffer, a first input end of the nand gate U24A is electrically connected with an output end of the a/D conversion circuit, a second input end of the nand gate U24A is electrically connected with the single-chip microcomputer integrated control circuit, an output end of the nand gate U24A is electrically connected with the data buffer, and the data buffer is electrically connected with the single-chip microcomputer integrated control circuit.
Specifically, in this embodiment, each data buffer circuit includes 2 data buffers, and D0-D11 digital signals output by the a/D conversion circuit are connected to the data input end of the data buffer, so that collected data is temporarily stored in the data buffer, processing load of the monolithic integrated control circuit is reduced, errors generated when the monolithic integrated control circuit processes collected data of multiple channels are avoided, and data collection efficiency is improved. The single data buffer can only store 8-bit data, and the 2 data buffers are connected in parallel, so that the requirement of storing 12-bit data generated by the A/D conversion circuit can be met.
Finally, it should be noted that the above description is only of the preferred embodiments of the present utility model, and is not intended to limit the scope of the present utility model. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present utility model should be included in the protection scope of the present utility model.
Claims (8)
1. The utility model provides a repetition frequency pulse power waveform acquisition circuit which characterized in that: the system comprises a data processing module and a plurality of data acquisition modules which are respectively and electrically connected with the data processing module; the data processing module comprises a digital signal processor and a first communication circuit electrically connected with the digital signal processor; each data acquisition module comprises a single chip microcomputer integrated control circuit, a data acquisition unit and a second communication circuit, wherein the data acquisition unit and the second communication circuit are respectively and electrically connected with the single chip microcomputer integrated control circuit, the single chip microcomputer integrated control circuit is electrically connected with the digital signal processor through the second communication circuit, the data acquisition unit comprises an analog conditioning circuit, an A/D conversion circuit and a data buffer circuit which are sequentially and electrically connected, and the data buffer circuit is electrically connected with the single chip microcomputer integrated control circuit.
2. The repetition frequency pulse power waveform acquisition circuit of claim 1, wherein: the SCM integrated control circuit adopts TMS320F28335 type microcontroller and peripheral circuits thereof.
3. The repetition frequency pulse power supply waveform acquisition circuit according to claim 1 or 2, wherein: and the first communication circuit and the second communication circuit both adopt RS485 communication circuits.
4. The repetition frequency pulse power waveform acquisition circuit of claim 1, wherein: the first communication circuit and the second communication circuit both adopt ADM2582EBRWZ-REEL7 type isolation RS485 drivers and peripheral circuits thereof.
5. The repetition frequency pulse power waveform acquisition circuit of claim 1, wherein: the analog conditioning circuit comprises an OPA2197 type operational amplifier U19, a current signal acquisition interface XS2, a resistor R50, a resistor R53, a resistor R54, a capacitor C85, a capacitor C91, a resistor R49, a capacitor C78, a resistor R46, a resistor R55, a capacitor C80, a capacitor C81, a capacitor C86, a resistor R47, a resistor R48, a resistor R51, a capacitor C92, a resistor R52, a capacitor C93 and a TVS diode TVS1; wherein the pin 2 of the operational amplifier U19 is electrically connected with one terminal of the current signal acquisition interface XS2 through a resistor R49, a capacitor C91 and a resistor R50 in sequence, the pin 3 of the operational amplifier U19 is electrically connected with the other terminal of the current signal acquisition interface XS2 through a resistor R55, the joint point of the resistor R55 and the current signal acquisition interface XS2 is grounded, the capacitor C85 is connected with the capacitor C91 in parallel, one end of the resistor R53 is electrically connected with the joint point of the capacitor C91 and the resistor R50, the other end of the resistor R53 is electrically connected with the other terminal of the current signal acquisition interface XS2, one end of the resistor R54 is electrically connected with the joint point of the resistor R49 and the capacitor C91, the other end of the resistor R54 is electrically connected with the other terminal of the current signal acquisition interface XS2, the pin 2 of the operational amplifier U19 is also electrically connected with the pin 1 of the operational amplifier U19 through a capacitor C78 and a resistor R46 respectively, the 8 pin of the operational amplifier U19 is grounded through a capacitor C8, the 8 pin of the operational amplifier U19 is electrically connected with a +5V power supply, the 1 pin of the operational amplifier U19 is grounded through a capacitor C86 and a resistor R47 in sequence, a capacitor C81 is connected with a capacitor C82 in parallel, the 6 pin of the operational amplifier U19 is grounded through a resistor R51 and a TVS diode TVS1 in sequence, a capacitor C92 is connected with the resistor R51 in parallel, the 6 pin of the operational amplifier U19 is also electrically connected with a joint point of the capacitor C86 and the resistor R47 through a resistor R48, the 5 pin of the operational amplifier U19 is grounded through a resistor R52, the 4 pin of the operational amplifier U19 is electrically connected with a-5V power supply, and the 7 pin of the operational amplifier U19 is electrically connected with an A/D conversion circuit of a corresponding data acquisition unit as an output end of the analog conditioning circuit.
6. The repetition frequency pulse power waveform acquisition circuit of claim 1, wherein: the A/D conversion circuit adopts an LTC1412CG type AD converter and a peripheral circuit thereof.
7. The repetition frequency pulse power waveform acquisition circuit of claim 1, wherein: the data buffer circuit comprises a NAND gate U24A and a CH424 type data buffer, a first input end of the NAND gate U24A is electrically connected with an output end of the A/D conversion circuit, a second input end of the NAND gate U24A is electrically connected with the single chip microcomputer integrated control circuit, an output end of the NAND gate U24A is electrically connected with the data buffer, and the data buffer is electrically connected with the single chip microcomputer integrated control circuit.
8. The repetition frequency pulse power waveform acquisition circuit of claim 1, wherein: in each data acquisition module, the data acquisition units are provided with a plurality of groups, and the data acquisition units are electrically connected with the singlechip integrated control circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322008775.0U CN220419440U (en) | 2023-07-27 | 2023-07-27 | Repetition frequency pulse power supply waveform acquisition circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322008775.0U CN220419440U (en) | 2023-07-27 | 2023-07-27 | Repetition frequency pulse power supply waveform acquisition circuit |
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| Publication Number | Publication Date |
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| CN220419440U true CN220419440U (en) | 2024-01-30 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202322008775.0U Active CN220419440U (en) | 2023-07-27 | 2023-07-27 | Repetition frequency pulse power supply waveform acquisition circuit |
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| CN (1) | CN220419440U (en) |
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- 2023-07-27 CN CN202322008775.0U patent/CN220419440U/en active Active
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