CN220401738U

CN220401738U - ADC front end without sample-hold amplifier

Info

Publication number: CN220401738U
Application number: CN202321903009.4U
Authority: CN
Inventors: 王玉军; 王博; 韩旭
Original assignee: Chengdu Tiger Microelectronics Research Institute Co ltd
Current assignee: Chengdu Tiger Microelectronics Research Institute Co ltd
Priority date: 2023-07-19
Filing date: 2023-07-19
Publication date: 2024-01-26
Anticipated expiration: 2033-07-19

Abstract

The utility model discloses an ADC front end without a sample-hold amplifier, which comprises a signal input end Vin, a first operational amplifier, a second operational amplifier, a first switch, a second switch, a VRN1 port, a VRP1 port, a port change-over switch module, a first capacitor Cs, a second capacitor Cdither, a third capacitor Cf, a Dither port, a VTHi interface, an encoder, an adder and a subtracter. The utility model can eliminate aperture error in the non-sampling holding amplifier, add the dither signal into the sampling signal, sample and quantize the signal together, then remove the same dither signal in the digital domain, thus eliminating the periodic quantization error of the sampling capacitor, eliminating the relativity between the input and the quantization noise and reducing the quantization noise.

Description

ADC front end without sample-hold amplifier

Technical Field

The present utility model relates to high-speed ADCs, and more particularly to an ADC front-end without a sample-and-hold amplifier.

Background

The pipelined ADC stage circuit includes two parts: sub-ADCs (sub-ADCs) and MDACs. The sub-ADC quantizes the input voltage to obtain a quantized result, and then the DAC in the MDAC converts the quantized result into a corresponding analog voltage Vda. The sampling paths of the sub-ADC and MDAC tend to be different;

for the first stage of the ADC, i.e. the front end of the ADC, the input voltage is a rapidly changing input signal. If the sampling paths of the sub-ADC and the MDAC are different, mismatch problem is introduced, and the sampling time of the two paths is different, so that aperture error is caused. The conventional solution is to add a sample-and-hold amplifier at the common front end of the sub-ADC and MDAC. Its output is fully established, making the aperture error between the following sub-ADC and MDAC insignificant. For each stage of circuit after the first stage, the residual amplifier of the previous stage is equivalent to a sample-and-hold amplifier of the common front end, so that the sample-and-hold amplifier does not need to be added again. The sample-hold amplifier of the first stage is realized by an operational amplifier with a closed loop gain of 1, the power consumption of the operational amplifier can occupy about 1/5 of the whole power consumption of the pipeline ADC, and the power consumption of the sample-hold amplifier is very large, which is not beneficial to realizing the low power consumption design. Furthermore, the noise of the sample-and-hold amplifier is equivalent to the input of the ADC without attenuation, thereby reducing the signal-to-noise ratio of the ADC. Thus, sample-and-hold amplifiers are a significant burden for implementing high performance low power pipelined ADCs.

Disclosure of Invention

The utility model aims to overcome the defects of the prior art and provide the ADC front end without the sample-hold amplifier, which can eliminate aperture errors under the condition without the sample-hold amplifier.

The utility model aims at realizing the following technical scheme, which comprises a signal input end Vin, a first operational amplifier, a second operational amplifier, a first switch, a second switch, a VRN1 port, a VRP1 port, a port change-over switch module, a first capacitor Cs, a second capacitor Cdither, a third capacitor Cf, a Dither port, a VTHi interface, an encoder, an adder and a subtracter, wherein the signal input end Vin is connected with the first operational amplifier;

the signal input end Vin is connected to the inverting input end of the first operational amplifier through a first switch and a first capacitor Cs in sequence; the first end of the adder is connected with the Dither port, the second end of the adder is connected with the VTHi interface, the VTHi interface is used for inputting a reference threshold voltage signal, and the adder adds the threshold voltage signal input by the VTHi interface and the input signal of the Dither port and outputs the added threshold voltage signal to the non-inverting input end of the first operational amplifier; the Dither port is also connected to the inverting input end of the first operational amplifier through a second capacitor Cdither, the output end of the first operational amplifier is connected with the encoder, the output end of the encoder is connected with the positive input end of the subtracter, the negative input end of the subtracter is connected with the Dither port, and the output end of the subtracter is used as the first output end of the front end of the ADC;

one end of the second switch is connected between the first switch and the first capacitor Cs, and the other end of the second switch is grounded;

the VRN1 port and the VRP1 port are connected with a port switching switch module, the output end of the port switching switch module is connected between a first switch and a first capacitor Cs, and the output end of the first operational amplifier is also connected with the port switching switch module;

the inverting input end of the second operational amplifier is connected with the inverting input end of the first operational amplifier, the non-inverting input end of the second operational amplifier is grounded, the output end of the second operational amplifier is used as the second output end of the sampling circuit, and the third capacitor Cf is arranged between the output end and the inverting input end of the second operational amplifier.

The beneficial effects of the utility model are as follows: the utility model combines two sampling paths of the first-stage sub ADC and the MDAC into one path, thereby fundamentally eliminating aperture errors, constructing the front end of the ADC under the condition of no sample-hold amplifier, and effectively reducing the power consumption of the front end of the ADC; meanwhile, the dither signals are added into the sampling signals to carry out sampling quantization together, and then the same dither signals are removed in the digital domain, so that periodic quantization errors of sampling capacitors can be eliminated, correlation between input and quantization noise is eliminated, and quantization noise is reduced.

Drawings

Fig. 1 is a functional block diagram of the present utility model.

Detailed Description

The technical solution of the present utility model will be described in further detail with reference to the accompanying drawings, but the scope of the present utility model is not limited to the following description.

As shown in fig. 1, the front end of the ADC without the sample-and-hold amplifier includes a signal input Vin, a first operational amplifier, a second operational amplifier, a first switch, a second switch, a VRN1 port, a VRP1 port, a port switch module, a first capacitor Cs, a second capacitor Cdither, a third capacitor Cf, a Dither port, a VTHi interface, an encoder, an adder, and a subtractor;

In an embodiment of the present application, the first operational amplifier is a COMP operational amplifier. The second operational amplifier is an AMP amplifier. The sample-and-hold-free amplifier further comprises an nΦ1 interface connected with the first operational amplifier, wherein nΦ1 is connected to a latch control terminal in the first operational amplifier.

In an embodiment of the present application, the sample-and-hold amplifier further includes a third switch, one end of which is connected to the non-inverting input terminal of the second operational amplifier, and the other end of which is connected to the inverting input terminal of the second operational amplifier

The port change-over switch module comprises a first signal selection input end, a second signal selection input end, a fourth switch, a fifth switch, a level inverter and a signal selection output end, wherein the VRN1 port is connected with the signal selection output end through the first signal selection input end and the fourth switch in sequence, and the VRP1 port is connected with the signal selection output end through the second signal selection input end and the fifth switch in sequence;

the output end of the first operational amplifier is directly connected with the control end of the fourth switch, and the output end of the first operational amplifier is also connected with the control end of the fifth switch through the level inverter.

The sample-and-hold-free amplifier further comprises a seventh switch, wherein one end of the seventh switch is connected with the output end of the second operational amplifier, and the other end of the seventh switch is grounded. The second operational amplifier is generally connected with the post-stage circuit, the seventh switch is opened when the second operational amplifier at the front end of the ADC outputs, directly outputs signals to the post-stage circuit, and is closed when no output is provided, so that the port connected to the post-stage circuit is grounded, and the influence on devices in the post-stage circuit is avoided.

In the embodiment of the application, the front end of the ADC without the sample-and-hold amplifier can remarkably reduce power consumption and noise, the first switch is controlled by a clock phi 1, the second switch is controlled by a clock phi 2, and the third switch is controlled by a clock phi 1 p; the output of the first operational amplifier (COMP, used as a comparator) is used as the sampling result of the sub-ADC, and the output of the second operational amplifier is used as the sampling result of the MADC;

when the sub ADC is used for sampling (Vin, cs, COMP), the first switch is controlled to be closed by using the clock phi 1, the second switch is controlled to be opened by using the clock phi 2, the third switch is controlled to be opened by using the clock phi 1p, after a signal input by the signal input end Vin passes through the sampling capacitor, an input signal of a Dither port is added, the signal is sent to the inverting input end of the first operational amplifier, an input signal of the Dither port is added in a threshold voltage signal input by the VTHi interface through the adder, and then the signal is sent to the non-inverting input end of the first operational amplifier; then comparing in a first operational amplifier; the comparison result is stored in a latch of the first operational amplifier, wherein a signal output by the Nphi 1 interface is subjected to latch control, namely whether the comparator outputs the comparison result (when Nphi 1 is high, the comparison result is output, when Nphi 1 is low, the comparison result is not output), when the comparison result is output, the output comparison result is used as a sampling output of the sub-ADC to be transmitted to an Encoder (Encoder), and then the input signal of a Dither port is subtracted from the signal output by the encoding to obtain a first path of output signal at the front end of the ADC;

when MDAC sampling is carried out (the paths are VRP1/VRN1, cs and Amp), the clock phi 1 is used for controlling the first switch to be opened, the clock phi 2 is used for controlling the second switch to be closed, the clock phi 1p is used for controlling the third switch to be closed, and the comparator is controlled to output latching data; at this time, the fourth switch or the fifth switch is controlled to be turned on according to the data output by COMP, and the signals input by the control ends of the fourth switch and the fifth switch are turned on in high and low level, so that the fifth switch is turned off when the fourth switch is turned on, and the fourth switch is turned off when the fifth switch is turned on, which corresponds to the switching gating of the signals performed by the port switching switch module, and the input of one port is selected from the VRN1 port and the VRP1 port, enters the AMP amplifier through the sampling capacitor, and is output as the sampling result of the MDAC by the AMP amplifier operational amplifier. In the pipeline ADC stage circuit, a plurality of ADC front ends of the pipeline ADC stage circuit can be adopted, a sub ADC at the front end of each ADC is used for outputting a digital signal, after being encoded by an encoder, a Dither signal is subtracted to remove quantization errors, a comparator output signal is utilized to control signal gating of a VRN1 port and a VRP1 port, the gated signal is sampled by MDAC, and the obtained signal is used as a sub ADC input of the front end of the next stage ADC (the signal of a first stage sampling circuit is directly input from the outside); the sub-ADC and the MDAC share the path where the first capacitor is located, so that the aperture error is eliminated fundamentally.

Meanwhile, the Dither signal input by the Dither port is a known random signal, the Dither signal is added into the sampling signal to carry out sampling quantization together, and then the same Dither signal is removed in the digital domain, so that the Dither signal can be used for eliminating the periodic quantization error of the sampling capacitor, eliminating the correlation between the input and quantization noise and reducing the quantization noise.

It is to be noted that various corresponding changes and modifications can be made by those skilled in the art without departing from the spirit and the essence of the present utility model, and these corresponding changes and modifications should fall within the scope of the appended claims.

Claims

1. An ADC front-end without a sample-and-hold amplifier, characterized by: the circuit comprises a signal input end Vin, a first operational amplifier, a second operational amplifier, a first switch, a second switch, a VRN1 port, a VRP1 port, a port switching switch module, a first capacitor Cs, a second capacitor Cdither, a third capacitor Cf, a Dither port, a VTHi interface, an encoder, an adder and a subtracter;

2. The sample-and-hold amplifier-less ADC front-end of claim 1, wherein: the first operational amplifier is a COMP operational amplifier.

3. The sample-and-hold amplifier-less ADC front-end of claim 1, wherein: the second operational amplifier is an AMP amplifier.

4. The sample-and-hold amplifier-less ADC front-end of claim 1, wherein: the sample-and-hold-free amplifier further comprises an nΦ1 interface connected with the first operational amplifier, wherein nΦ1 is connected to a latch control terminal in the first operational amplifier.

5. The sample-and-hold amplifier-less ADC front-end of claim 1, wherein: the sample-and-hold amplifier further comprises a third switch, one end of the third switch is connected with the non-inverting input end of the second operational amplifier, and the other end of the third switch is connected with the inverting input end of the second operational amplifier.

6. The sample-and-hold amplifier-less ADC front-end of claim 1, wherein: the port change-over switch module comprises a first signal selection input end, a second signal selection input end, a fourth switch, a fifth switch, a level inverter and a signal selection output end, wherein the VRN1 port is connected with the signal selection output end through the first signal selection input end and the fourth switch in sequence, and the VRP1 port is connected with the signal selection output end through the second signal selection input end and the fifth switch in sequence;

7. The sample-and-hold amplifier-less ADC front-end of claim 1, wherein: the sample-and-hold-free amplifier further comprises a seventh switch, wherein one end of the seventh switch is connected with the output end of the second operational amplifier, and the other end of the seventh switch is grounded.