CN220382096U - Power semiconductor module and vehicle - Google Patents

Abstract

The utility model relates to a power semiconductor module and a vehicle, comprising a bearing plate and a plurality of chips; the plurality of chips are respectively a first bridge arm chip and a second bridge arm chip; the bearing plate is provided with a first metal area, a second metal area, a third metal area and a fourth metal area which are sequentially arranged at intervals; the first bridge arm chip is connected to the second metal area, and the signal control area of the first bridge arm chip is positioned at one end of the first bridge arm chip, which is away from the third metal area; the signal control area of the first bridge arm chip is connected with the first metal area; the second bridge arm chip is connected to the third metal area, and the signal control area of the second bridge arm chip is positioned at one end of the second bridge arm chip, which is away from the second metal area; the signal control area of the second bridge arm chip is connected with the fourth metal area. The arrangement can enable the signal control areas of the first bridge arm chip and the second bridge arm chip to be far away, so that a large arrangement space can be reserved for related circuits for leading out the signal control areas of the first bridge arm chip and the second bridge arm chip, and the power semiconductor module can be assembled conveniently.

Description

Power semiconductor module and vehicle

Technical Field

The utility model belongs to the technical field of semiconductors, and relates to a power semiconductor module and a vehicle.

Background

In recent years, power semiconductor modules have been widely used in industries such as electric automobiles, photovoltaic power generation, wind power generation, industrial frequency conversion, and the like. The power semiconductor module generally includes a plurality of MOSFET power chips 20, a substrate, and corresponding leads, both the chips 20 and the leads being disposed on the substrate, the leads being for extracting corresponding regions of the chips 20.

As shown in fig. 1, the chip 20 includes a kelvin source region 203, a gate region 202, and a drain region 204, wherein the kelvin source region 203 and the gate region 202 are both signal control regions 201 of the chip 20, the kelvin source region 203 and the gate region 202 are both located on the front surface of the chip 20, and the drain region 204 is located on the back surface of the chip 20. In addition, the front surface of the chip 20 is further formed with a first source region 205, and the first source region 205 and the kelvin source region 203 are electrically connected inside the chip 20, which are equivalent to two metal regions led out by the source of the chip 20 on the front surface of the chip 20; the first source region 205 is for large current to pass. Wherein the kelvin source region 203 and the first source region 205 are located at two ends of the chip 20, respectively, and the gate region 202 and the kelvin source region 203 are located at the same end of the chip 20.

In addition, some of the plurality of chips 20 of the power semiconductor module belong to the upper arm chip, and others belong to the lower arm chip. In the existing power semiconductor module, the control area 201 of the upper bridge arm chip and the control area 201 of the lower bridge arm chip are too close, and corresponding lines for leading out the control areas 201 of the upper bridge arm chip and the lower bridge arm chip are too dense, so that the power semiconductor module is troublesome to assemble.

Disclosure of Invention

Aiming at the problem that in the prior art, the control area of the upper bridge arm chip and the control area of the lower bridge arm chip of the power semiconductor module are too close to each other, so that the power semiconductor module is troublesome to assemble, the power semiconductor module and the vehicle are provided.

In order to solve the technical problems, in one aspect, an embodiment of the present utility model provides a power semiconductor module, including a carrier board and a plurality of chips; the chips are respectively a first bridge arm chip and a second bridge arm chip; the bearing plate is provided with a first metal area, a second metal area, a third metal area and a fourth metal area which are sequentially arranged at intervals; the first bridge arm chip is connected to the second metal region, and the signal control region of the first bridge arm chip is positioned at one end of the first bridge arm chip, which is away from the third metal region; the signal control area of the first bridge arm chip is connected with the first metal area; the second bridge arm chip is connected to the third metal area, and the signal control area of the second bridge arm chip is positioned at one end of the second bridge arm chip, which is away from the second metal area; and the signal control area of the second bridge arm chip is connected with the fourth metal area.

Optionally, the power semiconductor module further includes a first power pin and a second power pin, where the first power pin is connected with the third metal region, and the second power pin is connected with the second metal region; the first power pin and the second power pin are overlapped.

Optionally, the power semiconductor module further includes a first metal pin and a second metal pin; the first metal pins and the signal control areas of the first bridge arm chip are welded to the first metal areas; and the second metal pins and the signal control area of the second bridge arm chip are welded to the fourth metal area.

Optionally, the carrier plate includes a first substrate and a second substrate; the chip is arranged between the first substrate and the second substrate, and the chip is respectively connected with the first substrate and the second substrate.

Optionally, the second metal region includes a first direct current region and a first alternating current region; the third metal region comprises a second direct current region and a second alternating current region; the first direct current region and the second alternating current region are both arranged on the surface of the first substrate, which is close to the second substrate, and the second direct current region and the first alternating current region are both arranged on the surface of the second substrate, which is close to the first substrate; the drain electrode region of the first bridge arm chip is connected with the first direct current region, and the first source electrode region of the first bridge arm chip is connected with the first alternating current region; the drain electrode region of the second bridge arm chip is connected with the second alternating current region, and the first source electrode region of the second bridge arm chip is connected with the second direct current region.

Optionally, the power semiconductor module further includes a first power pin, a second power pin, and a third power pin; the first power pin is connected with the second direct current region; the second power pin is connected with the first direct current region; the third power pin is respectively connected with the first alternating current area and the second alternating current area.

Optionally, a first sampling area and a second sampling area are further arranged on the first substrate; the power semiconductor module further comprises a first sampling pin and a second sampling pin; the first sampling area is connected with the first direct current area, and the second sampling area is connected with the second alternating current area; one end of the first sampling pin is connected with the first sampling area, and the other end of the first sampling pin extends out of a space between the first substrate and the second substrate; one end of the second sampling pin is connected with the second sampling area, and the other end of the second sampling pin extends out of the space between the first substrate and the second substrate.

Optionally, the control region of the chip includes a kelvin source region and a gate region; the first metal region comprises a first metal signal region and a second metal signal region which are electrically isolated, and the fourth metal region comprises a third metal signal region and a fourth metal signal region which are electrically isolated; the Kelvin source region of the first bridge arm chip is connected with the first metal signal region, and the grid region of the first bridge arm chip is connected with the second metal signal region; and the Kelvin source region of the second bridge arm chip is connected with the third metal signal region, and the grid region of the second bridge arm chip is connected with the fourth metal signal region.

Optionally, the carrier plate includes a first substrate and a second substrate, and the chip is disposed between the first substrate and the second substrate; the power semiconductor module further includes a first metal pin including a first source pin and a first gate pin; the first metal signal region comprises a first source electrode control region, a second source electrode control region and a first conductive block; the first source electrode control region is arranged on the first substrate, the second source electrode control region is arranged on the second substrate, and two ends of the first conductive block are respectively connected with the first source electrode control region and the second source electrode control region; one end of the first source pin is connected with the first source control region, and the other end of the first source pin extends out of a space between the first substrate and the second substrate; the Kelvin source region of the first bridge arm chip is connected with the second source control region; the second metal signal area is arranged on the second substrate, one end of the first gate pin is connected with the second metal signal area, and the other end of the first gate pin extends out of a space between the first substrate and the second substrate.

Optionally, the power semiconductor module further includes a second metal pin, where the second metal pin includes a second source pin and a second gate pin; the third metal signal region comprises a third source electrode control region, a fourth source electrode control region and a second conductive block; the third source electrode control region is arranged on the first substrate, the fourth source electrode control region is arranged on the second substrate, and two ends of the second conductive block are respectively connected with the third source electrode control region and the fourth source electrode control region; one end of the second source pin is connected with the third source control region, and the other end of the second source pin extends out of the space between the first substrate and the second substrate; the Kelvin source region of the second bridge arm chip is connected with the fourth source control region; the fourth metal signal area is arranged on the second substrate, one end of the second grid electrode pin is connected with the fourth metal signal area, and the other end of the second grid electrode pin extends out of a space between the first substrate and the second substrate.

In order to solve the above technical problems, another aspect of the present utility model provides a vehicle, including the power semiconductor module described in any one of the above.

In the power semiconductor module and the vehicle provided by the embodiment of the utility model, the signal control area of the first bridge arm chip and the signal control area of the second bridge arm chip are far away, the first metal area is positioned at one side of the first bridge arm chip, which is away from the second bridge arm chip, and the second metal area is positioned at one side of the second bridge arm chip, which is away from the first bridge arm chip, so that a larger arrangement space can be reserved for related lines for leading out the signal control areas of the first bridge arm chip and the second bridge arm chip, thereby facilitating the assembly of the power semiconductor module, and cross interference of the leading-out lines of the signal control areas of the first bridge arm chip and the second bridge arm chip can be effectively avoided.

Drawings

FIG. 1 is a schematic diagram of a chip according to an embodiment of the present utility model;

fig. 2 is a schematic structural diagram of a power semiconductor module according to an embodiment of the present utility model;

fig. 3 is an exploded view of a power semiconductor module according to an embodiment of the present utility model;

fig. 4 is a schematic diagram illustrating an internal structure of a power semiconductor module according to an embodiment of the present utility model;

FIG. 5 is a schematic diagram of a metal region on a first substrate of a power semiconductor module according to an embodiment of the present utility model;

FIG. 6 is a schematic diagram of a metal region on a second substrate of a power semiconductor module according to an embodiment of the present utility model;

fig. 7 is a schematic diagram of a chip of a power semiconductor module according to an embodiment of the utility model, and the chip is matched with a second substrate and the second substrate.

Reference numerals in the specification are as follows:

100. a power semiconductor module;

10. a carrying plate; 1. a first metal region; 11. a first metal signal region; 111. a first source control region; 112. a second source control region; 113. a first connection block; 114. a first sub-region; 12. a second metal signal region; 2. a second metal region; 21. a first direct current region; 22. a first ac section; 3. a third metal region; 31. a second DC region; 32. a second alternating current region; 4. a fourth metal region; 41. a third metal signal region; 411. a fourth source control region; 412. a fourth source control region; 413. a second connection block; 414. a second sub-region; 42. a fourth metal signal region; 5. a first substrate; 51. a first sampling region; 52. a second sampling region; 6. a second substrate;

20. a chip; 201. a signal control region; 202. a gate region; 203. a Kelvin source region; 204. a drain region; 205. a first source region;

30. a first power pin;

40. a second power pin;

50. a third power pin;

60. a first metal pin; 601. a first source lead; 602. a first gate pin;

70. a second metal pin; 701. a second source lead; 702. a second gate pin;

80. a first sampling pin;

90. and a second sampling pin.

Detailed Description

In order to make the technical problems, technical schemes and beneficial effects solved by the utility model more clear, the utility model is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the utility model.

As shown in fig. 2 to 4, in an embodiment, the power semiconductor module 100 includes a carrier plate 10 and a plurality of chips 20; the plurality of chips 20 are a first bridge arm chip 20a and a second bridge arm chip 20b, respectively; the bearing plate 10 is provided with a first metal area 1, a second metal area 2, a third metal area 3 and a fourth metal area 4 which are sequentially arranged at intervals; the first bridge arm chip 20a is connected to the second metal area 2, and the signal control area 201 of the first bridge arm chip 20a is located at one end of the first bridge arm chip 20a, which is away from the third metal area 3; the signal control area 201 of the first bridge arm chip 20a is connected with the first metal area 1; the second bridge arm chip 20b is connected to the third metal area 3, and the signal control area 201 of the second bridge arm chip 20b is located at one end of the second bridge arm chip 20b away from the second metal area 2; the signal control region 201 of the second bridge arm chip 20b is connected to the fourth metal region 4.

In this embodiment, the first bridge arm chip 20a is electrically connected to the first metal region 1 and the second metal region 2, respectively, and the second bridge arm chip 20b is electrically connected to the third metal region 3 and the fourth metal region 4, respectively. The first metal region 1 belongs to a line leading out of the control region of the first bridge arm chip 20a, and the second metal region 2 belongs to a line leading out of the control region of the second bridge arm chip 20 b.

In addition, the signal control area 201 of the first bridge arm chip 20a and the signal control area 201 of the second bridge arm chip 20b are far apart, the first metal area 1 is located at one side of the first bridge arm chip 20a, which is away from the second bridge arm chip 20b, and the second metal area 2 is located at one side of the second bridge arm chip 20b, which is away from the first bridge arm chip 20a, so that a larger arrangement space can be reserved for related lines for leading out the signal control areas of the two, thereby facilitating the assembly of the power semiconductor module 100, and the arrangement can also effectively avoid cross interference of the leading-out lines of the signal control areas of the first bridge arm chip 20a and the second bridge arm chip 20 b.

The chip 20 may be a SIC MOSFET device, the structure of which is shown in fig. 1. At this time, the signal control region 201 of the first bridge arm chip 20a being located at the end of the first bridge arm chip 20a facing away from the third metal region 3 means that the signal control region 201 of the first bridge arm chip 20a is located at the side of the first source region 205 of the first bridge arm chip 20a facing away from the third metal region 3; the signal control region 201 of the second bridge arm chip 20b being located at the end of the second bridge arm chip 20b facing away from the second metal region 2 means that the signal control region 201 of the second bridge arm chip 20b is located at the side of the first source region 205 of the second bridge arm chip 20b facing away from the second metal region 2. The connection of the signal control region 201 of the first bridge arm chip 20a with the first metal region 1 means that the gate region 202 and the kelvin source region 203 of the first bridge arm chip 20a are respectively connected with the first metal region 1; the connection of the first bridge arm chip 20a and the second metal region 2 means that the drain region 204 and the first source region 205 of the first bridge arm chip 20a are respectively connected to the second metal region 2; the connection of the control region of the second bridge arm chip 20b with the fourth metal region 4 means that the gate region 202 and the kelvin source region 203 of the second bridge arm chip 20b are respectively connected with the fourth metal region 4; the connection of the second bridge arm chip 20b to the third metal region 3 means that the drain region 204 and the first source region 205 of the second bridge arm chip 20b are respectively connected to the third metal region 3.

In an embodiment, the first bridge arm chip 20a and the second bridge arm chip 20b are provided with a plurality, where "plurality" refers to greater than or equal to two. In addition, the first metal region 1, the second metal region 2, the third metal region 3, and the fourth metal region 4 are arranged at intervals along the first direction; the plurality of first bridge arm chips 20a are sequentially and alternately arranged on the second metal region 2 along the second direction, and the plurality of second bridge arm chips 20b are sequentially and alternately arranged on the third metal region 3 along the second direction, wherein the first direction is perpendicular to the second direction.

In an actual scenario, the first direction is the width direction of the power semiconductor module 100, and the second direction is the length direction of the power semiconductor module 100. In addition, the number of first leg chips 20a may be equal to the number of second leg chips 20 b. Note that, the connection between each first arm chip 20a and the carrier plate 10 is the same, and the connection between each second arm chip 20b and the carrier plate 10 is the same.

As shown in fig. 2 to 4, in an embodiment, the power semiconductor module 100 further includes a first power pin 30 and a second power pin 40, where the first power pin 30 is electrically connected to the third metal region 3, and the second power pin 40 is electrically connected to the second metal region 2; the first power pin 30 and the second power pin 40 are arranged to overlap. This is advantageous in enhancing the effect of magnetic fluxes canceling each other and reducing parasitic inductance of the entire power semiconductor module 100. It should be noted that the first power pin 30 and the second power pin 40 are separated by a corresponding insulating object so as to avoid a short circuit therebetween.

As shown in fig. 2 to 4, in an embodiment, the power semiconductor module 100 further includes a third power pin 50, and the third power pin 50 is connected to the second metal region 2 and the third metal region 3. When the power semiconductor module 100 is used later, the power semiconductor module 100 can be used in an inverter circuit to convert direct current into alternating current, at this time, the first power pin 30 can be connected with the negative electrode of the direct current power supply, the second power pin 40 can be connected with the positive electrode of the direct current power supply, and the third power pin 50 can output alternating current to the outside. Of course, in the following use, the power semiconductor module 100 may be used in a rectifying circuit, where the third power pin 50 is connected to an ac power source, the first power pin 30 may be used as a negative output terminal, and the second power pin 40 may be used as a positive output terminal.

As shown in fig. 2 and 4, in an embodiment, the power semiconductor module 100 further includes a first metal pin 60 and a second metal pin 70; the first metal pin 60 and the signal control region 201 of the first bridge arm chip 20a are welded to the first metal region 1; the second metal pins 70 and the signal control regions 201 of the second bridge arm chip 20b are welded to the fourth metal region 4. Wherein the first metal pin 60 is electrically connected with the first metal region 1; the second metal pin 70 is electrically connected to the fourth metal region 4. In addition, in actual production, welding may be performed by welding or sintering.

Because the first metal pin 60 and the signal control region 201 of the first bridge arm chip 20a are electrically connected with the first metal region 1, the first metal pin 60 and the signal control region 201 of the first bridge arm chip 20a can be electrically connected through the first metal region 1, and at this time, the first metal pin 60 and the signal control region 201 of the first bridge arm chip 20a can be electrically connected without binding wires. Likewise, the second metal pin 70 and the control region of the second bridge arm chip 20b may be electrically connected through the second metal region 2, that is, the two may be electrically connected without a binding wire. The binding wire is separated by vibration of the module due to external factors by electrically connecting the metal pins with the control region of the chip 20 through the binding wire, which easily causes the electrical connection between the binding wire and the metal pins (and the control region of the chip 20) to be broken, and the problem can be effectively prevented by electrically connecting the metal pins with the control region of the chip 20 through the metal region on the carrier plate 10, thereby improving the stability of the power semiconductor module 100.

In an embodiment, other areas of the chip 20 may be connected to corresponding metal areas on the carrier plate 10 by soldering, wherein the chip 20 may be soldered to corresponding metal areas on the carrier plate 10 by soldering or sintering. The first metal pins 60, the second metal pins 70, the first power pins 30, the second power pins 40, and the third power pins 50 may be welded to corresponding metal areas on the carrier plate 10 by ultrasonic welding or solder welding.

As shown in fig. 3 to 7, in an embodiment, the carrier plate 10 includes a first substrate 5 and a second substrate 6; the chip 20 is disposed between the first substrate 5 and the second substrate 6, and the chip 20 is connected to the first substrate 5 and the second substrate 6, respectively. The two sides of the chip 20 can respectively dissipate heat through the first substrate 5 and the second substrate 6, so that the heat dissipation efficiency of the chip 20 can be improved, and the heat dissipation efficiency of the whole power semiconductor module 100 can be further improved. Wherein the back surface of the chip 20 faces the first substrate 5 and the front surface of the chip 20 faces the second substrate 6.

The arrangement direction (defined as a third direction) of the first substrate 5 and the second substrate 6 is the thickness direction of the power semiconductor module 100, the third direction is perpendicular to the first direction, and the third direction is perpendicular to the second direction.

The first substrate 5 and the second substrate 6 are both insulating plates, and both may be ceramic plates. In actual use, corresponding heat dissipation devices can be mounted on the first substrate 5 and the second substrate 6, so as to improve the heat dissipation efficiency of the power semiconductor module 100. At this time, a first metal layer is disposed on the surface of the first substrate 5 facing away from the second substrate 6, a second metal layer is disposed on the surface of the second substrate 6 facing away from the first substrate 5, and the first metal layer and the second metal layer are both used for welding corresponding heat sinks.

As shown in fig. 4 to 6, in an embodiment, the second metal region 2 includes a first direct current region 21 and a first alternating current region 22; the third metal region 3 includes a second direct current region 31 and a second alternating current region 32; the first direct current region 21 and the second alternating current region 32 are both arranged on the first substrate 5, and the second direct current region 31 and the first alternating current region 22 are both arranged on the second substrate 6; the drain region 204 of the first bridge arm chip 20a is connected to the first dc region 21, and the first source region 205 of the first bridge arm chip 20a is connected to the first ac region 22; the drain region 204 of the second leg chip 20b is connected to the second ac region 32, and the first source region 205 of the second leg chip 20b is connected to the second dc region 31. The first dc region 21 and the second ac region 32 are metal layers disposed on the surface of the first substrate 5 near the second substrate 6, and are disposed at intervals; the second dc region 31 and the first ac region 22 are metal layers disposed on the surface of the second substrate 6 adjacent to the first substrate 5, and are disposed at intervals.

In the present embodiment, the drain region 204 and the first source region 205 of the chip 20 are led out through the corresponding metal regions on both the first substrate 5 and the second substrate 6, respectively, and the use of the binder wire can be reduced. The arrangement of the present embodiment can reduce the use of binding-wires (even without using binding-wires) compared to a power semiconductor module having only one substrate, so that the overall thickness of the power semiconductor module 100 can be reduced, thereby reducing the volume of the power semiconductor module 100.

In this embodiment, the first power pin 30 is actually electrically connected to the second dc region 31, and the two may be welded together; the second power pin 40 is actually electrically connected to the first dc region 21, and may be welded together; the third power pin 50 is actually electrically connected to the first ac section 22 and the second ac section 32, respectively, wherein the third power pin 50 is welded to the first ac section 22 and the third power pin 50 is also welded to the second ac section 32.

In addition, the first power pin 30, the second power pin 40, and the third power pin 50 all protrude from the space between the first substrate 5 and the second substrate 6 to facilitate connection with external circuits. The space between the first substrate 5 and the second substrate 6 refers to a space between two opposite regions, for example, a first region of the first substrate 5 is opposite to a second region of the second substrate 6, the space between the first substrate 5 and the second substrate 6 refers to a space between the first region and the second region, and in addition, in the orthographic projection of the first substrate 5 on the second substrate 6, the orthographic projection of the first region coincides with the second region.

Further, the first and second power pins 30 and 40 protrude from the same side in the length direction of the power semiconductor module 100 from the space between the first and second substrates 5 and 6, and the first and third power pins 30 and 50 protrude from both sides in the length direction of the power semiconductor module 100 from the space between the first and second substrates 5 and 6, respectively.

As shown in fig. 4, in an embodiment, the first metal region 1 includes a first metal signal region 11 and a second metal signal region 12 that are electrically isolated, and the fourth metal region 4 includes a third metal signal region 41 and a fourth metal signal region 42 that are electrically isolated; the kelvin source region 203 of the first bridge arm chip 20a is connected with the first metal signal region 11, and the gate region 202 of the first bridge arm chip 20a is connected with the second metal signal region 12; the kelvin source region 203 of the second leg chip 20b is connected to the third metal signal region 41 and the gate region 202 of the second leg chip 20b is connected to the fourth metal signal region 42.

As shown in fig. 3 and 4, the first metal signal region 11 includes a first source control region 111, a second source control region 112, and a first conductive block 113; the first source control region 111 is disposed on the first substrate 5, the second source control region 112 is disposed on the second substrate 6, and two ends of the first conductive block 113 are electrically connected to the first source control region 111 and the second source control region 112, respectively; the second metal signal region 12 is disposed on the second substrate 6 and spaced apart from the second source control region 112.

As shown in fig. 2 to 4, the first metal lead 60 includes a first source lead 601 and a first gate lead 602; one end of the first source lead 601 is electrically connected to the first source control region 111, and the other end of the first source lead 601 extends out of the space between the first substrate 5 and the second substrate 6; one end of the first gate pin 602 is electrically connected to the second metal signal region 12, and the other end of the first gate pin 602 protrudes out of the space between the first substrate 5 and the second substrate 6. The kelvin source region 203 of the first bridge arm chip 20a is electrically connected to the second source control region 112, and finally, the kelvin source region 203 of the first bridge arm chip 20a is led out through the second source control region 112, the first conductive block 113, the first source control region 111 and the first source lead 601 in sequence. The gate region 202 of the first bridge arm chip 20a is led out through the second metal signal region 12 and the first gate pin 602 in sequence.

In this embodiment, the first source lead 601 is connected to the first substrate 5, the first gate lead 602 is connected to the second substrate 6, and the operation of connecting the first source lead 601 to the first substrate 5 and the operation of connecting the first gate lead 602 to the second substrate 6 can be performed at different stations at the same time during the production process, so that the assembly efficiency of the power semiconductor module 100 can be improved.

The two ends of the first conductive block 113 are respectively welded to the first source control region 111 and the second source control region 112, the first source lead 601 is welded to the first source control region 111, the first gate lead 602 is welded to the second metal signal region 12, the kelvin source region 203 of the first bridge arm chip 20a is welded to the second source control region 112, and the gate of the first bridge arm chip 20a is welded to the second metal signal region 12.

As shown in fig. 2 to 4, the second metal lead 70 includes a second source lead 701 and a second gate lead 702; the third metal signal region 41 includes a third source control region 411, a fourth source control region 412, and a second conductive block 413; the third source control region 411 is disposed on the first substrate 5, the fourth source control region 412 is disposed on the second substrate 6, and two ends of the second conductive block 413 are respectively connected to the third source control region 411 and the fourth source control region 412; the fourth metal signal region 42 is disposed on the second substrate 6 and spaced apart from the fourth source control region 412. One end of the second source lead 701 is connected to the third source control region 411, and the other end of the second source lead 701 protrudes out of the space between the first substrate 5 and the second substrate 6; the kelvin source region 203 of the second bridge arm chip 20b is connected to the fourth source control region 412; one end of the second gate lead 702 is connected to the fourth metal signal region 42, and the other end of the second gate lead 702 protrudes out of the space between the first substrate 5 and the second substrate 6.

Finally, the kelvin source region 203 of the second bridge arm chip 20b is led out through the fourth source control region 412, the second conductive block 413, the third source control region 411, and the second source lead 701 in order. The gate region 202 of the second bridge arm chip 20b is led out through the fourth metal signal region 42 and the second gate pin 702 in sequence.

In this embodiment, the second source lead 701 is connected to the first substrate 5, the second gate lead 702 is connected to the second substrate 6, and the operation of connecting the second source lead 701 to the first substrate 5 and the operation of connecting the second gate lead 702 to the second substrate 6 can be performed at different stations simultaneously during the production process, so as to improve the assembly efficiency of the power semiconductor module 100.

The two ends of the second conductive block 413 are respectively welded to the third source control region 411 and the fourth source control region 412, the second source lead 701 is welded to the third source control region 411, the second gate lead 702 is welded to the fourth metal signal region 42, the kelvin source region 203 of the second bridge arm chip 20a is welded to the fourth source control region 412, and the gate of the second bridge arm chip 20a is welded to the fourth metal signal region 42.

As shown in fig. 6, in an embodiment, the second source control region 112 includes a plurality of first sub-regions 114 spaced apart along the second direction; the fourth source control region 412 includes a plurality of second sub-regions 414 spaced apart along the second direction; the first conductive block 113 and the second conductive block 413 are each plural; a first sub-region is connected to the first source control region 111 through a first conductive block 113; a second sub-region is connected to the third source control region 411 by a second conductive block 413.

The second metal signal regions 12 may pass between adjacent first sub-regions 114 to connect the gate regions 202 of the respective first leg chips 20a, so that the second metal signal regions 12 do not need to cross the second source control regions 112, facilitating production and assembly. Likewise, fourth metal signal regions 42 may pass between adjacent second sub-regions 414 to connect gate regions 202 of respective second leg chips 20b, such that fourth metal signal regions 42 do not need to cross fourth source control regions 412, facilitating production assembly.

In an embodiment, the first source lead 601, the first gate lead 602, the second source lead 701, and the second gate lead 702 all extend from the same side of the carrier 10 to the space between the first substrate 5 and the second substrate 6; the first gate lead 602, the first source lead 601, the second source lead 701 and the second gate lead 702 are sequentially arranged at intervals; and the arrangement directions of the first gate lead 602, the first source lead 601, the second source lead 701 and the second gate lead 702 are parallel to the arrangement directions of the first metal region 1, the second metal region 2, the third metal region 3 and the fourth metal region 4.

Specifically, the fourth power pin is located on the same side as the first power pin 30, and the first source pin 601 and the second source pin 701 are located on two sides of the first power pin 30 respectively.

As shown in fig. 4, 5 and 7, in an embodiment, the first substrate 5 is further provided with a first sampling area 51 and a second sampling area 52; the power semiconductor module 100 further includes a first sampling pin 80 and a second sampling pin 90; the first sampling region 51 is electrically connected to the first ac region 21, and the second sampling region 52 is electrically connected to the second ac region 32; one end of the first sampling pin 80 is electrically connected with the first sampling region 51, and the other end of the first sampling pin 80 extends out of the space between the first substrate 5 and the second substrate 6; one end of the second sampling pin 90 is electrically connected to the second sampling region 52, and the other end of the second sampling pin 90 protrudes out of the space between the first substrate 5 and the second substrate 6. During subsequent use of the power semiconductor module 100, samples from the first power pin 30 and the third power pin 50 are required, and the arrangement of this embodiment may be such that samples at the first sampling pin 80 are replaced with samples at the first power pin 30; and may be sampled at the second sampling pin 90 instead of the third power pin 50, thus avoiding the problem of current oscillation caused by direct sampling.

In addition, the first sampling pin 80 is welded to the first sampling region 51, and the second sampling pin 90 is welded to the second sampling region 52.

In the production process, a metal layer may be first prepared on the first substrate 5, and then the corresponding area of the metal layer is removed through exposure, development, etching, etc., so as to obtain the first source control area 111, the first dc area 21, the second ac area 32, the third source control area 411, the first sampling area 51, and the second sampling area 52 on the first substrate 5.

Similarly, a metal layer may be first prepared on the second substrate 6, and then the corresponding area of the metal layer is removed through exposing, developing, etching, etc., so as to obtain the second metal signal area 12, the second source control area 112, the first ac area 22, the second dc area 31, the fourth source control area 412, and the fourth metal signal area 42 on the second substrate 6.

In an embodiment, the metal layers on both the first substrate 5 and the second substrate 6 may cover the corresponding insulating layers except for the regions for electrical connection with other elements, so as to improve the insulating effect. It should be noted that the first arm chip 20a is a part of a first arm of the power semiconductor module 100, and the second arm chip 20b is a part of a second arm of the power semiconductor module 100. In addition, the first bridge arm and the second bridge arm are symmetrically arranged, so that parasitic inductance of the whole power semiconductor module 100 can be reduced. Specifically, the first bridge arm chips 20a and the second bridge arm chips 20b are symmetrically disposed with respect to a plane (defined as a first plane) perpendicular to the first direction, where each first bridge arm chip 20a has a second bridge arm chip 20b symmetrical with respect to the first plane; in addition, the first source control region 111 and the third source control region 411 are symmetrical with respect to a first plane, the second source control region 112 and the fourth source control region 412 are symmetrical with respect to the first plane, and the second metal signal region 12 and the fourth metal signal region 42 are symmetrical with respect to the first plane; at least a portion of both the first dc region 21 and the second ac region 32 are symmetrical about a first plane, and at least a portion of both the second dc region 31 and the first ac region 22 are symmetrical about the first plane.

The embodiment of the present utility model also provides a vehicle, which uses the power semiconductor module 100 according to any one of the above embodiments. In practical use, the power semiconductor module 100 is used in an inverter circuit, and typically three power semiconductor modules 100 are used together, and the third power pins 50 of the three power semiconductor modules 100 are respectively used as output ends of a three-phase power supply, for example, the third power pins of the three power semiconductor modules are respectively electrically connected to U, V, W three phases of the motor.

The foregoing description of the preferred embodiments of the utility model is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the utility model.

Claims (11)

1. The power semiconductor module is characterized by comprising a bearing plate and a plurality of chips;

the chips are respectively a first bridge arm chip and a second bridge arm chip;

the bearing plate is provided with a first metal area, a second metal area, a third metal area and a fourth metal area which are sequentially arranged at intervals;

the first bridge arm chip is connected to the second metal region, and the signal control region of the first bridge arm chip is positioned at one end of the first bridge arm chip, which is away from the third metal region; the signal control area of the first bridge arm chip is connected with the first metal area;

the second bridge arm chip is connected to the third metal area, and the signal control area of the second bridge arm chip is positioned at one end of the second bridge arm chip, which is away from the second metal area; and the signal control area of the second bridge arm chip is connected with the fourth metal area.

2. The power semiconductor module of claim 1, further comprising a first power pin and a second power pin, the first power pin being connected to the third metal region and the second power pin being connected to the second metal region;

the first power pin and the second power pin are overlapped.

3. The power semiconductor module of claim 1, further comprising a first metal pin and a second metal pin;

the first metal pins and the signal control areas of the first bridge arm chip are welded to the first metal areas;

and the second metal pins and the signal control area of the second bridge arm chip are welded to the fourth metal area.

4. The power semiconductor module of claim 1, wherein the carrier plate comprises a first substrate and a second substrate;

the chip is arranged between the first substrate and the second substrate, and the chip is respectively connected with the first substrate and the second substrate.

5. The power semiconductor module of claim 4, wherein the second metal region comprises a first direct current region and a first alternating current region; the third metal region comprises a second direct current region and a second alternating current region;

the first direct current region and the second alternating current region are both arranged on the surface of the first substrate, which is close to the second substrate, and the second direct current region and the first alternating current region are both arranged on the surface of the second substrate, which is close to the first substrate;

the drain electrode region of the first bridge arm chip is connected with the first direct current region, and the first source electrode region of the first bridge arm chip is connected with the first alternating current region;

the drain electrode region of the second bridge arm chip is connected with the second alternating current region, and the first source electrode region of the second bridge arm chip is connected with the second direct current region.

6. The power semiconductor module of claim 5, further comprising a first power pin, a second power pin, and a third power pin;

the first power pin is connected with the second direct current region;

the second power pin is connected with the first direct current region;

the third power pin is respectively connected with the first alternating current area and the second alternating current area.

7. The power semiconductor module according to claim 5, wherein the first substrate is further provided with a first sampling region and a second sampling region; the power semiconductor module further comprises a first sampling pin and a second sampling pin;

the first sampling area is connected with the first direct current area, and the second sampling area is connected with the second alternating current area;

one end of the first sampling pin is connected with the first sampling area, and the other end of the first sampling pin extends out of a space between the first substrate and the second substrate;

one end of the second sampling pin is connected with the second sampling area, and the other end of the second sampling pin extends out of the space between the first substrate and the second substrate.

8. The power semiconductor module of any of claims 1-7, wherein the control region of the chip comprises a kelvin source region and a gate region;

the first metal region comprises a first metal signal region and a second metal signal region which are electrically isolated, and the fourth metal region comprises a third metal signal region and a fourth metal signal region which are electrically isolated;

the Kelvin source region of the first bridge arm chip is connected with the first metal signal region, and the grid region of the first bridge arm chip is connected with the second metal signal region;

and the Kelvin source region of the second bridge arm chip is connected with the third metal signal region, and the grid region of the second bridge arm chip is connected with the fourth metal signal region.

9. The power semiconductor module of claim 8, wherein the carrier plate comprises a first substrate and a second substrate, the die being disposed between the first substrate and the second substrate;

the power semiconductor module further includes a first metal pin including a first source pin and a first gate pin;

the first metal signal region comprises a first source electrode control region, a second source electrode control region and a first conductive block; the first source electrode control region is arranged on the first substrate, the second source electrode control region is arranged on the second substrate, and two ends of the first conductive block are respectively connected with the first source electrode control region and the second source electrode control region;

one end of the first source pin is connected with the first source control region, and the other end of the first source pin extends out of a space between the first substrate and the second substrate; the Kelvin source region of the first bridge arm chip is connected with the second source control region;

the second metal signal area is arranged on the second substrate, one end of the first gate pin is connected with the second metal signal area, and the other end of the first gate pin extends out of a space between the first substrate and the second substrate.

10. The power semiconductor module of claim 9, further comprising a second metal pin, the second metal pin comprising a second source pin and a second gate pin;

the third metal signal region comprises a third source electrode control region, a fourth source electrode control region and a second conductive block; the third source electrode control region is arranged on the first substrate, the fourth source electrode control region is arranged on the second substrate, and two ends of the second conductive block are respectively connected with the third source electrode control region and the fourth source electrode control region;

one end of the second source pin is connected with the third source control region, and the other end of the second source pin extends out of the space between the first substrate and the second substrate; the Kelvin source region of the second bridge arm chip is connected with the fourth source control region;

the fourth metal signal area is arranged on the second substrate, one end of the second grid electrode pin is connected with the fourth metal signal area, and the other end of the second grid electrode pin extends out of a space between the first substrate and the second substrate.

11. A vehicle comprising a power semiconductor module according to any one of claims 1-10.