CN220381585U - Adapter plate and main board - Google Patents
Adapter plate and main board Download PDFInfo
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- CN220381585U CN220381585U CN202321713961.8U CN202321713961U CN220381585U CN 220381585 U CN220381585 U CN 220381585U CN 202321713961 U CN202321713961 U CN 202321713961U CN 220381585 U CN220381585 U CN 220381585U
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
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- 238000012360 testing method Methods 0.000 abstract description 28
- 238000010586 diagram Methods 0.000 description 7
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- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 230000008054 signal transmission Effects 0.000 description 4
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- 238000006467 substitution reaction Methods 0.000 description 2
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Abstract
The application discloses an adapter plate and a main board, wherein the adapter plate comprises a printed circuit board, a clock buffer chip, a signal conversion chip, an input end and an output port, the clock buffer chip is arranged on the printed circuit board and is electrically connected with the printed circuit board, the output port is arranged on the side edge of the printed circuit board, the signal conversion chip is arranged between the clock buffer chip and the output port, one side of the signal conversion chip is connected with the clock buffer chip through a signal wire, the other side of the signal conversion chip is electrically connected with the output port through a signal wire, and the output port is a USB 3.2Gen2X2 port; the input end is arranged on the side of the printed circuit board and is different from the output end; the clock buffer chip is used for shunting the input signal to the signal conversion chip, and the signal conversion chip is used for converting the input signal into a USB 3.2Gen2X2 port signal. Through above mode, increase mainboard USB 3.2Gen2X2 port quantity, improve test efficiency, practice thrift the test cost.
Description
Technical Field
The present disclosure relates to the field of chips, and in particular, to an interposer and a motherboard.
Background
Because the USB 3.2Gen2X2 has high read-write bandwidth requirement, the theoretical bandwidth needs 20Gbps, and the performance requirement on the main board is high, so that the number of USB 3.2Gen2X2 ports on the main board is small, only one port exists, and even no port exists on the main board, so that the test cost on the USB 3.2Gen2X2 product is high.
How to increase the number of USB 3.2Gen2X2 ports of a main board, improve the testing efficiency, save the testing cost and become a problem to be solved in the field.
Disclosure of Invention
The application discloses keysets and mainboard, purpose increase mainboard USB 3.2Gen2X2 port quantity, improve test efficiency, practice thrift the test cost.
The application discloses an adapter plate, which comprises a printed circuit board, a clock buffer chip, a signal conversion chip, an input end and an output port, wherein the clock buffer chip is arranged on the printed circuit board and is electrically connected with the printed circuit board, the output port is arranged on the side edge of the printed circuit board, the signal conversion chip is arranged between the clock buffer chip and the output port, one side of the signal conversion chip is connected with the clock buffer chip through a signal wire, the other side of the signal conversion chip is electrically connected with the output port through a signal wire, and the output port is a USB 3.2Gen2X2 port; the input end is arranged on the side edge of the printed circuit board and is different from the output port; the clock buffer chip is used for shunting an input signal to the signal conversion chip, and the signal conversion chip is used for converting the input signal into a USB 3.2Gen2X2 port signal.
Optionally, the input end is a pcie x16 golden finger.
Optionally, the signal conversion chip has a plurality of, the output port has a plurality of, every the signal conversion chip respectively with every the output port is connected, a plurality of the output port interval sets up the at least one side of printed circuit board.
Optionally, the number of the signal conversion chips is four, the number of the output ports is four, and the four output ports are arranged on one side edge of the printed circuit board adjacent to the input end at intervals; each signal conversion chip is connected with each output port to form four signal channels.
Optionally, the printed circuit board includes a first side and a second side, the first side and the second side are disposed opposite to each other, the output port includes a first output port and a second output port, the first output port is disposed on the first side, and the second output port is disposed on the second side.
Optionally, the output port further includes a third output port, and the third output port is disposed on a side of the printed circuit board opposite to the input port.
Optionally, the number of the signal conversion chips is four, the number of the output ports is four, and the four output ports are arranged on the side edge of the printed circuit board opposite to the input end at intervals; each signal conversion chip is connected with each output port to form four signal channels.
Optionally, a space between the clock buffer chip and the signal conversion chip is 3 to 5 times as large as a width of the signal line.
The application discloses mainboard for with foretell keysets connects, be provided with the slot on the mainboard, the slot with the input of keysets is connected.
Optionally, the slot is a PCIE GEN 3x16 slot or a PCIE GEN 4x16 slot, and the input end and the slot have the same specification.
According to the method, the adapter plate is additionally designed on the main board, the clock buffer chip on the adapter plate is utilized to shunt the input signals to the signal conversion chip, the input signals are converted into USB 3.2Gen2X2 port signals through the signal conversion chip, the USB 3.2Gen2X2 port on the adapter plate is used for outputting, so that the number of USB 3.2Gen2X2 ports of the main board can be increased through the adapter plate, the testing efficiency is improved, and the testing cost is saved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the present application, from which other drawings can be obtained without inventive effort for a person skilled in the art, in which:
FIG. 1 is a schematic view of a first embodiment of an interposer of the present application;
FIG. 2 is a schematic view of a second embodiment of an adapter plate of the present application;
FIG. 3 is a schematic view of a third embodiment of an adapter plate of the present application;
FIG. 4 is a schematic view of a fourth embodiment of an adapter plate of the present application;
FIG. 5 is a schematic view of a fifth embodiment of an adapter plate of the present application;
fig. 6 is a schematic diagram of an embodiment of a motherboard of the present application.
10, a main board; 100. an adapter plate; 200. a slot; 110. a printed circuit board; 111. a first side; 112. a second side; 120. a clock buffer chip; 130. a signal conversion chip; 140. an input end; 141. a golden finger; 150. an output port; 151. a first output port; 152. a second output port; 153. a third output port; 160. and a signal line.
Detailed Description
The present application will be described in detail below with reference to the drawings and optional embodiments, and it should be noted that, without conflict, new embodiments may be formed by any combination of the embodiments or technical features described below.
Fig. 1 is a schematic diagram of a first embodiment of an interposer of the present application, as shown in fig. 1, the present application discloses an interposer 100, which includes a printed circuit board 110, a clock buffer chip 120, a signal conversion chip 130, an input end 140, and an output port 150, wherein the clock buffer chip 120 is disposed on the printed circuit board 110 and is electrically connected to the printed circuit board 110, the output port 150 is disposed at a side of the printed circuit board 110, the signal conversion chip 130 is disposed between the clock buffer chip 120 and the output port 150, one side of the signal conversion chip 130 is connected to the clock buffer chip 120 through a signal line 160, the other side is electrically connected to the output port 150 through the signal line 160, and the output port 150 is a USB 3.2gen2x2 port; the input end 140 is disposed on a side of the printed circuit board 110 and is different from the output port 150; the clock buffer chip 120 is used for shunting the input signal to the signal conversion chip 130, and the signal conversion chip 130 is used for converting the input signal into a USB 3.2gen2x2 port signal.
According to the method, the adapter plate 100 is additionally designed on the main board 10, the clock buffer chip 120 on the adapter plate 100 is utilized to shunt an input signal to the signal conversion chip 130, the signal conversion chip 130 is used for converting the input signal into a USB 3.2Gen2X2 port signal, and the USB 3.2Gen2X2 port on the adapter plate 100 is used for outputting, so that the number of the 10USB 3.2Gen2X2 ports of the main board can be increased through the adapter plate 100, the testing efficiency is improved, and the testing cost is saved.
Specifically, the input end 140 is a pcie x16 golden finger 141. That is, when the patch panel 100 receives an input signal as a PCIE signal and the patch panel 100 is mounted on the motherboard 10, only the golden finger 141 of the patch panel 100 needs to be inserted into the slot 200 of the motherboard 10, and the patch panel 100 is used to convert the PCIE signal into a USB signal for output, thereby increasing the number of ports of the USB 3.2gen2x2, being beneficial to improving the testing efficiency and saving the testing cost.
Further, the interval between the clock buffer chip 120 and the signal conversion chip 130 is 3 to 5 times the width of the signal line 160.
When the interval between the clock buffer chip 120 and the signal conversion chip 130 is less than 3 times of the width of the signal line 160, signal interference is easily generated between the clock buffer chip 120 and the signal conversion chip 130, and when the interval between the clock buffer chip 120 and the signal conversion chip 130 is less than 5 times of the width of the signal line 160, the path of signal transmission is long, and signal loss easily occurs; therefore, when the interval between the clock buffer chip 120 and the signal conversion chip 130 is set to be between 3 and 5 times the width of the signal line 160, specifically, 4 times the width of the signal line 160, interference in the signal transmission or signal conversion process can be effectively avoided, and the path of signal propagation can be effectively controlled, so that signal loss in the signal propagation process is reduced.
Fig. 2 is a schematic diagram of a second embodiment of an interposer according to the present application, as shown in fig. 2, where the embodiment shown in fig. 2 is based on the modification of fig. 1, and there are a plurality of signal conversion chips 130, a plurality of output ports 150, each signal conversion chip 130 is connected to each output port 150, and a plurality of output ports 150 are disposed at intervals on at least one side of the printed circuit board 110.
In this embodiment, since the adapter board 100 has the plurality of output ports 150, after the adapter board 100 is connected with the motherboard 10, signals on the motherboard 10 can be converted into a plurality of USB 3.2gen2x2 port signals for outputting, so that the number of USB 3.2gen2x2 ports on the motherboard 10 is further increased, which is beneficial to testing a plurality of products simultaneously, further improves testing efficiency, and saves testing cost.
Specifically, the number of the signal conversion chips 130 is four, the number of the output ports 150 is four, and the four output ports 150 are arranged on one side edge of the printed circuit board 110 adjacent to the input end 140 at intervals; each signal conversion chip 130 is connected to each output port 150 to form four signal channels.
The clock buffer chip 120 and the 4 signal conversion chips 130 are used to convert signals such as PCIE3.0 or PCIE4.0 into USB signals required by the USB 3.2gen2x2 interface, where one adapter board 100 can support up to 4 ports of USB 3.2gen2x2 (and the bandwidth satisfies the maximum bandwidth of 20Gbps of USB 3.2gen2x2), so that the number of ports of USB 3.2gen2x2 is increased, the test efficiency is improved, and the test cost is saved.
Fig. 3 is a schematic diagram of a third embodiment of the interposer of the present application, as shown in fig. 3, where the embodiment shown in fig. 3 is based on the modification of fig. 2, the printed circuit board 110 includes a first side 111 and a second side 112, the first side 111 and the second side 112 are opposite, the output port 150 includes a first output port 151 and a second output port 152, the first output port 151 is disposed on the first side 111, and the second output port 152 is disposed on the second side 112.
In this embodiment, the positions of the output ports 150 are designed, and the first output port 151 and the second output port 152 are respectively disposed on two adjacent sides of the input port 140, so that not only can products be tested in two different directions on the adapter plate 100, and mutual interference between a plurality of products is avoided, but also the relative distance between the output port 150 and the input port 140 can be relatively short, the propagation path of signals can be effectively shortened, the signals transmitted from the input port 140 can reach the output port 150 relatively fast, the signal transmission rate can be improved to a certain extent, and the interference suffered by the signals can be reduced.
Fig. 4 is a schematic diagram of a fourth embodiment of the interposer of the present application, as shown in fig. 4, where the embodiment shown in fig. 4 is based on the modification of fig. 3, and the output port 150 further includes a third output port 153, where the third output port 153 is disposed on a side of the printed circuit board 110 opposite to the input port 140.
Unlike the previous embodiment, in this embodiment, the third output port 153 is further disposed on the side opposite to the input end 140 on the printed circuit board 110, that is, the output ports 150 are disposed on the sides of the printed circuit board 110 except the sides where the output ends are located, so that the three sides of the printed circuit board 110 can test the products through the output ports 150, and when testing the products, the products can be tested from different directions of the adapter board 100 according to actual requirements, so as to avoid mutual interference between the products to be tested.
Fig. 5 is a schematic diagram of a fifth embodiment of the interposer of the present application, as shown in fig. 5, where the embodiment shown in fig. 5 is based on the modification of fig. 2, and there are four signal conversion chips 130, four output ports 150, and four output ports 150 are disposed on the opposite side of the printed circuit board 110 from the input port 140 at intervals; each signal conversion chip 130 is connected to each output port 150 to form four signal channels.
In this embodiment, the positions of the output ports 150 are designed, and the four output ports 150 are all disposed on the side of the printed circuit board 110 opposite to the input end 140, and are respectively connected with each output port 150 through the four signal conversion chips 130 to form four signal channels, so that four products can be tested at the same time, and the testing efficiency is improved.
In addition, because the input end 140 of the adapter plate 100 is inserted into the main board 10 and the four output ports 150 are disposed at positions far from the input end 140 in the use process of the adapter plate 100, the connection between the test product and the output ports 150 can be more convenient.
Fig. 6 is a schematic diagram of an embodiment of a motherboard of the present application, as shown in fig. 6, and the present application discloses a motherboard 10, which is used for being connected to the above-mentioned interposer 100, a socket 200 is disposed on the motherboard 10, and the socket 200 is connected to the input end 140 of the interposer 100.
The motherboard 10 of the present application may be a computer motherboard 10, a notebook motherboard 10, or other types of motherboards 10, and the present application does not specifically limit the types of the motherboard 10, but only illustrates the computer motherboard 10.
Because of the large number of conventional ports in the current computer motherboard 10, the large number of ports of the USB 3.2gen2x2 with high transmission rate is small, and some of the computer motherboards 10 even do not have the port, so that the test rate of the USB 3.2gen2x2 product is low and the test cost is high.
In order to solve the above problems, the present application additionally adds the adapter board 100 on the motherboard 10, and uses the clock buffer chip 120 on the adapter board 100 to shunt the input signal to the signal conversion chip 130, and converts the input signal into the USB 3.2gen2x2 port signal through the signal conversion chip 130, and then outputs the signal through the USB 3.2gen2x2 port on the adapter board 100, so that the number of the USB 3.2gen2x2 ports of the motherboard 10 can be increased through the adapter board 100, thereby improving the test efficiency and saving the test cost.
Specifically, the slot 200 is a PCIE GEN 3x16 slot 200 or a PCIE GEN 4x16 slot 200, and the input end 140 has the same specification as the slot 200. This ensures the stability of signal transmission of the interposer 100 after insertion into the socket 200 of the motherboard 10.
When the slot 200 on the motherboard 10 is the PCIE GEN 3x16 slot 200 or the PCIE GEN 4x16 slot 200, the golden finger 141 of the adapter board 100 is inserted into the slot 200 corresponding to the motherboard 10 to convert the PCIE signal into the USB signal for outputting, thereby increasing the number of ports of the USB 3.2gen2x2, being beneficial to improving the test efficiency and saving the test cost.
It should be noted that, the inventive concept of the present application may form a very large number of embodiments, but the application documents have limited space and cannot be listed one by one, so that on the premise of no conflict, the above-described embodiments or technical features may be arbitrarily combined to form new embodiments, and after the embodiments or technical features are combined, the original technical effects will be enhanced.
The foregoing is a further detailed description of the present application in connection with specific alternative embodiments, and it is not intended that the practice of the present application be limited to such descriptions. It should be understood that those skilled in the art to which the present application pertains may make several simple deductions or substitutions without departing from the spirit of the present application, and all such deductions or substitutions should be considered to be within the scope of the present application.
Claims (10)
1. An adapter board is characterized by comprising a printed circuit board, a clock buffer chip, a signal conversion chip, an input end and an output port,
the clock buffer chip is arranged on the printed circuit board and is electrically connected with the printed circuit board, the output port is arranged on the side edge of the printed circuit board, the signal conversion chip is arranged between the clock buffer chip and the output port, one side of the signal conversion chip is connected with the clock buffer chip through a signal line, the other side of the signal conversion chip is electrically connected with the output port through a signal line, and the output port is a USB 3.2Gen2X2 port;
the input end is arranged on the side edge of the printed circuit board and is different from the output port;
the clock buffer chip is used for shunting an input signal to the signal conversion chip, and the signal conversion chip is used for converting the input signal into a USB 3.2Gen2X2 port signal.
2. The interposer of claim 1, wherein the input is a pci ex16 gold finger.
3. The interposer of claim 1, wherein said plurality of signal conversion chips, said plurality of output ports, each of said signal conversion chips being respectively connected to each of said output ports, said plurality of output ports being spaced apart from at least one side of said printed circuit board.
4. The interposer of claim 3, wherein said signal conversion chip has four said output ports, four said output ports being spaced apart on said printed circuit board on a side adjacent said input port;
each signal conversion chip is connected with each output port to form four signal channels.
5. The interposer of claim 3, wherein said printed circuit board comprises a first side and a second side, said first side and said second side being disposed opposite, said output port comprising a first output port and a second output port, said first output port being disposed on said first side and said second output port being disposed on said second side.
6. The interposer of claim 5, wherein said output port further comprises a third output port disposed on a side of said printed circuit board opposite said input port.
7. The interposer of claim 3, wherein said signal conversion chip has four said output ports, four said output ports being spaced on opposite sides of said printed circuit board from said input ports;
each signal conversion chip is connected with each output port to form four signal channels.
8. The interposer of claim 1, wherein a spacing between the clock buffer chip and the signal conversion chip is 3 to 5 times a width of the signal line.
9. A motherboard for connection to the patch panel of any one of claims 1 to 8, wherein a slot is provided on the motherboard, the slot being connected to an input of the patch panel.
10. The motherboard of claim 9 wherein the slot is a PCIE GEN 3x16 slot or a PCIE GEN 4x16 slot, and the input terminal is the same as the slot in specification.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321713961.8U CN220381585U (en) | 2023-06-30 | 2023-06-30 | Adapter plate and main board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321713961.8U CN220381585U (en) | 2023-06-30 | 2023-06-30 | Adapter plate and main board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN220381585U true CN220381585U (en) | 2024-01-23 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202321713961.8U Active CN220381585U (en) | 2023-06-30 | 2023-06-30 | Adapter plate and main board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN220381585U (en) |
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2023
- 2023-06-30 CN CN202321713961.8U patent/CN220381585U/en active Active
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Address after: 518000 floor 1, floor 2 and floor 3, No. 7, Xinfa East Road, Xiangshan community, Xinqiao street, Bao'an District, Shenzhen, Guangdong Province; No.5 1st, 2nd and 3rd floors Patentee after: Shenzhen Shi Creative Electronics Co.,Ltd. Country or region after: China Address before: Shenzhen Shishi Creative Electronics Co., Ltd., No. 5, Xinfa East Road, Xinqiao Street, Bao'an District, Shenzhen City, Guangdong Province, 518000 Patentee before: SHENZHEN SHICHUANGYI ELECTRONIC CO.,LTD. Country or region before: China |