CN220367346U - Positive and negative voltage detection circuit realized by single-ended AD - Google Patents
Positive and negative voltage detection circuit realized by single-ended AD Download PDFInfo
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- CN220367346U CN220367346U CN202321254769.7U CN202321254769U CN220367346U CN 220367346 U CN220367346 U CN 220367346U CN 202321254769 U CN202321254769 U CN 202321254769U CN 220367346 U CN220367346 U CN 220367346U
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Abstract
The utility model discloses a single-ended AD (analog-to-digital) realization positive and negative voltage detection circuit which comprises a first filter circuit, a forward amplification circuit, a second filter circuit, a reverse amplification circuit and a third filter circuit, wherein the first filter circuit is electrically connected with the forward amplification circuit and the reverse amplification circuit, the forward amplification circuit is electrically connected with the second filter circuit, and the reverse amplification circuit is electrically connected with the third filter circuit; compared with the existing positive and negative voltage detection circuit, the utility model adopts single-ended AD input, utilizes the dual-power operational amplifier to realize the positive amplification and the negative amplification to obtain the positive and negative voltage ADC acquisition, subtracts the voltage lifting circuit before the existing negative voltage ADC acquisition, and the amplification times of the positive and negative voltage acquisition can be different.
Description
Technical Field
The utility model relates to the technical field of detection circuits, in particular to a single-ended AD (analog-to-digital) realization positive and negative voltage detection circuit.
Background
Voltage refers to the work done by the force of an electric field on the movement of a unit positive charge in the electric field from one point to another, and voltage measurement is an important content of electronic circuit measurement and is the basis of many electrical parameter measurements. The existing storage battery charging and discharging detection circuit generally adopts a positive voltage detection circuit and a negative voltage detection circuit, wherein the positive voltage ADC acquisition is obtained by directly inputting a positive voltage and then passing through a forward amplification circuit, and the negative voltage ADC acquisition is obtained by further passing through a voltage lifting and then passing through the forward amplification circuit. Therefore, the ADC of the voltage collects one more voltage lifting circuit, and the amplification factors of the forward amplifying circuits before positive and negative voltage collection are required to be the same.
Disclosure of Invention
The utility model aims to provide a single-ended AD (analog-to-digital) implementation positive and negative voltage detection circuit so as to solve the problems in the background technology.
In order to solve the technical problems, the utility model provides the following technical scheme: the utility model provides a positive and negative voltage detection circuit is realized to single-ended AD, includes first filter circuit, forward amplification circuit, second filter circuit, reverse amplification circuit and third filter circuit, first filter circuit electric connection has forward amplification circuit and reverse amplification circuit, and forward amplification circuit electric connection has the second filter circuit, and reverse amplification circuit electric connection has the third filter circuit.
Preferably, the first filter circuit includes a magnetic bead ACZ3, a capacitor IC1, a capacitor IC2, a capacitor IC3, a capacitor IC5, a resistor IR1, a resistor IR2, a resistor IR3, and a resistor IR4, one end of the magnetic bead ACZ3 is connected to the voltage input, the other end is connected in parallel with the capacitor IC1, the capacitor IC2, the resistor IR1, and the resistor IR3, and the other ends of the capacitor IC1 and the capacitor IC2 are connected in parallel with the other ends of the resistor IR1 and the capacitor IC3, and the other ends of the resistor IR2 are connected with the forward amplification circuit, the other ends of the capacitor IC3 are connected in parallel with the resistor IR4 and the capacitor IC5, and the other ends of the resistor IR4 are connected with the reverse amplification circuit, and the other ends of the capacitor IC5 are connected with the AGND.
Preferably, the forward amplifying circuit includes an operational amplifier IU1B, a resistor IR5 and a resistor IR7, wherein the other end of the resistor IR2 is connected to a pin 5 of the operational amplifier IU1B, a pin 6 of the operational amplifier IU1B is connected in parallel with the resistor IR5 and the resistor IR7, the other end of the resistor IR5 is connected to AGND, the other end of the resistor IR7 is connected to a pin 7 of the operational amplifier IU1B, and the pin 7 of the operational amplifier IU1B is connected to the second filter circuit.
Preferably, the second filter circuit includes a resistor IR10 and a capacitor IC4, one end of the resistor IR10 is connected in parallel with a resistor IR9 and a diode ID1, the other end of the resistor IR9 is connected with a pin 7 of the operational amplifier IU1B, the input end of the diode ID1 is connected with AGND, the other end of the resistor IR10 is connected in parallel with the capacitors IC4 and AD in, and the other end of the capacitor IC4 is connected with the input end of the diode ID 1.
Preferably, the inverting amplification circuit includes an operational amplifier IU1A, a resistor IR8 and a resistor IR6, wherein the other end of the resistor IR4 is connected with a pin 2 of the operational amplifier IU1A, the pin 2 and the pin 1 of the operational amplifier IU1A are connected in series through the resistor IR8, the pin 1 of the operational amplifier IU1A is connected with a third filter circuit, the pin 3 is connected with an AGND after being connected with the resistor IR6 in series, the pin 4 is connected with V5.0 and a capacitor IC7 in parallel, the other end of the capacitor IC7 is connected with AGND, the pin 11 is connected with-V5.0 and the capacitor IC6 in parallel, and the other end of the capacitor IC6 is connected with AGND.
Preferably, the third filter circuit includes a resistor IR12 and a capacitor IC8, one end of the resistor IR12 is connected in parallel with a resistor IR11 and a diode ID2, the other end of the resistor IR11 is connected with the pin 1 of the operational amplifier IU1A, the input end of the diode ID2 is connected with AGND, the other end of the resistor IR12 is connected in parallel with the capacitors IC8 and AD out, and the other end of the capacitor IC8 is connected with the input end of the diode ID 2.
The utility model provides a single-ended AD realization positive and negative voltage detection circuit, which has the advantages that: compared with the existing positive and negative voltage detection circuit, the utility model adopts single-ended AD input, utilizes the dual-power operational amplifier to realize the positive amplification and the negative amplification to obtain the positive and negative voltage ADC acquisition, subtracts the voltage lifting circuit before the existing negative voltage ADC acquisition, and the amplification times of the positive and negative voltage acquisition can be different.
Drawings
In order to more clearly illustrate the embodiments of the present utility model or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are some embodiments of the present utility model, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a circuit diagram of the present utility model;
in the figure: 1. a first filter circuit; 2. a forward amplifying circuit; 3. a second filter circuit; 4. an inverting amplification circuit; 5. and a third filter circuit.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present utility model more apparent, the technical solutions of the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model, and it is apparent that the described embodiments are some embodiments of the present utility model, but not all embodiments of the present utility model. All other embodiments, which can be made by one of ordinary skill in the art without inventive faculty, are intended to be within the scope of the present utility model, based on the embodiments of the present utility model.
Referring to fig. 1, an embodiment of the present utility model is provided: the utility model provides a positive and negative voltage detection circuit is realized to single-ended AD, includes first filter circuit 1, forward amplification circuit 2, second filter circuit 3, reverse amplification circuit 4 and third filter circuit 5, and first filter circuit 1 electric connection has forward amplification circuit 2 and reverse amplification circuit 4, and forward amplification circuit 2 electric connection has second filter circuit 3, and reverse amplification circuit 4 electric connection has third filter circuit 5; the first filter circuit 1 comprises a magnetic bead ACZ3, a capacitor IC1, a capacitor IC2, a capacitor IC3, a capacitor IC5, a resistor IR1, a resistor IR2, a resistor IR3 and a resistor IR4, wherein one end of the magnetic bead ACZ3 is connected with a voltage input, the other end of the magnetic bead ACZ is connected with the capacitor IC1, the capacitor IC2, the resistor IR1 and the resistor IR3 in parallel, the other ends of the capacitor IC1 and the capacitor IC2 are connected with the resistor IR2 and the capacitor IC3 in parallel, the other ends of the resistor IR2 are connected with a forward amplification circuit 2, the other ends of the capacitor IC3 are connected with the resistor IR4 and the capacitor IC5 in parallel, the other ends of the resistor IR4 are connected with a reverse amplification circuit 4, and the other ends of the capacitor IC5 are connected with the AGND; the forward amplifying circuit 2 comprises an operational amplifier IU1B, a resistor IR5 and a resistor IR7, wherein the other end of the resistor IR2 is connected with a pin 5 of the operational amplifier IU1B, a pin 6 of the operational amplifier IU1B is connected with the resistor IR5 and the resistor IR7 in parallel, the other end of the resistor IR5 is connected with an AGND, the other end of the resistor IR7 is connected with a pin 7 of the operational amplifier IU1B, and the pin 7 of the operational amplifier IU1B is connected with the second filter circuit 3; the second filter circuit 3 comprises a resistor IR10 and a capacitor IC4, wherein one end of the resistor IR10 is connected with a resistor IR9 and a diode ID1 in parallel, the other end of the resistor IR9 is connected with a pin 7 of an operational amplifier IU1B, the input end of the diode ID1 is connected with AGND, the other end of the resistor IR10 is connected with the capacitors IC4 and AD in parallel, and the other end of the capacitor IC4 is connected with the input end of the diode ID 1; the inverting amplifier circuit 4 comprises an operational amplifier IU1A, a resistor IR8 and a resistor IR6, wherein the other end of the resistor IR4 is connected with a pin 2 of the operational amplifier IU1A, the pin 2 and the pin 1 of the operational amplifier IU1A are connected in series through the resistor IR8, the pin 1 of the operational amplifier IU1A is connected with a third filter circuit 5, the pin 3 is connected with an resistor IR6 in series and then is connected with an AGND, the pin 4 is connected with a V5.0 and a capacitor IC7 in parallel, the other end of the capacitor IC7 is connected with an AGND, the pin 11 is connected with a V5.0 and the capacitor IC6 in parallel, and the other end of the capacitor IC6 is connected with the AGND; the third filter circuit 5 comprises a resistor IR12 and a capacitor IC8, wherein one end of the resistor IR12 is connected with a resistor IR11 and a diode ID2 in parallel, the other end of the resistor IR11 is connected with the pin 1 of the operational amplifier IU1A, the input end of the diode ID2 is connected with AGND, the other end of the resistor IR12 is connected with the capacitors IC8 and AD out in parallel, and the other end of the capacitor IC8 is connected with the input end of the diode ID 2.
Working principle: after the shunt is connected into the circuit, when the measured voltage is positive voltage, the measured voltage enters the forward amplification circuit 2 after passing through an RC filter circuit formed by a magnetic bead ACZ3, a capacitor IC1, a capacitor IC3, a resistor IR1 and a resistor IR2 in the first filter circuit 1, reasonable amplification factors are set, data conversion is realized, after passing through a second filter circuit 3 formed by a resistor IR10 and a capacitor IC4, the data is connected into an ADC (analog to digital converter) for data acquisition, and a diode ID1 is used for clamping and protecting the amplified data; when the measured voltage is negative voltage, the measured voltage enters an inverse amplifying circuit 4 after passing through an RC filter circuit consisting of a magnetic bead ACZ3, a capacitor IC2, a capacitor IC5, a resistor IR3 and a resistor IR4 in a first filter circuit 1, reasonable amplification factors are set, data conversion is realized, and after passing through a third filter circuit 5 consisting of a resistor IR12 and a capacitor IC8, the data is accessed into an ADC for data acquisition, and a diode ID2 is used for clamping and protecting the amplified data; when the measured voltage is positive, the value obtained at the AD out position is negative, the ADC can not collect data at the moment, when the measured voltage is negative, the value obtained at the AD in position is negative, the ADC can not collect data at the moment, and compared with the traditional circuit, the circuit can realize the detection of positive and negative voltages only by connecting the AD with a single end, and the whole circuit is simple and reliable, high in accuracy and strong in practicability.
In the description of the present utility model, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present utility model will be understood in specific cases by those of ordinary skill in the art.
The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present utility model without undue burden.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present utility model, and are not limiting; although the utility model has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present utility model.
Claims (6)
1. The utility model provides a positive negative voltage detection circuit is realized to single-ended AD, includes first filter circuit (1), forward amplification circuit (2), second filter circuit (3), reverse amplification circuit (4) and third filter circuit (5), its characterized in that: the first filter circuit (1) is electrically connected with a forward amplification circuit (2) and a reverse amplification circuit (4), the forward amplification circuit (2) is electrically connected with a second filter circuit (3), and the reverse amplification circuit (4) is electrically connected with a third filter circuit (5).
2. The single-ended AD implemented positive and negative voltage detection circuit of claim 1, wherein: the first filter circuit (1) comprises a magnetic bead ACZ3, a capacitor IC1, a capacitor IC2, a capacitor IC3, a capacitor IC5, a resistor IR1, a resistor IR2, a resistor IR3 and a resistor IR4, one end of the magnetic bead ACZ3 is connected with voltage input, the other end of the magnetic bead ACZ is connected with the capacitor IC1, the capacitor IC2, the resistor IR1 and the resistor IR3 in parallel, the other ends of the capacitor IC1 and the capacitor IC2 are connected with the resistor IR2 and the capacitor IC3 in parallel, the other ends of the resistor IR2 are connected with the forward amplifying circuit (2), the other ends of the capacitor IC3 are connected with the resistor IR4 and the capacitor IC5 in parallel, the other ends of the resistor IR4 are connected with the reverse amplifying circuit (4), and the other ends of the capacitor IC5 are connected with the AGND in parallel.
3. The single-ended AD implemented positive and negative voltage detection circuit of claim 2, wherein: the forward amplifying circuit (2) comprises an operational amplifier IU1B, a resistor IR5 and a resistor IR7, wherein the other end of the resistor IR2 is connected with a pin 5 of the operational amplifier IU1B, a pin 6 of the operational amplifier IU1B is connected with the resistor IR5 and the resistor IR7 in parallel, the other end of the resistor IR5 is connected with an AGND, the other end of the resistor IR7 is connected with a pin 7 of the operational amplifier IU1B, and the pin 7 of the operational amplifier IU1B is connected with the second filter circuit (3).
4. A single-ended AD implemented positive and negative voltage detection circuit according to claim 3, characterized in that: the second filter circuit (3) comprises a resistor IR10 and a capacitor IC4, wherein one end of the resistor IR10 is connected with a resistor IR9 and a diode ID1 in parallel, the other end of the resistor IR9 is connected with a pin 7 of an operational amplifier IU1B, the input end of the diode ID1 is connected with AGND, the other end of the resistor IR10 is connected with the capacitors IC4 and AD in parallel, and the other end of the capacitor IC4 is connected with the input end of the diode ID 1.
5. The single-ended AD implemented positive and negative voltage detection circuit of claim 2, wherein: the reverse amplifying circuit (4) comprises an operational amplifier IU1A, a resistor IR8 and a resistor IR6, the other end of the resistor IR4 is connected with a pin 2 of the operational amplifier IU1A, the pin 2 and the pin 1 of the operational amplifier IU1A are connected in series through the resistor IR8, the pin 1 of the operational amplifier IU1A is connected with a third filter circuit (5), the pin 3 is connected with an AGND after being connected with the resistor IR6 in series, the pin 4 is connected with V5.0 and a capacitor IC7 in parallel, the other end of the capacitor IC7 is connected with the AGND, the pin 11 is connected with the capacitor IC6 in parallel, and the other end of the capacitor IC6 is connected with the AGND.
6. The single-ended AD implemented positive and negative voltage detection circuit of claim 5, wherein: the third filter circuit (5) comprises a resistor IR12 and a capacitor IC8, wherein one end of the resistor IR12 is connected with a resistor IR11 and a diode ID2 in parallel, the other end of the resistor IR11 is connected with a pin 1 of the operational amplifier IU1A, the input end of the diode ID2 is connected with AGND, the other end of the resistor IR12 is connected with the capacitors IC8 and AD out in parallel, and the other end of the capacitor IC8 is connected with the input end of the diode ID 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321254769.7U CN220367346U (en) | 2023-05-23 | 2023-05-23 | Positive and negative voltage detection circuit realized by single-ended AD |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321254769.7U CN220367346U (en) | 2023-05-23 | 2023-05-23 | Positive and negative voltage detection circuit realized by single-ended AD |
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| Publication Number | Publication Date |
|---|---|
| CN220367346U true CN220367346U (en) | 2024-01-19 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202321254769.7U Active CN220367346U (en) | 2023-05-23 | 2023-05-23 | Positive and negative voltage detection circuit realized by single-ended AD |
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| Country | Link |
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| CN (1) | CN220367346U (en) |
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- 2023-05-23 CN CN202321254769.7U patent/CN220367346U/en active Active
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