CN220357459U

CN220357459U - Data acquisition system and control device for pipeline detection

Info

Publication number: CN220357459U
Application number: CN202322320640.8U
Authority: CN
Inventors: 刘彦龙
Original assignee: Yijia Intelligent Hebei Technology Co ltd
Current assignee: Liu Yanlong
Priority date: 2023-08-28
Filing date: 2023-08-28
Publication date: 2024-01-16
Anticipated expiration: 2033-08-28

Abstract

The utility model provides a data acquisition system, a method and a control device for pipeline detection, wherein the system comprises: the system comprises a digital channel acquisition board card, an analog channel acquisition board card and a control device, wherein the control device receives acquired digital signal data related to pipeline change through the digital channel acquisition board card, receives acquired analog signal data related to pipeline change through the analog channel acquisition board card, and receives acquired mileage data, and the control device stores and processes the acquired digital signal data, analog signal data and mileage data. According to the scheme of the utility model, the absolute synchronous acquisition of the same kind of data and the relative synchronous acquisition of different types of data can be realized, and the synchronous stability under the abnormal conditions of electromagnetic interference and the like is solved, so that the data analysis is more accurate.

Description

Data acquisition system and control device for pipeline detection

Technical Field

The utility model relates to the field of multichannel high-speed data acquisition, in particular to a data acquisition system and a control device for pipeline detection.

Background

The pipeline nondestructive detection technology is used for detecting potential safety hazards such as corrosion, abrasion, perforation, crack and the like of long-distance oil and gas conveying pipelines in the petroleum and natural gas industry. The main detection device at present is magnetic leakage detection equipment, and the equipment mainly comprises a detection sensor probe, a support arm, a junction box, a compression-resistant bin, an electronic package system, a safety battery, a power leather cup, a support leather cup, an anti-collision wheel and the like. The sensor probe and the electronic acquisition system are the cores of the ultra-high-definition acquisition device, the acquisition system on the market at present mainly comprises a single chip microcomputer, a single chip microcomputer and FPGA combination, a DSP and an FPGA combination, the acquisition architecture has no operating system, the development efficiency is low, the data processing operation efficiency is low, the requirements of ultra-high-definition multi-channel high-speed data acquisition and storage are difficult to be met, the splicing system is complex, the stability is poor, and the problems of data loss, incomplete data acquisition, asynchronous data and the like are easy to occur.

Accordingly, there is a need in the art for a scheme that enables high-speed multi-channel acquisition of data within a pipeline.

The above information disclosed in the background section is only for a further understanding of the background of the utility model and therefore it may contain information that does not form the prior art that is already known to a person of ordinary skill in the art.

Disclosure of Invention

The utility model provides a data acquisition system, a method and a control device for pipeline detection. The scheme of the utility model can solve the technical problems that the existing acquisition architecture has no operating system, low development efficiency, low data processing operation efficiency, difficulty in meeting the requirements of ultrahigh-definition multi-channel high-speed data acquisition and storage, complex splicing system, poor stability, easiness in data loss, incomplete data acquisition, asynchronous data and the like.

The first aspect of the utility model provides a digital channel acquisition board, an analog channel acquisition board and a control device, wherein the control device receives acquired digital signal data related to pipeline change through the digital channel acquisition board, receives acquired analog signal data related to pipeline change through the analog channel acquisition board, receives acquired mileage data, and stores and processes the acquired digital signal data, analog signal data and mileage data.

A second aspect of the present utility model provides a control device for data acquisition for pipeline detection, wherein the control device includes a SoC processing unit integrated with a main FPGA unit and a processor, and wherein the main FPGA unit is configured to synchronously acquire digital signal data sensed by a digital sensor, analog signal data sensed by an analog sensor, and mileage data sensed by a mileage sensor, and store the acquired data in a memory, the processor communicates with the main FPGA unit through a bus, and reads data in the memory for processing, and wherein the main FPGA unit acquires data of the sensor in real time, a system of the processor is a multitasking Linux operating system, the main FPGA unit writes sensor data in real time in a cache of the memory, and the processor periodically processes real-time data acquired by the FPGA at one time.

The utility model provides a super-large-scale multichannel data synchronous acquisition architecture, which realizes the absolute synchronous acquisition of the same kind of data and the relative synchronous acquisition of different types of data and solves the synchronous stability under the abnormal conditions of electromagnetic interference and the like. The data synchronization ensures the alignment of the data, so that the quantitative analysis of the data is more accurate; especially, the existing large amount of artificial intelligence algorithms ensure the consistency of data in absolute synchronization, so that training models and data are matched more, and training efficiency and data identification accuracy are improved.

Drawings

In order to more clearly illustrate the technical solutions of the present utility model, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present utility model, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a data acquisition system for pipeline inspection according to an exemplary embodiment of the present utility model.

FIG. 2 is a block diagram of an implementation of a data acquisition system for pipeline detection according to an exemplary embodiment of the present utility model.

Fig. 3 is a block diagram of an implementation of a digital channel acquisition board according to an exemplary embodiment of the present utility model.

Fig. 4 shows a block diagram of an implementation of a digital acquisition sub-node according to an exemplary embodiment of the utility model.

Fig. 5 is a block diagram of an implementation of an analog channel acquisition board card according to an exemplary embodiment of the utility model.

Fig. 6 illustrates a block diagram of an implementation of an analog acquisition sub-node according to an exemplary embodiment of the present utility model.

FIG. 7 is a block diagram of an implementation of mileage preference logic according to an exemplary embodiment of the present utility model.

Fig. 8 shows a flowchart of an implementation of synchronization logic in a synchronization alignment unit according to an embodiment of the utility model.

Fig. 9 shows a schematic diagram of a control device for data acquisition for pipeline inspection in accordance with one or more embodiments of the utility model.

Fig. 10 shows a flow chart of a data acquisition method for pipeline detection according to an exemplary embodiment of the utility model.

DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION

As used herein, the terms "first," "second," and the like may be used to describe elements in exemplary embodiments of the present utility model. These terms are only used to distinguish one element from another element, and the inherent feature or sequence of the corresponding element, etc. is not limited by the terms. Unless defined otherwise, all terms (including technical or scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this utility model belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Those skilled in the art will understand that the devices and methods of the present utility model described herein and illustrated in the accompanying drawings are non-limiting exemplary embodiments and that the scope of the present utility model is defined solely by the claims. The features illustrated or described in connection with one exemplary embodiment may be combined with the features of other embodiments. Such modifications and variations are intended to be included within the scope of the present utility model.

Hereinafter, exemplary embodiments of the present utility model will be described in detail with reference to the accompanying drawings. In the drawings, detailed descriptions of related known functions or configurations are omitted so as not to unnecessarily obscure the technical gist of the present utility model. In addition, throughout the description, the same reference numerals denote the same circuits, modules or units, and repetitive descriptions of the same circuits, modules or units are omitted for brevity.

Furthermore, it should be understood that one or more of the following methods or aspects thereof may be performed by at least one control unit or controller. The terms "control unit", "controller", "control module" or "master" may refer to a hardware device comprising a memory and a processor. The memory or computer-readable storage medium is configured to store program instructions, and the processor is specifically configured to execute the program instructions to perform one or more processes that will be described further below. Moreover, it should be appreciated that the following methods may be performed by including a processor in combination with one or more other components, as will be appreciated by those of ordinary skill in the art.

The data in the pipeline usually needs a plurality of acquisition channels to acquire, and because the acquisition channels are more, synchronous acquisition reaches more than 4000 channels, and the singlechip system on the market generally acquires dozens of channels, so that real-time acquisition cannot be realized at all. In addition, a large number of acquisition channels involve the collaborative work of a plurality of submodules, some even one detection device has a plurality of complete acquisition systems, data synthesis is carried out through software after independent acquisition, the detection device has errors due to crystal oscillator frequency, so that basic synchronization can be ensured for data in a short time, after error accumulation for more than 24 hours is carried out, the acquired data can not be synchronized at all, even if larger synchronization errors are avoided through logic processing, small data deviation can influence judgment of the data, for example, the characteristic of girth weld is a specific data expression rule, once the deviation occurs, human eyes can not recognize the characteristic, an artificial intelligence algorithm can judge errors, and great uncertainty is brought to detection of pipelines.

The utility model provides a multichannel synchronous high-speed acquisition and storage system and a data acquisition and synchronization method. The system comprises a main control device and an acquisition extension sub-node which are connected through a self-defined SPI bus, wherein the acquisition sub-node is connected with a sensor, a mileage sensor is connected with a main control unit, and the main control unit can be connected with an upper computer through a kilomega network port. The system of the utility model supports two modes of timing sampling and mileage acquisition. The system can integrate multichannel data acquisition of the same type and can access various data of different types; by the aid of the homologous clock and the synchronous signal, absolute synchronous acquisition of the same type of data and relative synchronous acquisition of different types of data are achieved, and relative synchronous errors are accurate to be within one sampling period.

If shown in fig. 1, the system comprises a digital sensor group, an analog sensor group, a mileage sensor group, a digital channel acquisition board card, an analog channel acquisition board card and a control device, wherein the control device comprises a memory, and the control device is connected to an upper computer through a gigabit network port. The analog sensor group is used for acquiring analog signal data for sensing pipeline change, the digital sensor group is used for acquiring digital signal data for sensing pipeline change, and the mileage sensor group is used for acquiring mileage signal data for sensing mileage change. The data collected by the digital sensor and the analog sensor are respectively sent to the control device through the digital channel collection board card and the analog channel collection board card, and the mileage data collected by the mileage sensor is sent to the control device. The control device stores and processes the acquired digital signal data, analog signal data and mileage data.

As shown in fig. 2, in the data acquisition system, the control device is a main control unit, and the main control unit adopts a hardware system architecture of an fpga+cortex integrated SOC; when the method is realized, the on-chip FPGA is responsible for synchronous acquisition of external data through verilog programming, can carry out link expansion with an external FPGA junction box through a designed SPI bus, and stores the acquired data into the DDR for caching through the on-chip bus; and loading a Linux system on the chip Cortex kernel, hanging the DDR memory, the RTC and the gigabit network card, reading data cached in the DDR by the FPGA through a driver, processing and storing the data, and finally checking and exporting real-time data through the gigabit Ethernet. The main control unit comprises a main control board, an interface board, a power board, an auxiliary acquisition unit, a memory and a homologous clock.

According to one or more embodiments of the present utility model, the SOC chip of the control device of the present utility model is a ZYNQ-series chip, and includes an FPGA array and a CPU with an A9 core; the synchronous acquisition is mainly realized by an FPGA unit (comprising a main FPGA unit and a sub-FPGA unit, wherein the sub-FPGA unit is positioned in an FPGA junction box in fig. 2), the FPGA unit is responsible for data acquisition, the acquired data is stored in the DDR in real time for caching, and the CPU reads the data from the DDR for processing, wherein the FPGA has the characteristics of high processing efficiency but cannot complete complex logic; the CPU is characterized by completing complex operation, but the real-time performance is insufficient, so the utility model combines the two to realize the high-speed data acquisition and storage of the whole system. In fig. 2, the main FPGA unit directly writes the collected data into the DDR through the bus at regular time and in real time; the CPU reads the data from the DDR and stores the data.

According to one or more embodiments of the present utility model, the main control device includes a DDR memory, and because the data volume collected by the FPGA is particularly large and is a real-time system, the data can only be stored in the DDR after being collected; the system in the processor is a Linux operating system, is a multitasking and has large data processing capacity, but is not a real-time system, so after the FPGA collects data, the data is directly sent to the Linux system, and the Linux cannot respond with high probability.

As shown in fig. 3, the digital channel acquisition board includes a plurality of digital acquisition sub-nodes, each digital acquisition sub-node including: the digital signal data acquired by the digital sensor are sent to the digital sub-FPGA unit through the connector array and the digital bus interface, and the digital sub-FPGA unit is used for acquiring the digital signal data in the corresponding digital acquisition sub-node in real time.

As shown in fig. 3, the mileage module (or mileage processing unit) in the main control unit is mainly for realizing mileage sampling; the timing samples may be 1ms one data point; mileage sampling may be 1mm from one data point; the crystal oscillator is used for generating a crystal oscillator with a clock frequency; the PLL is a phase-locked loop, and can multiply or divide the frequency of a clock generated by the crystal oscillator; the auxiliary acquisition module is used for realizing magnetic flux leakage detection; the cable is a physical cable and AXI is a Soc connection bus between the main FPGA and the processor Cortex.

As shown in fig. 4, the digital sub-FPGA unit is implemented by using the digital acquisition sub-node shown in fig. 4, the digital sensor senses the magnetic leakage signal of the 36 channel, and sends the magnetic leakage signal to the digital sub-FPGA unit through the connector array and the digital bus interface, and the digital sub-FPGA unit sends the magnetic leakage signal to the main control unit shown in fig. 3 through the connector after the conversion of the single-ended and differential signals through the homologous clock, the synchronous signal and the SPI bus.

Fig. 5 shows a block diagram of an implementation of an analog channel acquisition board card according to an exemplary embodiment of the utility model.

As shown in fig. 5, the analog channel acquisition board includes a plurality of analog acquisition sub-nodes, wherein each analog acquisition sub-node includes: the analog signal data acquired by the analog sensor are sent to the analog sub-FPGA unit after analog-to-digital conversion through the analog connector array and the operational amplifier, and the analog sub-FPGA unit is used for acquiring the analog signal data in the corresponding analog acquisition sub-node in real time.

As shown in fig. 6, the analog sub-FPGA unit is implemented by using the analog acquisition sub-node shown in fig. 6, the analog data sensed by the 64 analog sensors are sent to the analog sub-FPGA unit through the cable, the connector array, the operational amplifier and the ADC converter, and the analog sub-FPGA unit is sent to the main control unit shown in fig. 3 through the connector after being converted by the single-ended and differential signals through the homologous clock, the synchronous signal and the SPI bus.

According to one or more embodiments of the utility model, the sensor of the data acquisition system has two types of digital interface output and analog interface output, a single chip microcomputer is added to be directly connected with a sensor chip during the design of the digital sensor, and the single chip microcomputer is connected with a digital sub-FPGA unit of a sub-node through a differential bus; the analog output sensor is connected with an ADC (analog to digital) converter of the sub-node, and the ADC converter is directly connected with a sub-FPGA unit of the analog sub-node; and finally, transmitting the data to the main control unit through the analog or digital sub-FPGA unit.

According to one or more embodiments of the present utility model, a communication protocol between a main FPGA unit and a sub FPGA unit of the data acquisition system is mainly an SPI, which is a preferred communication protocol with stable bus number and communication, and may also be a UART, IIC, parallel port or the like, and the SPI is 3 wires for unidirectional communication and 4 wires for bidirectional communication; when the transmission distance is longer, the signal line can be converted into a differential signal line by using a conversion chip, so that the anti-interference capability is stronger; the communication rate of the SPI is between 1Mhz and 50Mhz, and the communication is carried out according to the data volume of the child node, preferably the low-frequency rate; the maximum data communication rate of the single signal line is 6.25MBytes; because the system is communication among the FPGA, the group of SPIs can simultaneously have two or more data transmission lines for data transmission, and only one signal line and chip selection line are needed to realize frequency multiplication of communication rate. Specifically, the conventional SPI is generally divided into 4 lines, CS, SCK, MOSIMISO, and the communication modes are serial communication, so that 8 lines are needed for two groups of SPI, and the custom SPI bus in the utility model shares the 5 lines CS, SCK, MOSI, MISO and MISO2 as the data lines, so that the 8-line communication rate in the conventional SPI bus can be realized, and the connected data lines are greatly reduced.

According to one or more embodiments of the present utility model, the data acquisition system of the present utility model can support 18434 channel data synchronous acquisition at most, and the main FPGA unit can expand 32 FPGA sub-nodes at most through the SPI bus; each sub-node can be connected with a 16-channel digital signal or a 64-channel analog signal, and each digital probe can acquire 36-channel data; the radial sampling interval of single triaxial magnetic leakage is smaller than 2mm, taking a triaxial sampling point per 2mm of the largest diameter of 1422mm in China as an example, and a formula (the number of acquisition channels=the diameter of a pipeline X3.14×three-axis 3 channels/sampling interval) 1422 (mm) 3×14×3/2 (mm) =6698 channels; the data system is far higher than the index, and can support data acquisition with larger caliber or higher precision; the number of sub-node channels can be reduced according to the real size space. The analog acquisition channel may acquire an eddy current (IDOD) signal (geometric angle hall sensor signal).

According to one or more embodiments of the utility model, the data acquisition system supports 20Khz synchronous sampling, and an ADC chip with the speed higher than 20Khz and a high-speed Hall sensor are selected; the data acquisition system supports a timing sampling storage mode and a mileage sampling mode, and the mileage sampling mode supports the acquisition and storage of one data point smaller than 1 mm. For example: the flow rate of fluid in the oil way pipeline is usually between 0.5m/s and 5m/s, the highest flow rate is 10m/s, and the 20Khz sampling of the system can be carried out once every 0.5mm under the flow rate of 10 m/s; in view of optimization of the real-world accuracy and the data amount, it is preferable to store one data point every 1 mm; the practical application of a 5k sampling rate meets the accuracy requirements of most pipeline detection.

According to one or more embodiments of the present utility model, the sampling channel and sampling rate of the data system of the present utility model may be flexibly configured according to actual requirements, where FPGA sub-nodes (or sub-FPGA units) may be connected to at least one, and the sensor signal may be accessed to at least 1 path; the format of the data storage channel can be configured by sending a command through gigabit network port communication; the sampling rate is tuned by adjusting the clock rate of the main FPGA unit, for example: the range of 100 Hz-20 Khz can be adjusted, and the configuration is carried out by issuing instructions through the Ethernet.

According to one or more embodiments of the present utility model, the data acquisition system of the present utility model supports file system storage, can mount 8 blocks of 8TB solid state hard disks, maximally supports 64TB storage capacity, and can also mount 8 1TB TF cards for storage; the magnetic flux leakage data is stored according to 18434 channels, 16 bits (2 Bytes) and one point stored every 1mm, and the required capacity per kilometer is (capacity per kilometer=channel number X per channel data amount X1 kilometer/1 mm) =18432X 2Bytes X1000000/1= 36864000000 bytes= 36.864GB; the 64TB may store a mileage of 64TB/36.864GB per kilometer=1736 kilometers; the file system preferably has an EXT file storage format.

According to one or more embodiments of the present utility model, the data acquisition system is connected to the upper computer through gigabit ethernet, and the Linux system communicates with the upper computer through TCP/IP protocol and FTP protocol, where the data transmission rate can reach 1000Mbps.

According to one or more embodiments of the present utility model, a mileage processing unit is included in the control device or the main control unit of fig. 3, and the mileage processing unit supports a mileage sampling mode and also supports mileage preference logic (i.e., includes a plurality of mileage wheels), and when the control device of the present utility model may set two or more mileage wheels, the fastest mileage wheel is used as a mileage sampling reference. The mileage optimization logic is to mark a main mileage wheel and clear the state, the main mileage wheel is directly collected and cleared after triggering (i.e. the data collection action is executed once when the count reaches a threshold value, for example, the data collection action is executed once when the count is triggered once by 1mm distance, the clear state is recounting), and if the secondary mileage wheel is triggered 2 times within the interval of two triggering of the main mileage wheel, the current secondary mileage wheel is switched to the main mileage wheel, and the data collection and clear state is executed. The mileage sensor can be realized by an encoder, a magnetic Hall angle sensor and a proximity switch. The mileage preference logic may be implemented in hardware circuitry contained in the main control unit or the control device or in a software program in the processor.

As shown in fig. 7, at S11: setting two or more mileage wheels, taking the mileage wheel with the fastest rotation as a mileage sampling reference, marking the mileage wheel as a main mileage wheel, and setting a response time counter in each mileage wheel;

s12: each mileage wheel works independently, and when the mileage is detected to advance to reach one mileage sampling interval, the response times are increased by 1 in a counter when the mileage wheel responds;

s13: judging whether the response times in the counter of the main mileage wheel is more than or equal to 1 in the sampling interval;

s14: if the response times in the counter of the main mileage wheel is greater than or equal to 1, collecting all data once;

s15: if the response times in the response counter of the main mileage wheel is less than 1 in the sampling interval, sequentially determining whether the response times of the response counters of other mileage wheels have channels which are more than or equal to 2;

s16: if the response times of the response counters of the other mileage wheels are provided with channels which are more than or equal to 2, marking the mileage wheels with the response times which are more than or equal to 2 as main mileage wheels, and collecting all data once;

S17: after the data acquisition is completed once, all the counters of all the mileage wheels are cleared, and the data acquisition of the next mileage interval is carried out.

According to one or more embodiments of the present utility model, the data stored by the data acquisition system may be synchronously fused with other detector data, for example, the data acquisition system of the present utility model is equipped with an RTC clock chip (such as RX 8025) with 2ppm error and temperature compensation for GPS positioning, and before the device runs, GPS clock pair is performed once; the absolute time is recorded in each data point during data acquisition and storage, so that data alignment can be carried out through an RTC absolute clock with other data carrying the same accurate time; absolute mileage information is recorded in the data collected by the utility model, and alignment or data splicing can be performed according to mileage (namely, short mileage data are spliced to long mileage data).

According to one or more embodiments of the utility model, the mileage processing module implements a mileage alignment function. For example: a pipeline is 200 km from the same entrance, the relative distance is fixed, if the sampled data contains this distance information, the distance can be used for alignment, the actual final data in the pipeline detector is shown in mileage, and the timing sampling is just the implementation process. The mileage processing module realizes the mileage splicing function. For example, the internal battery of the mileage detector can only run for 100 km, but one pipeline has a length of 200 km, so that the pipeline of 0-100 km can be detected by the No. 1 detector, then the pipeline of 2 # is dormant, only the mileage distance is detected, and all functional detection is started after reaching 100 km, thus the pipeline detection of 200 km is realized by the two detection.

According to one or more embodiments of the present utility model, data collected by a data collection system includes: magnetic flux leakage data, magnetic disturbance eddy current data, geometric angle data, attitude acceleration gyroscope data, pressure, electric quantity and temperature data.

According to one or more embodiments of the present utility model, a main FPGA unit communicates with digital sub-FPGA units and analog sub-FPGAs in an analog channel acquisition board and a digital channel acquisition board through multiple sets of SPI buses, and the main FPGA unit transmits a homologous clock signal and a synchronization signal to the digital sub-FPGA units and the analog sub-FPGA units. The control device or the main control unit comprises an RTC clock chip, GPS clock time synchronization is carried out once before the data acquisition system operates, absolute time of each data point is recorded when the control device acquires and stores sensing data, and data alignment of sensing data of all sensors is carried out through the GPS clock. The mileage sensing data comprises absolute mileage information, and the analog sensing data and the digital sensing data are subjected to mileage alignment or mileage data stitching as described above according to the absolute mileage information.

According to one or more embodiments of the present utility model, the data acquisition system of the present utility model is a multi-sensor synchronous acquisition system, the sensor has a plurality of sub-nodes, and has a plurality of data inputs with different types and different sampling rates, and in order to realize synchronous acquisition and storage of data, the data system of the present utility model specifically designs a set of synchronization mechanism, which can realize absolute synchronous acquisition of the same type of data, and relative synchronous acquisition of different types of data, so that different synchronization errors of sensed data are within a sampling period.

According to one or more embodiments of the present utility model, when the absolute synchronous acquisition of the same sensor is implemented, firstly, the whole system of the data acquisition system of the present utility model shares a set of clock sources, so as to ensure that the clock frequency and the phase are consistent, the main control unit inputs the crystal oscillator frequency, then carries out frequency multiplication adjustment through the PLL to obtain a desired clock, and distributes the clock to 32 sub-FPGA units, and carries out synchronous output of the clock through GPIO (general purpose input output pin), and the sub-FPGA units of each sub-node of the system use the clock output by the control device (or the main control unit) as the clock source, so that the clock frequency and the phase of the whole system are absolutely synchronous. When the system operates, as the sub-FPGA units are connected with the main FPGA units through cables, the cable is subject to an interference clock source to possibly generate a frequency loss phenomenon in the data acquisition operation process, and in order to solve the problem, the utility model adds a low-frequency synchronous signal in each FPGA sub-node (the sub-FPGA unit) and the main node (the main FPGA unit), and the main node divides the frequency through a homologous clock and transmits one low-frequency synchronous signal every N sampling periods; after receiving the synchronous signal, the child node can complete the sampling period, and after the child FPGA unit completes sampling, the next sampling period is aligned and synchronized, so that the absolute synchronization of the subsequent sampling point and the synchronous signal is ensured.

A synchronization alignment unit is included in the control device (or master control unit) that ensures that the sampling points are in absolute synchronization with the synchronization signal, the absolute synchronization comprising an absolute synchronization of the sampling rate and the sampling phase. The sequential logic of data transmission is: and when synchronization starts, setting 0 for the synchronization signal in the sub-FPGA unit, setting 1 for the synchronization signal if the synchronization signal reaches the rising edge, finishing data transmission on the rising edge of the synchronization signal, setting 0 for the synchronization signal, and continuously detecting whether the synchronization signal reaches the rising edge if the synchronization signal does not reach the rising edge. As shown in fig. 8, the synchronization logic in synchronization alignment includes:

s21: setting a first counter and a second counter in each analog sub-FPGA unit or each digital sub-FPGA unit, and resetting the first counter and the second counter;

s22: after receiving the synchronous clock signal sent by the control device, adding 1 to the first counter;

s23, judging whether the synchronous signal is 1;

s24: if the synchronous signal is 1, adding 1 to the second counter, and then judging whether the value in the first counter is larger than a preset constant or not;

S25: if the synchronous signal is not 1, judging whether the value in the first counter is larger than a preset constant or not;

s26: if the value in the first counter is larger than or equal to a preset constant, the sub-FPGA unit collects data and sends the data,

s27: if the value in the first counter is smaller than the preset constant, returning to the step S22;

s28: after step S25, it is continued to determine whether the synchronizing clock signal is 1,

s29: if the synchronous clock signal is not 1, returning to step S21;

s30 if the synchronization signal is 1, the value of counter a is set to the value of counter B,

s31: the value of the counter B is cleared, and then the process returns to step S22.

In the synchronization mechanism, because the main FPGA unit and the sub FPGA unit are homologous clocks, the synchronization signal is sent when the counter a is a preset constant, so the counter B is always 0 under normal conditions, when the counter a loses frequency, the synchronization signal arrives when the counter a is smaller than the preset constant, so the counter a in the next cycle shortens the counting cycle according to the counter B, and is aligned with the synchronization clock.

According to one or more embodiments of the present utility model, an error control logic is further included in the control device, by which the control device maintains a synchronization error of the collected data of the different sensor types within one sampling interval, the error control logic comprising: setting minimum sampling intervals of an analog sub-FPGA unit and a digital sub-FPGA unit, wherein each sub-FPGA unit collects data once in each minimum sampling interval, when the data in the sensor is updated in the minimum sampling interval, the new data is sent to the control device, and when the data in the sensor is not updated in the minimum sampling interval, the sampled data in the last sampling interval is repeatedly sent to the control device. For example, in order to realize synchronous acquisition of different sensors, each sub-node of the data acquisition system acquires data once every 0.05ms, when the sensor has data update, new data is sent to the main node, and when the data of 0.05ms is not updated, the last data is repeatedly sent to the main node, so that the synchronous error of the data is ensured to be within one sampling point and not more than 0.05ms.

The data acquisition system of the utility model can acquire and process data of different sensor types. For example, the magnetic leakage and the eddy current are different sensors, the magnetic leakage can only detect whether metal loss exists on the metal pipe wall and how much metal is lost, but the loss is on the inner wall or the outer wall of the pipeline cannot be identified, an eddy current signal cannot be quantized, and only the signal reaction exists on the loss inside the pipeline; therefore, the magnetic leakage system needs to process the data of the two sensors simultaneously for identifying the defect, and the data of the two sensors at the same position are identified simultaneously, so that the inner wall or the outer wall is identified simultaneously when the defect is identified.

According to one or more embodiments of the present utility model, the memory is set as a plurality of buffers or a plurality of memories, and the collected sensor data is stored in the plurality of buffers or in the plurality of memories by interleaving, so that when one memory or buffer fails, it is ensured that one low-definition complete data can still be obtained. For example: the complete basic data analysis function can be realized under the condition of single failure of the equipment.

According to one or more embodiments of the utility model, the ultra-high definition data sampling interval is typically 1-2mm, the high definition device sampling interval is 3mm, and the detection device sampling interval is typically 6mm. Therefore, the odd channels of the data channels are stored in the A memory, the even channels of the data channels are stored in the B memory, and when one of the memories is abnormal, the complete detection data with one-level definition can be obtained. The utility model preferably uses two sets of data storage, and can be stored in three sets, four sets or more in practical use. For example, if a face such as 10mm of the acquisition tube has 10 probes corresponding to 0-1mm,1-2mm … … -10mm, respectively, the resolution is 1mm, and if 1, 3, 5, 7, 9 are combined into a single queue, the resolution is 2mm. In pipeline detection, ultra-high definition mainly refers to detection interval of a sensor, resolution, such as detecting a steel plate with the width of 10mm, and 10 probes respectively correspond to 0-1mm and 1-2mm … … -10m, so that the resolution is 1mm, and each probe needs 3 acquisition channels in three directions, namely one point. Taking 1422mm caliber as an example, perimeter 4465, 4465/6*3 =2233 channels are required per 6mm probe; 4465 channels are required per 3mm of probe, so the ultra-high definition resolution of the acquired data can be understood as a data resolution similar to pixels.

According to one or more embodiments of the present utility model, there is further provided a control apparatus for data acquisition for pipeline inspection, the control apparatus including a main FPGA unit and a SoC processing unit integrated with a processor, and wherein the main FPGA unit is configured to synchronously acquire digital signal data sensed by a digital sensor, analog signal data sensed by an analog sensor, and mileage data sensed by a mileage sensor, and to buffer the acquired data in a memory, and the processor is in communication with the main FPGA unit through a bus, and to read the data in the memory for processing. The processor is an on-chip Cortex kernel and loads a Linux system.

According to one or more embodiments of the present utility model, the control apparatus of the present utility model further includes a mileage processing unit (executing mileage preference logic as shown in fig. 7), error control logic. The mileage preference logic and the error control logic have been described in detail in the previous description of the data acquisition system and are not described in detail herein.

According to one or more embodiments of the present utility model, there is also provided a data acquisition method for pipeline inspection, the method comprising:

s1: acquiring digital signal data for sensing the change of the pipeline through a plurality of digital sensors, acquiring analog signal data for sensing the change of the pipeline through a plurality of analog sensors, and acquiring mileage signal data for sensing the change of the mileage through a plurality of mileage sensors;

s2: the digital signal data and the analog signal data are sent to a control device through a digital channel acquisition board card and an analog channel acquisition board card, and mileage data acquired by the mileage sensor are sent to the control device;

s3: and storing and processing the acquired sensing data through the control device.

According to one or more embodiments of the present utility model, the data acquisition method for pipeline detection includes a mileage optimization step, a synchronization step between the main FPGA unit and the sub FPGA unit, and a cross storage step, and the detailed description of the data acquisition system is omitted herein.

The data acquisition scheme for pipeline detection designs a super-large-scale multichannel data synchronous acquisition architecture, realizes the absolute synchronous acquisition of the same kind of data and the relative synchronous acquisition of different types of data, and solves the synchronous stability under the abnormal conditions of electromagnetic interference and the like. The data synchronization ensures the alignment of the data, so that the quantitative analysis of the data is more accurate; especially, the existing large amount of artificial intelligence algorithms ensure the consistency of data in absolute synchronization, so that training models and data are matched more, and training efficiency and data identification accuracy are improved.

The data acquisition system can realize synchronous acquisition of the detector data in the ultra-high definition pipeline, the ultra-high definition data is displayed more clearly, the defect quantification is more accurate, the number of channels is increased by 1mm, the fault tolerance of the system can be increased through staggered storage and cross transmission of signal lines, when part of device functions fail, the system can still obtain complete data with low primary definition, and the secondary detection process is avoided under the condition that the data is available. When the signal of the individual channel is abnormal, warning or deviation correction can be carried out through the adjacent channel data;

The data acquisition system of the utility model uses the improved SPI bus, and a group of SPI buses are added with synchronous data lines, thereby realizing higher data bandwidth; and compared with the parallel port bus, the parallel port bus has the advantages of less cables, more flexibility and convenience.

The data acquisition system can be compatible with the access of data of different acquisition units, realizes the synchronous acquisition of diversified data, and is accessed with collectors such as magnetic leakage, IDOD, geometry, IMU, mileage, battery voltage, temperature, pressure and the like through an SPI interface; the method has strong expansibility and good compatibility, and ensures the synchronism of data.

The data acquisition system designs the homologous clock and the synchronous signal, can realize the absolute synchronization of the same kind of acquired data, comprises frequency and phase synchronization, and can meet any acquisition application with high requirement on multichannel synchronization.

In accordance with one or more embodiments of the present utility model, control logic in the apparatus and systems of the present utility model may implement processes as in the above systems of the present utility model using encoded instructions (e.g., computer and/or machine readable instructions) stored on a non-transitory computer and/or machine readable medium (e.g., hard disk drive, flash memory, read-only memory, optical disk, digital versatile disk, cache, random access memory, and/or any other storage device or storage disk) where information during any time period (e.g., extended period of time, permanent, transient instance, temporary cache, and/or information cache) is stored. As used herein, the term "non-transitory computer-readable medium" is expressly defined to include any type of computer-readable storage device and/or storage disk and to exclude propagating signals and to exclude transmission media.

Logic in the system of the present utility model may be implemented using control circuitry, (control logic, a master control system, or a control module) that may include one or more processors or may include a non-transitory computer readable medium therein, in accordance with one or more embodiments of the present utility model. In particular, the master control system or control module may comprise a microcontroller MCU. Processors used to implement the processing of logic in the system of the present utility model may be, for example, but are not limited to, one or more single-core or multi-core processors. The processor(s) may include any combination of general-purpose processors and special-purpose processors (e.g., graphics processors, application processors, etc.). The processor may be coupled to and/or may include a memory/storage device and may be configured to execute instructions stored in the memory/storage device to implement various applications and/or operating systems running on the controller of the present utility model.

The following are further examples of the utility model:

example 1. A data acquisition system for pipeline inspection, the system comprising: a digital channel acquisition board card, an analog channel acquisition board card and a control device, wherein,

The control device receives the collected digital signal data related to the pipeline change through the digital channel collecting board card, receives the collected analog signal data related to the pipeline change through the analog channel collecting board card, and receives the collected mileage data, and the control device stores and processes the collected digital signal data, the analog signal data and the mileage data. The system further comprises: a plurality of digital sensors for sensing the pipe change output digital signal data, a plurality of analog sensors for sensing the pipe change output analog signal data, a plurality of mileage sensors for sensing mileage changes.

Example 2. The system of example 1, wherein,

the control device comprises a SoC processing unit integrated by a main FPGA unit and a processor, and

the main FPGA unit is used for synchronously collecting the digital signal data, the analog signal data and the mileage data, caching the data in the memory, and the processor is communicated with the main FPGA unit through the bus and reads the data in the memory for processing.

Example 3. The system of example 1, wherein the processor is an on-chip Cortex kernel and loads a Linux system.

Example 4 the system of example 1, wherein the digital channel acquisition board comprises a plurality of digital acquisition sub-nodes, each digital acquisition sub-node comprising: digital connector array, digital bus interface, digital sub-FPGA unit, and

the digital signal data acquired by the digital sensor are sent to the digital sub-FPGA unit through the connector array and the digital bus interface, and the digital sub-FPGA unit is used for acquiring the digital signal data in the corresponding digital acquisition sub-node in real time.

Example 5 the system of example 4, wherein the analog channel acquisition board includes a plurality of analog acquisition sub-nodes, wherein each analog acquisition sub-node includes: analog connector array, operational amplifier, ADC converter, analog sub-FPGA unit, and method for manufacturing the same

The analog signal data acquired by the analog sensor are sent to the analog sub-FPGA unit after analog-to-digital conversion through the analog connector array and the operational amplifier, and the analog sub-FPGA unit is used for acquiring the analog signal data in the corresponding analog acquisition sub-node in real time.

Example 6 the system of example 5, wherein the master FPGA unit communicates with the digital sub-FPGA unit and the analog sub-FPGA in the analog channel acquisition board and the digital channel acquisition board over multiple sets of SPI buses, and the master FPGA unit sends a homologous clock signal and a synchronization signal to the digital sub-FPGA unit and the analog sub-FPGA unit.

Example 7. The system of example 6, wherein the set of SPI buses simultaneously carries out data transmission with a plurality of data lines, and comprises a clock signal line and a chip select line.

Example 8. The system of example 1, wherein the control device is connected to the host computer through a network, the data processed by the control device is sent to the host computer, and the host computer configures the data acquisition parameters of the system by sending instructions to the control device.

Example 9 the system of example 1, wherein the data collected by the data collection system comprises: magnetic flux leakage data, magnetic disturbance eddy current data, geometric angle data, attitude acceleration gyroscope data, pressure, electric quantity and temperature data.

Example 10. The system of example 1, wherein the mileage sensor is implemented with any one of an encoder, a magnetic hall angle sensor, a proximity switch implementation.

Example 11. The system of example 1, wherein the control device further includes an auxiliary acquisition unit configured to detect magnetic flux leakage in the pipeline.

Example 12 the system of example 2, wherein the main FPGA unit collects data sensed by the plurality of digital sensors, the plurality of analog sensors, and the plurality of mileage sensors in real time, the system of the processor is a multitasking Linux operating system, the main FPGA unit writes the data sensed by the sensors into a cache of the memory in real time, and the processor processes the real-time data collected by the FPGA at one time at irregular intervals.

Example 13 the system of example 1, wherein the control device further comprises a mileage processing unit that implements mileage sampling with mileage preference logic comprising:

s11: setting two or more mileage wheels, taking the mileage wheel with the fastest rotation as a mileage sampling reference, marking the mileage wheel as a main mileage wheel, and setting a response time counter in each mileage wheel;

Example 14. The system of example 1, wherein the control device includes an RTC clock chip, and before the system operates, performing GPS clock synchronization once, and when the control device collects and stores the sensing data, recording an absolute time of each data point, and performing data alignment of the sensing data of all the sensors through the GPS clock; and

and the mileage sensing data comprises absolute mileage information, and the analog sensing data and the digital sensing data are subjected to mileage alignment or mileage data splicing according to the absolute mileage information.

Example 15. The system of example 1, wherein the control device further includes a synchronization processing unit, the control device distributes the general purpose input/output signal to each of the analog and digital sub-FPGA units for synchronous output of the clock, and each of the analog and digital sub-FPGA units uses the clock signal output by the control device as a clock source.

Example 16 the system of example 6, wherein each of the analog and digital sub-FPGA units includes a synchronization alignment unit therein that performs absolute synchronization of the sampling frequency and phase by executing synchronization logic comprising:

s23, judging whether the synchronous signal from the main FPGA unit is 1;

s29: if the synchronous clock signal is not 1, returning to step S21;

Example 17. The system of example 6, the control device to maintain synchronization errors of the collected data for the different sensor types within a sampling interval via error control logic, the error control logic comprising:

Setting minimum sampling intervals of an analog sub-FPGA unit and a digital sub-FPGA unit, wherein each sub-FPGA unit collects data once in each minimum sampling interval, when the data in the sensor is updated in the minimum sampling interval, the new data is sent to the control device, and when the data in the sensor is not updated in the minimum sampling interval, the sampled data in the last sampling interval is repeatedly sent to the control device.

Example 18. The system of example 2, wherein the memory is configured as a plurality of buffers or a plurality of memories, the collected sensor data being stored across the plurality of buffers or in the plurality of memories, ensuring that a low definition complete data is still available when one memory or buffer fails.

Example 19. A control device for pipe inspection, wherein the control device comprises a SoC processing unit integrated with a main FPGA unit and a processor, and wherein the main FPGA unit is configured to synchronously collect digital signal data from digital sensor sensing, analog signal data from analog sensor sensing, and mileage data from mileage variations sensed by mileage sensor, and to buffer the collected data in a memory, and the processor is in communication with the main FPGA unit via a bus and to read the data in the memory for processing.

Example 20. The control device of example 19, wherein the processor is an on-chip Cortex kernel and loads a Linux system.

Example 21. The control device of example 19, wherein the control device is connected to an upper computer via a network, the data processed by the control device is sent to the upper computer, and the upper computer sends an instruction to the control device to configure data acquisition parameters.

Example 22. The control apparatus of example 19, wherein the main FPGA unit collects data of the sensor in real time, the system of the processor is a multitasking Linux operating system, the main FPGA unit writes the sensor data into a cache of the memory in real time, and the processor processes the real-time data collected by the FPGA at one time at an irregular period.

Example 23. The control device of example 19, wherein the master FPGA unit communicates with digital and analog sub-FPGA units in the external analog channel acquisition board and the digital channel acquisition board through multiple sets of SPI buses, and the master FPGA unit sends a homologous clock signal and a synchronization signal to the digital and analog sub-FPGA units;

wherein, the digital channel acquisition board card includes a plurality of digital acquisition subnodes, and wherein every digital acquisition subnode includes: the digital signal data acquired by the digital sensor are sent to the digital sub-FPGA unit through the connector array and the digital bus interface, and the digital sub-FPGA unit is used for acquiring the digital signal data in the corresponding digital acquisition sub-node in real time; and

Wherein, analog channel gathers board card and includes a plurality of analog collection subnodes, and wherein every analog collection subnode includes: the analog signal data acquired by the analog sensor are sent to the analog sub-FPGA unit after analog-to-digital conversion through the analog connector array and the operational amplifier, and the analog sub-FPGA unit is used for acquiring the analog signal data in the corresponding analog acquisition sub-node in real time.

Example 24. The control device of example 23, wherein the control device further includes a synchronization processing unit, the control device distributes the general purpose input/output signal to each of the analog and digital sub-FPGA units for synchronous output of the clock, and each of the analog and digital sub-FPGA units uses the clock signal output by the control device as a clock source.

Example 25. The control device of example 24, wherein the control device further comprises a mileage processing unit that implements mileage sampling with mileage preference logic comprising:

Example 26. The control device of example 23, wherein the control device maintains a synchronization error of the collected data for the different sensor types within a sampling interval via error control logic, the error control logic comprising:

Example 27 the control device of example 19, wherein the control device maintains a synchronization error of the collected data for the different sensor types within a sampling interval via error control logic, the error control logic comprising:

Example 28. The control apparatus of example 19, wherein the memory is configured as a plurality of buffers or a plurality of memories, and the collected sensor data is stored in the plurality of buffers or in the plurality of memories by interleaving, to ensure that one low-definition complete data is still available when one memory or buffer fails.

Example 29. A data acquisition method for pipeline inspection, the method comprising:

Example 30. The method of example 29, wherein the control device includes a SoC processing unit integrated with the main FPGA unit and the processor, and wherein the sensing data is synchronously acquired by the main FPGA unit in the control device, and the acquired data is cached in the memory, and the data in the memory is read and processed by the processor in the control device.

Example 31 the method of example 29, wherein the digital channel acquisition board includes a plurality of digital acquisition sub-nodes, each digital acquisition sub-node includes a digital sub-FPGA unit for real-time acquisition of digital signal data in the corresponding digital acquisition sub-node, and the analog channel acquisition board includes a plurality of analog acquisition sub-nodes, each analog acquisition sub-node includes an analog sub-FPGA unit for real-time acquisition of analog signal data in the corresponding analog acquisition sub-node.

Example 32. The method of example 30, wherein the main FPGA unit collects data of the sensor in real time, the system of the processor is a multitasking Linux operating system, the main FPGA unit writes the sensor data into a cache of the memory in real time, and the processor processes the real-time data collected by the FPGA at one time at irregular intervals.

Example 33 the method of example 31, further comprising a mileage optimization step comprising:

Example 34 the method of example 31, further comprising a synchronization step between the main FPGA unit and the sub FPGA unit, the synchronization step comprising:

s21: setting a first counter and a second counter in a sub-FPGA unit, and resetting the first counter and the second counter;

s23, judging whether the synchronous signal from the main FPGA unit is 1;

s29: if the synchronous clock signal is not 1, returning to step S21;

Example 35 the method of example 31, further comprising an error control step of maintaining a synchronization error of the different sensor types of acquired data within one sampling interval by error control logic, the error control step comprising:

Setting the minimum sampling interval of the sub-FPGA units, wherein each sub-FPGA unit collects data once in each minimum sampling interval, when the data in the sensor is updated in the minimum sampling interval, the new data is sent to the control device, and when the data in the sensor is not updated in the minimum sampling interval, the sampled data of the last sampling interval is repeatedly sent to the control device.

Example 36 the method of example 29, further comprising a cross-store step comprising: the storage is set to be a plurality of cache areas or a plurality of storages, and the acquired sensor data are stored in the plurality of cache areas or the plurality of storages in a crossing way, so that when one storage or the cache breaks down, the low-definition complete data can be obtained.

The figures and detailed description of the utility model referred to above as examples of the utility model are intended to illustrate the utility model, but not to limit the meaning or scope of the utility model described in the claims. Accordingly, modifications may be readily made by one skilled in the art from the foregoing description. In addition, one skilled in the art may delete some of the constituent elements described herein without deteriorating the performance, or may add other constituent elements to improve the performance. Furthermore, one skilled in the art may vary the order of the steps of the methods described herein depending on the environment of the process or equipment. Thus, the scope of the utility model should be determined not by the embodiments described above, but by the claims and their equivalents.

While the utility model has been described in connection with what is presently considered to be practical, it is to be understood that the utility model is not to be limited to the disclosed embodiments, but on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A data acquisition system for pipeline inspection, the system comprising: a digital channel acquisition board card, an analog channel acquisition board card and a control device, wherein,

the control device receives the collected digital signal data related to the pipeline change through the digital channel collecting board card, receives the collected analog signal data related to the pipeline change through the analog channel collecting board card, receives the collected mileage data, and

the control device stores and processes the acquired digital signal data, analog signal data and mileage data.

2. The system of claim 1, wherein the system further comprises:

a plurality of digital sensors for sensing the pipe change output digital signal data, a plurality of analog sensors for sensing the pipe change output analog signal data, a plurality of mileage sensors for sensing mileage changes.

3. The system of claim 2, wherein,

4. The system of claim 3, wherein the digital channel acquisition board comprises a plurality of digital acquisition sub-nodes, each digital acquisition sub-node comprising: digital connector array, digital bus interface, digital sub-FPGA unit, and

5. The system of claim 4, wherein the analog channel acquisition board comprises a plurality of analog acquisition sub-nodes, wherein each analog acquisition sub-node comprises: analog connector array, operational amplifier, ADC converter, analog sub-FPGA unit, and method for manufacturing the same

6. The system of claim 5, wherein the master FPGA unit communicates with digital and analog sub-FPGA units in the analog and digital channel acquisition boards over multiple sets of SPI buses, and the master FPGA unit sends homologous clock and synchronization signals to the digital and analog sub-FPGA units.

7. A system as in claim 6, wherein a set of SPI buses simultaneously carry data transmissions over a plurality of data lines, and comprises a clock signal line and a chip select line.

8. The system of claim 1, wherein,

the control device comprises an RTC clock chip, GPS clock time synchronization is carried out once before the system operates, absolute time of each data point is recorded when the control device collects and stores sensing data, and data alignment of sensing data of all sensors is carried out through the GPS clock; and

And the mileage sensing data comprises absolute mileage information, and the analog signal data and the digital signal data are subjected to mileage alignment or mileage data splicing according to the absolute mileage information.

9. The system according to claim 1, wherein the control device further comprises a synchronization processing unit, the control device distributes general input and output signals to each analog sub-FPGA unit and each digital sub-FPGA unit for synchronous output of clocks, and each analog sub-FPGA unit and each digital sub-FPGA unit take the clock signals output by the control device as clock sources.

10. The system of claim 3, wherein the main FPGA unit collects data sensed by the plurality of digital sensors, the plurality of analog sensors and the plurality of mileage sensors in real time, the system of the processor is a multitasking Linux operating system, the main FPGA unit writes the data sensed by the sensors into a buffer memory of the memory in real time, and the processor processes real-time data collected by the FPGA at one time at irregular intervals.

11. A control device for data acquisition for pipeline inspection, wherein the control device comprises a SoC processing unit integrated with a main FPGA unit and a processor, and wherein the main FPGA unit is configured to synchronously acquire digital signal data sensed by a digital sensor, analog signal data sensed by an analog sensor, and mileage data sensed by a mileage sensor, and store the acquired data in a memory, and the processor communicates with the main FPGA unit through a bus and reads the data in the memory for processing, and

The main FPGA unit is used for collecting the data of the sensor in real time, the system of the processor is a multitasking Linux operating system, the main FPGA unit is used for writing the sensor data into a cache of the memory in real time, and the processor is used for processing the real-time data collected by the FPGA at one time at random.