CN220325604U - Continuously adjustable triggerable pulse generating circuit - Google Patents
Continuously adjustable triggerable pulse generating circuit Download PDFInfo
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- CN220325604U CN220325604U CN202321543369.8U CN202321543369U CN220325604U CN 220325604 U CN220325604 U CN 220325604U CN 202321543369 U CN202321543369 U CN 202321543369U CN 220325604 U CN220325604 U CN 220325604U
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Abstract
In the circuit, the output end of a single-channel Schmitt trigger buffer is connected in series with a second base resistor R1 and then connected with the base electrode of an NPN type triode Q3, on the other hand, the output end of the single-channel Schmitt trigger buffer is connected in series with a first base resistor R2 and a buffer inductor L1 and then connected with the base electrode of the NPN type triode Q1, the collector electrode of the NPN type triode Q1 is connected with the base electrode of the NPN type triode Q3, the emitters of the NPN type triodes Q1 and Q3 are grounded, the collector electrode of the NPN type triode Q3 is connected with the output end of a constant current source circuit, the two input ends of a comparator are respectively connected with the collector electrode of the NPN type triode Q and the adjustable input voltage, one end of a storage capacitor C2 is grounded, and the other end of the storage capacitor C2 is connected between the collector electrode of the NPN type triode Q3 and the comparator, and the output end of the comparator serves as the output end of the continuously adjustable triggerable pulse generating circuit. The utility model realizes continuous adjustment of pulse width, has simple circuit, easy realization and low realization cost.
Description
Technical Field
The present utility model relates to the field of pulse generating circuits, and more particularly to a continuously adjustable triggerable pulse generating circuit.
Background
Rectangular pulse generating circuits with adjustable width, amplitude and repetition frequency can be used for testing transient response of linear systems or as analog signals for testing performance of radar, multiplex communication and other pulse digital systems, and therefore continuous improvement of the pulse generating circuits is needed to meet the use demands of continuous progress in technology.
Disclosure of Invention
The utility model aims to design a novel pulse generating circuit with continuously adjustable pulse width, and simultaneously meets the design requirements of simple circuit and low cost.
The utility model discloses a continuously adjustable triggerable pulse generating circuit which comprises a single-channel Schmidt trigger buffer, an NPN triode Q1, an NPN triode Q3, a first base resistor R2, a buffer inductor L1, a second base resistor R1, a constant current source circuit, a storage capacitor C2 and a comparator, wherein the single-channel Schmidt trigger buffer is connected with the NPN triode Q3;
the output end of the single-channel Schmitt trigger buffer is connected with the base electrode of an NPN type triode Q3 after being connected with a second base electrode resistor R1 in series, the output end of the single-channel Schmitt trigger buffer is connected with the base electrode of the NPN type triode Q3 after being connected with a first base electrode resistor R2 and a buffer inductor L1 in series, the collector electrode of the NPN type triode Q1 is connected with the base electrode of the NPN type triode Q3, the emitters of the NPN type triodes Q1 and Q3 are grounded, the collector electrode of the NPN type triode Q3 is connected with the output end of a constant current source circuit, two input ends of a comparator are respectively connected with the collector electrode of the NPN type triode Q and adjustable input voltage, one end of a storage capacitor C2 is grounded, the other end of the storage capacitor C2 is connected between the collector electrode of the NPN type triode Q3 and the comparator, and the output end of the comparator is used as the output end of the continuously adjustable triggerable pulse generating circuit.
In the continuously adjustable triggerable pulse generating circuit, the single-channel Schmidt trigger buffer is realized by adopting the SN74LVC1G17DCKT, the 2 nd pin of the N74LVC1G17DCKT is connected with the active crystal oscillator, the 3 rd pin and the 5 th pin are respectively grounded and positive power supply, and the 4 th pin is the output end of the single-channel Schmidt trigger buffer.
In the continuously adjustable triggerable pulse generating circuit, the 1 st pin of the active crystal oscillator model S7D2.000000A20f30T, S7D2.000000A20f30T is connected with a resistor R6 of 100KΩ in series and then is connected with a positive power supply, the 2 nd pin and the 4 nd pin of S7D2.000000A20f30T are respectively grounded and connected with the positive power supply, and the 1 st pin of S7D2.000000A20f30T is connected with the 2 nd pin of SN74LVC1G17 DCKT.
In the continuously adjustable triggerable pulse generating circuit, the model of the NPN triode Q1 and the model of the NPN triode Q3 are 2SC4713K, the first base resistor R2 is 330 omega, the second base resistor R1 is 50 omega, and the buffer inductance L1 is 220mH.
In the continuously adjustable triggerable pulse generating circuit, the constant current source circuit comprises an NPN triode Q2, a resistor R3, a resistor R4 and a chip TLC431_C963380, wherein a collector of the NPN triode Q2 is connected with a working positive power supply, two ends of the resistor R3 are respectively connected with a base electrode and a collector of the NPN triode Q2, a 1 st pin of the TLC431_C963380 is connected with an emitter electrode of the NPN triode Q2 of the TLC431_C963380, a2 nd pin of the TLC431_C963380 is connected with a base electrode of the NPN triode Q2, a resistor R4 is connected between 1 st pin and 3 rd pin of the TLC431_C963380, and an output end of the constant current source circuit is led out from the 3 rd pin of the TLC431_C 963380.
In the continuously adjustable triggerable pulse generating circuit, the model of the NPN triode Q2 is 2SC4713K, the resistor R3 is 10KΩ, the working positive power supply is 10V, and the resistor R4 is 33 ohms.
In the continuously adjustable triggerable pulse generating circuit, a clamping diode is further arranged between the storage capacitor C2 and the NPN triode Q3, and the model of the clamping diode is BZT52.C3V3X.
In the continuously adjustable triggerable pulse generating circuit of the present utility model, the storage capacitor C2 is 1.5nF.
In the continuously adjustable triggerable pulse generating circuit, the comparator is realized by adopting a TLV3501AIDR, a2 nd pin of the TLV3501AIDR is connected with the other end of the storage capacitor C2, a 3 rd pin of the TLV3501AIDR is connected with a movable end of a potentiometer RV1, one fixed end of the potentiometer RV1 is connected with a positive voltage, and the other fixed end of the potentiometer RV1 is grounded.
The continuously adjustable triggerable pulse generating circuit charges the storage capacitor through the constant current source circuit, then releases the electric quantity stored in the storage capacitor through a switch formed by NPN type triodes Q1 and Q3, and the like, simultaneously, the switch is operated to be closed through the generated narrow pulse width signal, the voltage at two ends of the storage capacitor can be quickly released due to the short time of the switch opening caused by the narrow pulse width factor, so that the voltage at two ends of the storage capacitor is reduced, then the constant current source circuit charges the storage capacitor, the voltage of the storage capacitor is again stably increased after being released, the original voltage value is recovered, the voltage signals at two ends of the storage capacitor also form sawtooth wave signals, then the needed continuously adjustable pulse signals are generated through comparison of the comparator and other input signals, and the pulse width of the output circuit can be adjusted through adjusting the voltage values of other input signals. The utility model realizes continuous adjustment of pulse width, has simple circuit, easy realization and low realization cost.
Drawings
The utility model will be further described with reference to the accompanying drawings and examples, in which:
FIG. 1 is a schematic diagram of one embodiment of a continuously adjustable triggerable pulse generation circuit of the present utility model;
fig. 2 is a signal schematic diagram of the operation of the continuously adjustable triggerable pulse generating circuit of the present utility model.
Detailed Description
For a clearer understanding of technical features, objects and effects of the present utility model, a detailed description of embodiments of the present utility model will be made with reference to the accompanying drawings.
Referring to fig. 1, the continuously adjustable triggerable pulse generating circuit of the present utility model includes a single-channel schmitt trigger buffer, an NPN transistor Q1, an NPN transistor Q3, a first base resistor R2, a buffer inductance L1, a second base resistor R1, a constant current source circuit, a storage capacitor C2, and a comparator.
The output end of the single-channel Schmitt trigger buffer is connected with the base electrode of an NPN type triode Q3 after being connected with a second base electrode resistor R1 in series, the output end of the single-channel Schmitt trigger buffer is connected with the base electrode of the NPN type triode Q3 after being connected with a first base electrode resistor R2 and a buffer inductor L1 in series, the collector electrode of the NPN type triode Q1 is connected with the base electrode of the NPN type triode Q3, the emitters of the NPN type triodes Q1 and Q3 are grounded, the collector electrode of the NPN type triode Q3 is connected with the output end of a constant current source circuit, two input ends of a comparator are respectively connected with the collector electrode of the NPN type triode Q and adjustable input voltage, one end of a storage capacitor C2 is grounded, the other end of the storage capacitor C2 is connected between the collector electrode of the NPN type triode Q3 and the comparator, and the output end of the comparator is used as the output end of the continuously adjustable triggerable pulse generating circuit. The model of NPN triode Q1 and NPN triode Q3 is 2SC4713K, the first base resistor R2 is 330 omega, the second base resistor R1 is 50 omega, the buffer inductance L1 is 220mH, and the storage capacitor C2 is preferably 1.5nF.
In this embodiment, a filter capacitor C47 is further disposed between the buffer inductor L1 and the base of the NPN transistor Q1, where the filter capacitor C47 is 47pF, so as to filter out high frequency noise in the signal.
The single-channel Schmidt trigger buffer is realized by adopting SN74LVC1G17DCKT, the 2 nd pin of N74LVC1G17DCKT is connected with the active crystal oscillator, the 3 rd pin and the 5 th pin are respectively grounded and positive power supply, and the 4 th pin is the output end of the single-channel Schmidt trigger buffer. The 1 st pin of the active crystal oscillator model S7D2.000000A20f30T, S7D2.000000A20f30T is connected with a resistor R6 of 100KΩ in series and then is connected with a positive power supply, the 2 nd pin and the 4 nd pin of S7D2.000000A20f30T are respectively grounded and connected with the positive power supply, the 1 st pin of S7D2.000000A20f30T is connected with the 2 nd pin of SN74LVC1G17DCKT, and the 3 rd pin of S7D2.000000A20f30T outputs a 2MHz clock signal so as to be provided for a single-channel Schmidt trigger buffer for use.
The working principle of the utility model is as follows: the single-channel schmitt trigger buffer outputs a PWM signal, when the PWM signal is in a low level, the NPN type triodes Q1 and Q3 are both cut off, the constant current source circuit continuously charges the storage capacitor C2, when the PWM signal is in a high level, due to the delay effect of the inductor, the NPN type triode Q1 is cut off and the NPN type triode Q3 is conducted in the delay time, at the moment, the storage capacitor C2 discharges to the ground through the NPN type triode Q3, the voltage on the storage capacitor C2 is reduced, after the delay time, the NPN type triodes Q1 and Q3 are both cut off, the constant current source circuit continuously charges the storage capacitor C2, and the switching on are controlled by forming a narrow pulse width signal. In the whole process, the voltage signals at two ends of the storage capacitor C2 form sawtooth wave signals, then the sawtooth wave signals are compared with other input signals through a comparator to generate required continuous adjustable pulse signals, and the voltage values of other input signals are adjusted to adjust the pulse width of the output circuit, and the specific reference can be made to fig. 2.
In an embodiment, the constant current source circuit includes an NPN triode Q2, a resistor R3, a resistor R4, and a chip TLC431_c963380, a collector of the NPN triode Q2 is connected to a positive power supply, two ends of the resistor R3 are respectively connected to a base and a collector of the NPN triode Q2, a 1 st pin of the TLC431_c963380 is connected to an emitter of the NPN triode Q2 of the TLC431_c963380, a2 nd pin of the TLC431_c963380 is connected to the base of the NPN triode Q2, the resistor R4 is connected between the 1 st and 3 rd pins of the TLC431_c963380, and an output end of the constant current source circuit is led out from the 3 rd pin of the TLC431_c 963380. The model of the NPN triode Q2 is 2SC4713K, the resistor R3 is 10KΩ, the working positive power supply is 10V, and the resistor R4 is 33 ohms. The 1 st pin of TLC431_C963380 is 2.5V, so the output current of the constant current source circuit is 2.5V/R4.
In another embodiment of the present utility model, a clamping diode is further disposed between the storage capacitor C2 and the NPN transistor Q3, and the clamping diode is of the type bz52.c3v3x, which prevents the output voltage from being excessively high beyond 3.3V.
The comparator is realized by adopting a TLV3501AIDR, a2 nd pin of the TLV3501AIDR is connected with the other end of the storage capacitor C2, a 3 rd pin of the TLV3501AIDR is connected with a movable end of a potentiometer RV1, one fixed end of the potentiometer RV1 is connected with a positive voltage, and the other fixed end is grounded. The input voltage on the 3 rd pin of the LV3501AIDR can be regulated through the potentiometer, and meanwhile, the 3 rd pin of the LV3501AIDR is connected with a capacitor C9, C9 is 0.1 mu F, and the capacitor C9 is used for keeping the voltage division signal stable.
The continuously adjustable triggerable pulse generating circuit charges the storage capacitor through the constant current source circuit, then releases the electric quantity stored in the storage capacitor through a switch formed by NPN type triodes Q1 and Q3, and the like, simultaneously, the switch is operated to be closed through the generated narrow pulse width signal, the voltage at two ends of the storage capacitor can be quickly released due to the short time of the switch opening caused by the narrow pulse width factor, so that the voltage at two ends of the storage capacitor is reduced, then the constant current source circuit charges the storage capacitor, the voltage of the storage capacitor is again stably increased after being released, the original voltage value is recovered, the voltage signals at two ends of the storage capacitor also form sawtooth wave signals, then the needed continuously adjustable pulse signals are generated through comparison of the comparator and other input signals, and the pulse width of the output circuit can be adjusted through adjusting the voltage values of other input signals. The utility model realizes continuous adjustment of pulse width, has simple circuit, easy realization and low realization cost.
The embodiments of the present utility model have been described above with reference to the accompanying drawings, but the present utility model is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present utility model and the scope of the claims, which are to be protected by the present utility model.
Claims (10)
1. A continuously adjustable triggerable pulse generating circuit comprising: the device comprises a single-way Schmidt trigger buffer, an NPN triode Q1, an NPN triode Q3, a first base resistor R2, a buffer inductor L1, a second base resistor R1, a constant current source circuit, a storage capacitor C2 and a comparator;
the output end of the single-channel Schmitt trigger buffer is connected with the base electrode of an NPN type triode Q3 after being connected with a second base electrode resistor R1 in series, the output end of the single-channel Schmitt trigger buffer is connected with the base electrode of the NPN type triode Q3 after being connected with a first base electrode resistor R2 and a buffer inductor L1 in series, the collector electrode of the NPN type triode Q1 is connected with the base electrode of the NPN type triode Q3, the emitters of the NPN type triodes Q1 and Q3 are grounded, the collector electrode of the NPN type triode Q3 is connected with the output end of a constant current source circuit, two input ends of a comparator are respectively connected with the collector electrode of the NPN type triode Q and adjustable input voltage, one end of a storage capacitor C2 is grounded, the other end of the storage capacitor C2 is connected between the collector electrode of the NPN type triode Q3 and the comparator, and the output end of the comparator is used as the output end of the continuously adjustable triggerable pulse generating circuit.
2. The continuously adjustable triggerable pulse generating circuit according to claim 1, wherein the single-channel schmitt trigger buffer is implemented by SN74LVC1G17DCKT, pin 2 of N74LVC1G17DCKT is connected to an active crystal oscillator, pins 3 and 5 are respectively grounded and powered positively, and pin 4 is an output end of the single-channel schmitt trigger buffer.
3. The continuously adjustable triggerable pulse generating circuit according to claim 2, wherein the 1 st pin of the active crystal oscillator model S7D2.000000A20f30T, S7D2.000000A20f30T is connected in series with a resistor R6 of 100kΩ and then connected to a positive power supply, the 2 nd and 4 nd pins of s7d2.000000a20f30t are respectively grounded and connected to the positive power supply, and the 1 st pin of s7d2.000000a20f30t is connected to the 2 nd pin of SN74LVC1G17 DCKT.
4. The continuously adjustable triggerable pulse generating circuit according to claim 1, wherein the NPN transistors Q1, Q3 are 2SC4713K, the first base resistor R2 is 330 Ω, the second base resistor R1 is 50 Ω, and the buffer inductance L1 is 220mH.
5. The continuously adjustable triggerable pulse generating circuit according to claim 1, wherein the constant current source circuit comprises an NPN type triode Q2, a resistor R3, a resistor R4 and a chip TLC431_c963380, a collector of the NPN type triode Q2 is connected with a positive power supply, two ends of the resistor R3 are respectively connected with a base and a collector of the NPN type triode Q2, a 1 st pin of the TLC431_c963380 is connected with an emitter of the NPN type triode Q2 of the TLC431_c963380, a2 nd pin of the TLC431_c963380 is connected with a base of the NPN type triode Q2, a resistor R4 is connected between 1 st and 3 rd pins of the TLC431_c963380, and an output end of the constant current source circuit is led out from the 3 rd pin of the TLC431_c 963380.
6. The continuously adjustable triggerable pulse generator circuit according to claim 5, wherein said NPN transistor Q2 is model 2SC4713K, resistor R3 is 10kΩ, said positive working power supply is 10V, and resistor R4 is 33 ohms.
7. The continuously adjustable triggerable pulse generating circuit according to claim 1, wherein a clamping diode is further arranged between the storage capacitor C2 and the NPN transistor Q3, and the clamping diode has a model bz52.c3v3x.
8. A continuously adjustable triggerable pulse generating circuit according to claim 1, wherein the storage capacitor C2 is 1.5nF.
9. The continuously adjustable triggerable pulse generating circuit according to claim 1, wherein the comparator is implemented by TLV3501AIDR, pin 2 of TLV3501AIDR is connected to the other end of storage capacitor C2, pin 3 of TLV3501AIDR is connected to a movable end of potentiometer RV1, one fixed end of potentiometer RV1 is connected to positive voltage, and the other fixed end is grounded.
10. The continuously adjustable triggerable pulse generating circuit according to claim 9, wherein the 3 rd pin of TLV3501AIDR is further connected to one end of a stabilizing capacitor C9, and the other end of the stabilizing capacitor C9 is grounded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321543369.8U CN220325604U (en) | 2023-06-15 | 2023-06-15 | Continuously adjustable triggerable pulse generating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321543369.8U CN220325604U (en) | 2023-06-15 | 2023-06-15 | Continuously adjustable triggerable pulse generating circuit |
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| Publication Number | Publication Date |
|---|---|
| CN220325604U true CN220325604U (en) | 2024-01-09 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202321543369.8U Active CN220325604U (en) | 2023-06-15 | 2023-06-15 | Continuously adjustable triggerable pulse generating circuit |
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| CN (1) | CN220325604U (en) |
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2023
- 2023-06-15 CN CN202321543369.8U patent/CN220325604U/en active Active
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