CN220290077U - Multipath mutation signal detection tracking device - Google Patents

Abstract

The utility model discloses a multipath abrupt change signal detection tracking device, which comprises a program-controlled attenuation amplifier, a high-speed A/D converter, a FIFO memory, a clock circuit, an MCU1 control circuit and an MCU2 display processing circuit, wherein the program-controlled attenuation amplifier is connected with the high-speed A/D converter; the program-controlled attenuation amplifier, the high-speed A/D converter, the FIFO memory and the MCU2 display processing circuit are sequentially connected through electrical signals; the MCU1 control circuit is electrically connected with the program-controlled attenuation amplifier and the MCU2 display processing circuit; the MCU1 control circuit is electrically connected with the high-speed A/D converter and the FIFO memory through the clock circuit. The method and the device have the advantages that through the arrangement of the whole set of multipath mutation signal detection tracking circuit, the interference of noise and other factors can be reduced while more useful information of signals can be acquired in a complex environment, the reliability of a system is enhanced, and meanwhile, the cost of equipment can be effectively reduced.

Description

Multipath mutation signal detection tracking device

Technical Field

The utility model relates to the technical field of measuring instruments, in particular to a method for detecting and tracking multipath mutation signals in a complex competition field environment.

Background

Because the free combat competition field environment is complex and changeable, the existing signal detection equipment is insufficient to meet the competition field environment requirement. If the bandwidth of the signal detection device is higher, more noise is detected while the signal is collected, and the sensitivity of the low-performance detection device is lower, and the useful information of more signals can be missed while part of noise is ignored, so that the accurate and effective analysis cannot be performed.

Disclosure of Invention

The utility model aims to provide a multipath mutation signal detection tracking device, which can effectively improve the accuracy of sampling signals and detect the mutation of the signals more accurately.

In order to achieve the above purpose, the present utility model provides the following technical solutions: a multipath abrupt signal detection tracking device comprises a program-controlled attenuation amplifier, a high-speed A/D converter, a FIFO memory, a clock circuit, an MCU1 control circuit and an MCU2 display processing circuit;

the program-controlled attenuation amplifier, the high-speed A/D converter, the FIFO memory and the MCU2 display processing circuit are sequentially connected through electrical signals; the MCU1 control circuit is electrically connected with the program-controlled attenuation amplifier and the MCU2 display processing circuit; the MCU1 control circuit is electrically connected with the high-speed A/D converter and the FIFO memory through the clock circuit.

Compared with the prior art, the utility model has the beneficial effects that:

the method and the device have the advantages that through the arrangement of the whole set of multipath mutation signal detection tracking circuit, the interference of noise and other factors can be reduced while more useful information of the signals can be acquired in a complex free combat competition field environment, the reliability of a system is enhanced, and the equipment cost can be effectively reduced.

Drawings

Fig. 1 is a functional block diagram of a signal detection device according to the present utility model.

FIG. 2 is a schematic diagram of a programmable attenuation amplifier according to the present utility model.

Fig. 3 is a circuit diagram of the high-speed AD conversion and FIFO according to the present utility model.

Fig. 4 is a clock circuit diagram of the present utility model.

Fig. 5 is a circuit diagram of the display processing of the MCU2 according to the present utility model.

Fig. 6 is a control circuit diagram of the MCU1 of the present utility model.

1. A program controlled attenuation amplifier; 2. a high-speed a/D converter; 3. a FIFO memory; 4. a clock circuit; 5. MCU1 control circuit; 6. MCU2 displays the processing circuit; 7. and a shaping circuit.

Detailed Description

The following description of the embodiments of the present utility model will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present utility model, but not all embodiments. Based on the embodiments of the present utility model, those of ordinary skill in the art may obtain other embodiments without making any inventive effort, which fall within the scope of the present utility model.

Referring to fig. 1-6, the present utility model provides a technical solution: a multipath abrupt signal detection tracking device comprises a program-controlled attenuation amplifier 1, a high-speed A/D converter 2, a FIFO memory 3, a clock circuit 4, an MCU1 control circuit 5 and an MCU2 display processing circuit 6. The program-controlled attenuation amplifier 1 is electrically connected with a signal input end, the MCU1 control circuit 5 is electrically connected with a key input end, and the MCU2 display processing circuit 6 is electrically connected with a display.

The program-controlled attenuation amplifier 1, the high-speed A/D converter 2, the FIFO memory 3 and the MCU2 display processing circuit 6 are sequentially connected through electric signals; the MCU1 control circuit 5 is electrically connected with the program-controlled attenuation amplifier 1 and the MCU2 display processing circuit 6; the MCU1 control circuit 5 is electrically connected with the high-speed A/D converter 2 and the FIFO memory 3 through the clock circuit 4. The program-controlled attenuation amplifier 1 is electrically connected with the MCU1 control circuit 5 through the shaping circuit 7.

The program-controlled attenuation amplifier 1 is an LM6172 high-speed operational amplification chip; the high-speed A/D converter 2 is an ADS830E chip or a 74LVC574 latch chip; the FIFO memory 3 is an IDT7204 memory chip; the clock circuit 4 adopts a 74F74, a 74LS390 or a 74F151 chip; the MCU1 control circuit 5 is a 2K1000LA chip, and the MCU2 display processing circuit 6 is an FPGA.

Pins 1, 2, 3, 4 and 5 in the program-controlled attenuation amplifier 1 are connected with pins 10, 12, 14, 16 and 31 of the MCU1 control circuit 5, pins 10, 11, 13, 14, 19, 20, 21 and 22 of the FIFO memory 3 are respectively connected with pins 2, 4, 6, 8, 10, 12, 14 and 16 of the MCU2 display processing circuit 6, and the MCU1 control circuit 5 is connected with the MCU2 display processing circuit 6 through an SPI bus.

The device adopts devices such as a 64-bit microprocessor Loongson 2K1000LA, a high-speed A/D converter ADS830 and the like on hardware, and a Loongnix real-time operating system is installed on software, so that programming is simplified, and the efficiency and stability of the system are improved. The input signal is accessed from the passive probe of the system, firstly passes through the input circuit, then passes through the signal conditioning circuit, the conditioned signal is then converted into a digital signal by the A/D converter, then passes through the cache FIFO, the signal data is transmitted into the FPGA, the FPGA finishes the processing of the signal data, finally the waveform is restored to the display screen, the technical indexes such as the frequency, the voltage and the like of the signal are displayed, and the screen can be adjusted in real time through the key selection mode.

Working principle: the program-controlled amplifying circuit attenuates or amplifies the input signal, and the output signal is within the input voltage requirement range of the AD converter. As shown in fig. 2, the signal to be measured is input from the BNC jack, the S0 relay determines the input coupling mode, the S0 actuation is the dc coupling mode, and the S0 disconnection is the ac coupling mode. The signal is sent into an attenuation circuit of X0.5/X0.05 composed of R12R 15R 17 and C3C 4C 5 after passing through an AC-DC coupling selection switch, the attenuation multiple is controlled by S1, when S1 is not absorbed, the signal is connected to the 0 end, the corresponding attenuation is counted as that when S1The suction is connected with the 1 end, and the corresponding attenuation is counted as +.>C2, C3 compensate for the high frequency signal. The attenuated signal is fed into buffer formed from high-speed operational amplifier U1A, then fed into inverting amplification circuit formed from U1B, and its amplification factor is defined by S2 and S3, the corresponding magnification is +.>When S2 is sucked and S3 is not sucked, the corresponding magnification is +.> S3 is not considered when S2 is attracted, but S2 is disconnected to reduce power consumption, and the corresponding magnification is +.>The output signal is selected by S4 to be amplified by an in-phase amplifier composed of U2A, when S4 is not sucked, the signal is amplified without in-phase amplification, when S4 is sucked>The signal is sent to an inverting amplifier with the amplification factor of-1 times composed of U2B to eliminate the negative sign brought by the inverting amplifier of the first stage, and meanwhile, the inverted base line voltage sent by U3A is added on the detected signal as the input midpoint voltage of the AD converter after being inverted by U2B and sent to the AD converter.

The power supply in the oscilloscope circuit is divided into a digital part and an analog part. In order to avoid mutual interference, the power supply of the digital part and the power supply of the analog part are separated, and are isolated by independent voltage stabilizing circuits and filters made of inductors and capacitors. The digital part requires a single +5V power supply, which is regulated by an LM7805 to an 8V supply voltage. The analog part is mainly an analog input circuit of a program controlled amplifier circuit and an AD converter, the program controlled amplifier circuit needs + -5V dual power supply, the analog part of the AD converter circuit needs +5V single power supply, +5V voltage is obtained by stabilizing 8V power supply voltage by LM317T, the +8V voltage is converted into about-8.3V by a DC/DC chip MC34063, the DC/DC output voltage is determined by R30 and R31,

the negative voltage output is stabilized by a negative voltage stabilizing chip LM337 to obtain-5V, and in order to avoid interference of a DC/DC circuit to other circuits, an input end and an output end of the negative voltage are respectively connected in series with L4 and L5 for isolation, and an energy storage inductor L3 selects an inductor with shielding in a magnetic tank packaging process when an element is selected, so that interference is minimized.

The signal regulated by the program-controlled amplifying circuit is divided into two paths, one path enters the AD converting circuit for sampling, and the sampled data is latched and buffered by the 74LVC574 and then sent into the FIFO memory. The FIFO is added between the AD converter and the MCU2 to perform a high-speed data buffering function, and the FIFO and the AD converter are made to operate synchronously to store the converted output data of the AD converter because the highest operating frequency of the AD converter is 60MHz far higher than the operating frequency of the MCU 2. The FIFO memory has 3 flag bit pins, respectively FF (full flag): the flag is set when the memory is full, at which point the memory ignores any write data operations. HF (half full flag): the flag is set when the memory is half full. EF (null flag): this flag is set when the memory is read empty, at which time the memory ignores all read data operations. In the circuit, only the FF mark of the chip is connected with the MCU2, when the FIFO memory is full, the FF pin is pulled high to inform the MCU2 to read data, at the moment, the MCU2 prohibits the clocks of the AD converter and the FIFO memory, the control right of the FIFO is given to the MCU2, when the MCU2 finishes reading data and completes software triggering, the clocks of the AD converter and the FIFO memory are enabled to continuously read new data, and meanwhile, the MCU2 processes and displays the read data.

The clock generation circuit provides a series of sampling clock signals for the AD converter, namely 600Hz, 6kHz, 60kHz, 600kHz, 3MHz, 6MHz, 30MHz and 60MHz, 8 types of sampling clock signals are respectively corresponding to different horizontal scanning speeds, the sampling clock signals are controlled by the MCU1, the reference clock signals are provided by a 60MHz temperature compensation type active crystal module, one path of the output 60MHz signals is directly used as a 60MHz sampling clock to be sent to the multiplexer 74F151, the other path of the output 60MHz signals is sent to a 2 frequency divider consisting of 74F74 triggers for frequency division, the obtained 30MHz signals are divided into two paths, one path of the output 60MHz signals are sent to the multiplexer 74F151, the other path of the output 60MHz signals are sent to a 5 frequency divider consisting of 2-5-10 frequency dividers 74LS390 for frequency division, the obtained 6MHz signals are divided into two paths, one path of output 60MHz signals are continuously divided, and the other path of output 60MHz signals are sent to the multiplexer 74F151, and the latter several stages of frequency division are the same as above. The first divide by two of the 60MHz signal does not use the 2 divider in 74LS390, but instead uses a single piece of 74F74, because the highest input frequency of the divider in 74LS390 is 40MHz, and therefore a single stage of divider is used in front of it. All 8 clock signals are fed to the multiplexer, and the MUC1 selects a desired sampling frequency by controlling three strobe signal lines S0, S1, S2 of 74F 151.

Claims (5)

1. A multipath mutation signal detection tracking device is characterized in that: the device comprises a program-controlled attenuation amplifier (1), a high-speed A/D converter (2), a FIFO memory (3), a clock circuit (4), an MCU1 control circuit (5) and an MCU2 display processing circuit (6);

the program-controlled attenuation amplifier (1), the high-speed A/D converter (2), the FIFO memory (3) and the MCU2 display processing circuit (6) are sequentially connected through electric signals; the MCU1 control circuit (5) is electrically connected with the program-controlled attenuation amplifier (1) and the MCU2 display processing circuit (6); the MCU1 control circuit (5) is electrically connected with the high-speed A/D converter (2) and the FIFO memory (3) through the clock circuit (4).

2. The multiple mutation signal detection tracking device of claim 1, wherein: the program-controlled attenuation amplifier (1) is electrically connected with the MCU1 control circuit (5) through the shaping circuit (7).

3. The multiple mutation signal detection tracking device of claim 1, wherein: the program-controlled attenuation amplifier (1) is an LM6172 high-speed operational amplification chip; the high-speed A/D converter (2) is an ADS830E chip or a 74LVC574 latch chip; the FIFO memory (3) is an IDT7204 memory chip; the clock circuit (4) adopts a 74F74, a 74LS390 or a 74F151 chip; the MCU1 control circuit (5) is a 2K1000LA chip, and the MCU2 display processing circuit (6) is an FPGA.

4. The multi-path mutation signal detecting and tracking device according to claim 3, wherein: pins 1, 2, 3, 4 and 5 in the program-controlled attenuation amplifier (1) are connected with pins 10, 12, 14, 16 and 31 of the MCU1 control circuit (5), pins 10, 11, 13, 14, 19, 20, 21 and 22 of the FIFO memory (3) are respectively connected with pins 2, 4, 6, 8, 10, 12, 14 and 16 of the MCU2 display processing circuit (6), and the MCU1 control circuit (5) is connected with the MCU2 display processing circuit (6) through an SPI bus.

5. The multiple mutation signal detection tracking device of claim 1, wherein: the MCU1 control circuit (5) is electrically connected with the key input end; the MCU2 display processing circuit (6) is electrically connected with a display; the program-controlled attenuation amplifier (1) is electrically connected with the signal input end.