CN220273657U - Signal holding circuit and low power consumption device - Google Patents
Signal holding circuit and low power consumption device Download PDFInfo
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- CN220273657U CN220273657U CN202321725324.2U CN202321725324U CN220273657U CN 220273657 U CN220273657 U CN 220273657U CN 202321725324 U CN202321725324 U CN 202321725324U CN 220273657 U CN220273657 U CN 220273657U
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- 230000008054 signal transmission Effects 0.000 claims abstract description 32
- 238000000034 method Methods 0.000 claims abstract description 13
- 239000003990 capacitor Substances 0.000 claims description 30
- 230000001960 triggered effect Effects 0.000 claims description 13
- 238000007599 discharging Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 6
- 238000001514 detection method Methods 0.000 description 4
- 238000003708 edge detection Methods 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
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- 239000002184 metal Substances 0.000 description 1
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Abstract
The utility model discloses a signal holding circuit and low-power consumption equipment, wherein the signal holding circuit comprises a signal receiving end and an interrupt signal holding circuit, the signal receiving end is used for being connected with a tact switch, the signal receiving end is also connected with a wake-up signal access end of a controller, an input end of the interrupt signal holding circuit is connected with the signal receiving end, and an output end of the interrupt signal holding circuit is connected with a signal transmission end of the controller. The utility model receives the trigger signal output by the tact switch through the signal receiving end so as to wake up the controller, and outputs the trigger signal to the interrupt signal holding circuit, and the interrupt signal holding circuit outputs the trigger signal to the controller after being waken up after holding the trigger signal so as to enable the controller to process the trigger signal, so that the controller can accurately recognize that the tact switch is pressed down after being waken up, and the controller can accurately control the low-power-consumption equipment.
Description
Technical Field
The present utility model relates to the field of interrupt signal holding technologies, and in particular, to a signal holding circuit and a low power device.
Background
In the conventional GPIO signal detection scheme, a tact switch signal is directly connected to an IO port of an MCU, and when the tact switch is disconnected, the IO signal is in a high level; when the tact switch is closed, the IO signal becomes low level, and the MCU can recognize that the tact switch is pressed through edge detection or low level detection.
However, the time for which the tact switch is pressed is very short, and for low-power-consumption products, the MCU is in a dormant state for most of the time, when the duration of the pressing of the tact switch is shorter than the initialization time after the MCU is awakened, the switch signal is lost after the MCU is successfully initialized, and the MCU cannot normally recognize the switch signal, namely the problem that the pressing of the tact switch cannot be accurately recognized after the MCU is initialized exists.
Disclosure of Invention
The utility model mainly aims to provide a signal holding circuit, which aims to solve the problem that a touch switch is pressed down in a short time and cannot be accurately identified after a controller in low-power-consumption equipment is initialized.
In order to achieve the above object, the present utility model proposes a signal holding circuit applied to a low power consumption device including a tact switch for outputting a trigger signal when triggered and a controller, the signal holding circuit comprising:
the signal receiving end is used for accessing the tact switch, is also connected with the wake-up signal access end of the controller, and is used for receiving a trigger signal output by the tact switch so as to wake up the controller and output the trigger signal;
the input end of the interrupt signal holding circuit is connected with the signal receiving end, and the output end of the interrupt signal holding circuit is connected with the signal transmission end of the controller; the interrupt signal holding circuit is used for holding the accessed trigger signal and then outputting the trigger signal to the controller after being awakened so that the controller processes the trigger signal.
In an embodiment, the interrupt signal holding circuit includes a delay circuit, a first end of the delay circuit is connected to the signal receiving end, a second end of the delay circuit is connected to the signal transmitting end of the controller, and the delay circuit is configured to delay the trigger signal, so as to perform signal holding on the trigger signal and output the trigger signal.
In an embodiment, the delay circuit includes a first capacitor and a first resistor, a first end of the first capacitor connected in parallel with the first resistor is connected to the signal receiving end, a first end of the first capacitor connected in parallel with the first resistor is also connected to the signal transmitting end of the controller, and a second end of the first capacitor connected in parallel with the first resistor is grounded.
In an embodiment, the interrupt signal holding circuit further includes a first switch circuit, a controlled end of the first switch circuit is connected to a second end of the delay circuit, a first end of the first switch circuit is connected to a signal transmission end of the controller, a first end of the first switch circuit is further connected to a power supply, a second end of the first switch circuit is grounded, and the first switch circuit is configured to be turned on when receiving a trigger signal output by the delay circuit, so as to output the trigger signal to the controller.
In an embodiment, the first switching circuit includes a second resistor and a first switching tube, a controlled end of the first switching tube is connected with a second end of the delay circuit, a first end of the first switching tube is connected with a signal transmission end of the controller through the second resistor, and a second end of the first switching tube is grounded.
In an embodiment, the interrupt signal holding circuit further includes a discharging circuit, one end of the discharging circuit is connected to the second end of the delay circuit, and the other end of the discharging circuit is connected to the signal transmission end of the controller.
In an embodiment, the discharging circuit includes a third resistor and a second switching tube, a controlled end of the second switching tube is connected with the controller, a first end of the second switching tube is connected with the delay circuit through the third resistor, and a second end of the second switching tube is grounded.
In an embodiment, the signal holding circuit further includes an inverter, an input end of the inverter is connected to an output end of the tact switch, an output end of the inverter is connected to a wake-up signal access end of the controller, and the inverter is configured to invert a phase of the trigger signal and output the phase to the controller to wake up the controller.
In an embodiment, the inverter includes a third switching tube and a fourth resistor, a controlled end of the third switching tube is connected with an output end of the tact switch, a first end of the third switching tube is connected with a wake-up signal access end of the controller, the first end of the third switching tube is further connected with a power supply through the fourth resistor, and a second end of the third switching tube is grounded.
The utility model also provides low-power-consumption equipment which comprises the tact switch, the controller and the signal holding circuit, wherein one end of the signal holding circuit is connected with the output end of the tact switch, and the other end of the signal holding circuit is connected with the controller.
According to the technical scheme, the trigger signal output by the tact switch is received through the signal receiving end so as to wake up the controller, the trigger signal is output to the interrupt signal holding circuit, the interrupt signal holding circuit holds the trigger signal and then outputs the trigger signal to the awakened controller, so that the controller processes the trigger signal, and the controller can accurately recognize that the tact switch is pressed down after being awakened, so that the controller can accurately control the low-power-consumption equipment.
Drawings
In order to more clearly illustrate the embodiments of the present utility model or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are only some embodiments of the present utility model, and other drawings may be obtained according to the structures shown in these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a block diagram of an embodiment of a signal hold circuit of the present utility model;
FIG. 2 is a block diagram of another embodiment of a signal hold circuit according to the present utility model;
FIG. 3 is a circuit diagram of an interrupt signal hold circuit of the present utility model;
FIG. 4 is a timing diagram of an embodiment of an interrupt signal hold circuit of the present utility model;
FIG. 5 is a circuit diagram of an interrupt signal hold circuit of the present utility model;
FIG. 6 is a timing diagram of an interrupt signal hold circuit of the present utility model.
Reference numerals illustrate:
the achievement of the objects, functional features and advantages of the present utility model will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
The following description of the embodiments of the present utility model will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.
Furthermore, descriptions such as those referred to as "first," "second," and the like, are provided for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implying an order of magnitude of the indicated technical features in the present disclosure. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present utility model.
In the conventional GPIO signal detection scheme, the tact switch 10 is directly connected to the IO port of the MCU, namely when the tact switch 10 is disconnected, the IO signal is in a high level; when the tact switch 10 is closed, the IO signal becomes low level, and the MCU can recognize that the tact switch 10 is pressed by edge detection or low level detection. However, the time for which the tact switch 10 is pressed is very short, and for low power consumption products, the MCU is in a sleep state for most of the time, and when the duration of the pressing of the tact switch 10 is shorter than the initialization time after the MCU is awakened, the switch signal is lost after the MCU is initialized successfully, and the MCU cannot normally recognize the switch signal, that is, there is a problem that the MCU cannot accurately recognize that the tact switch 10 is pressed after the MCU is initialized.
In order to solve the above-described problems, the present utility model proposes a signal holding circuit 20 applied to a low power consumption device including a tact switch 10 and a controller 30, the tact switch 10 outputting a trigger signal when triggered.
Referring to fig. 1, in an embodiment of the present utility model, the signal holding circuit 20 includes:
the signal receiving end is used for accessing the tact switch 10, is also connected with the wake-up signal access end of the controller 30, and is used for receiving a trigger signal output by the tact switch 10 so as to wake-up the controller 30 and output the trigger signal;
an interrupt signal holding circuit 21, wherein an input end of the interrupt signal holding circuit 21 is connected with the signal receiving end, and an output end of the interrupt signal holding circuit 21 is connected with a signal transmission end of the controller 30; the interrupt signal holding circuit 21 is configured to hold the trigger signal, and then output the trigger signal to the controller 30 after being woken up, so that the controller 30 processes the trigger signal.
In this embodiment, the controller 30 may be implemented by a main controller, such as an MCU, a DSP (Digital Signal Process, digital signal processing Chip), an FPGA (Field Programmable Gate Array, programmable gate array Chip), an SOC (System On Chip), or the like. The tact switch 10 is a sensitive switch, that is, when the touch switch 10 is in use, the pressure is applied to the operation direction of the tact switch 10 under the condition of meeting the operation force, and the tact switch 10 is turned on; when the pressure is removed, the tact switch 10 is disconnected, and the internal structure is switched on and off by the stress change of the metal spring plate. It can be understood that when the tact switch 10 is pressed by a user, a trigger signal is output to wake up the controller 30, and the controller 30 after being woken up responds to the trigger signal and controls the low power consumption device to perform corresponding operation, so as to realize the control of the low power consumption device to operate through the tact switch 10.
In the present embodiment, the interrupt signal holding circuit 21 may be implemented by any interrupt signal holding circuit 21 that can hold a trigger signal, such as the delay circuit 211. It will be appreciated that the low power consumption device is in a sleep state under normal conditions, when the tact switch 10 is triggered by a user, the signal receiving end receives a trigger signal and outputs the trigger signal to the wake-up signal access end of the controller 30 to wake up the controller 30, so that the controller 30 starts to initialize, meanwhile, the interrupt signal holding circuit 21 performs signal holding on the accessed trigger signal, and after the controller 30 is awakened, i.e. after the initialization of the controller 30 is completed, the interrupt signal holding circuit 21 outputs the held trigger signal to the controller 30, so that the controller 30 processes the trigger signal. For the controller 30 without the interrupt function or insufficient interrupt pins, the trigger signal output when the tact switch 10 is triggered is used for waking up the controller 30 to start initialization, and meanwhile, the trigger signal is transmitted to the controller 30 after being waken up after being subjected to signal retention by the interrupt signal retaining circuit 21, so that the controller 30 can correctly recognize that the tact switch 10 is pressed after the initialization is completed.
According to the technical scheme of the utility model, the trigger signal output by the tact switch 10 is received through the signal receiving end so as to wake up the controller 30, the trigger signal is output to the interrupt signal holding circuit 21, the interrupt signal holding circuit 21 holds the trigger signal and then outputs the trigger signal to the awakened controller 30, so that the controller 30 processes the trigger signal, and the controller 30 can accurately recognize that the tact switch 10 is pressed down after being awakened, so that the controller 30 can accurately control the low-power-consumption equipment.
Referring to fig. 3 and 4, in an embodiment, the interrupt signal holding circuit 21 includes a delay circuit 211, a first end of the delay circuit 211 is connected to the signal receiving end, a second end of the delay circuit 211 is connected to the signal transmitting end of the controller 30, and the delay circuit 211 is configured to delay the trigger signal to perform signal holding on the trigger signal and output the trigger signal.
In this embodiment, the delay circuit 211 may be implemented by using any delay circuit 211 capable of delaying a trigger signal, and specifically, the delay circuit 211 includes a first capacitor C1 and a first resistor R1, a first end of the first capacitor C1 connected in parallel with the first resistor R1 is connected to the signal receiving end, a first end of the first capacitor C1 connected in parallel with the first resistor R1 is also connected to the signal transmitting end of the controller 30, and a second end of the first capacitor C1 connected in parallel with the first resistor R1 is grounded. The first capacitor C1 and the first resistor R1 are the RC delay circuit 211 for delaying the trigger signal, so as to maintain the trigger signal and output the trigger signal. The capacitance value of the first capacitor C1 needs to be determined according to practical situations, for example, the controller 30 has a shorter initialization time, i.e. a capacitor with a smaller capacitance value is selected; the controller 30 has a longer initialization time, i.e. a capacitor with a larger capacitance value can be selected, so that the controller 30 can accurately recognize that the tact switch 10 is pressed after initialization.
It can be understood that, in this embodiment, the controller 30 is triggered at a high level, and when the tact switch 10 is turned off and the signal transmission terminal inputs a low level, the low power consumption device is in a sleep state; when the tact switch 10 is pressed down, the tact switch 10 is closed to output a trigger signal, the controller 30 is awakened and initialized while the first capacitor C1 is charged, when the first capacitor C1 is instantly fully charged, the signal transmission end of the controller 30 inputs a high level, after the tact switch 10 is opened, the first capacitor C1 holds the trigger signal, that is, the signal transmission end of the controller 30 continuously inputs the high level, and after the initialization of the controller 30 is completed, the controller 30 reads the high level of the signal transmission end to process the trigger signal. T1 in fig. 4 is the time when the tact switch is pressed, T2 is the initialization time of the controller, and typically T2 is greater than T1; the WAKE signal is the level signal of the WAKE-up access terminal of the controller, and the IO signal is the level signal of the signal transmission terminal of the controller. In order not to affect the next use of the tact switch 10, the controller 30 may configure the signal transmission terminal to output a low level after reading the signal transmission terminal level, so as to discharge the first capacitor C1, and discharge the electric quantity in the first capacitor C1, so that the circuit 211 again performs signal retention on the trigger signal when the next tact switch 10 is triggered for a time delay.
Referring to fig. 5 and 6, in an embodiment, the interrupt signal holding circuit 21 further includes a first switch circuit 212, a controlled end of the first switch circuit 212 is connected to the second end of the delay circuit 211, a first end of the first switch circuit 212 is connected to a signal transmission end of the controller 30, a first end of the first switch circuit 212 is further connected to a power supply, a second end of the first switch circuit 212 is grounded, and the first switch circuit 212 is turned on when receiving a trigger signal output by the delay circuit 211, so as to output the trigger signal to the controller 30.
In this embodiment, the first switching circuit 212 may be implemented by using a switching tube such as a triode or a MOS tube, and specifically, the first switching circuit 212 includes a second resistor R2 and a first switching tube Q1, a controlled end of the first switching tube Q1 is connected to a second end of the delay circuit 211, a first end of the first switching tube Q1 is connected to the controller 30 through the second resistor R2, and a second end of the first switching tube Q1 is grounded. It can be understood that, in this embodiment, the controller 30 is triggered at a low level, when the tact switch 10 is turned off and the signal transmission terminal inputs a high level, the low power consumption device is in a sleep state, and the first switching tube Q1 is turned off; when the tact switch 10 is pressed down, the tact switch 10 is closed to output a trigger signal, the controller 30 is awakened and initialized, the first capacitor C1 is charged, when the first capacitor C1 is fully charged, the first switching tube Q1 is conducted, and the signal transmission end of the controller 30 inputs a low level; in the initialization process of the controller 30, if the signal transmission end is pulled up, the resistance value of the second resistor R2 can be adjusted to keep the signal transmission end at a low level, and if the signal transmission end is pulled down or in a high resistance state, no adjustment is needed, and the signal transmission end is kept at a low level continuously; after the initialization of the controller 30 is completed, the low level of the signal transmission terminal is read to process the trigger signal. The first end of the first switching tube Q1 is further connected in series with the fifth resistor R5 through the second resistor R2 and then connected to a power supply. In fig. 6, T1 is a time when the tact switch is pressed, T3 is a time when the first capacitor is fully charged, t2+t3 is an initialization time of the controller, and t2+t3 is generally greater than T1, and T3 is less than T1; the WAKE signal is the level signal of the WAKE-up access terminal of the controller, and the IO signal is the level signal of the signal transmission terminal of the controller.
Referring to fig. 5, in an embodiment, the interrupt signal holding circuit 21 further includes a discharging circuit 213, one end of the discharging circuit 213 is connected to the second end of the delay circuit 211, and the other end of the discharging circuit 213 is connected to the signal transmission end of the controller 30.
In this embodiment, after the controller 30 processes the trigger signal, it controls the discharging circuit 213 to operate, so that the second end of the delay circuit 211 is grounded to discharge the first capacitor C1 in the delay circuit 211, and the electric quantity in the first capacitor C1 is discharged, so that the circuit 211 is convenient to signal and hold the trigger signal again when the next tact switch 10 is triggered.
In this embodiment, the discharging circuit 213 includes a third resistor R3 and a second switching tube Q2, a controlled end of the second switching tube Q2 is connected to the controller 30, a first end of the second switching tube Q2 is connected to the delay circuit 211 through the third resistor R3, and a second end of the second switching tube Q2 is grounded.
It can be understood that the controller 30 is triggered at a low level, when the tact switch 10 is turned off and the signal transmission end inputs a high level, the second switching tube Q2 is turned on, and the low power consumption device is in a sleep state; when the tact switch 10 is pressed, the tact switch 10 is closed to output a trigger signal to wake up the controller 30; the signal receiving end outputs the trigger signal to the delay circuit 211 to charge the first capacitor C1, so that the interrupt signal holding circuit 21 holds the trigger signal, and the trigger signal can be correctly identified after the initialization of the controller 30 is completed; when the first capacitor C1 is fully charged, the first switching tube Q1 is turned on, the signal transmission end of the controller 30 is at a low level, the second switching tube Q2 is turned off, and when the controller 30 finishes initializing, the low level of the signal transmission end is read, so that the next use of the tact switch 10 is not affected, the controller 30 can configure the signal transmission end to output a high level, and turn on the second switching tube Q2, so that the first capacitor C1 discharges through the second switching tube Q2, the electric quantity in the first capacitor C1 is discharged, and the next time the tact switch 10 is triggered, the trigger signal is kept again.
Referring to fig. 2 and 3, in an embodiment, the signal holding circuit 20 further includes an inverter 22, an input terminal of the inverter 22 is connected to an output terminal of the tact switch 10, an output terminal of the inverter 22 is connected to a wake-up signal access terminal of the controller 30, and the inverter 22 is configured to invert a phase of the trigger signal and output the phase to the controller 30 to wake-up the controller 30.
In this embodiment, the inverter 22 may be implemented by any inverter 22 capable of inverting the phase of the trigger signal by 180 degrees, such as a TTL (Transistor-Transistor Logic) inverter 22, a CMOS (Complementary Metal Oxide Semiconductor ) inverter 22, and the like. Specifically, the inverter 22 includes a third switching tube Q3 and a fourth resistor R4, where a controlled end of the third switching tube Q3 is connected to an output end of the tact switch 10, a first end of the third switching tube Q3 is connected to an wake-up signal access end of the controller 30, a first end of the third switching tube Q3 is further connected to a power supply through the fourth resistor R4, and a second end of the third switching tube Q3 is grounded. It can be understood that in the present embodiment, the controller 30 wakes up at a low level, that is, when the trigger signal received by the wake-up access terminal of the controller 30 is at a low level, the controller 30 will be woken up, and therefore when the trigger signal outputted as a high level is triggered by the tact switch 10, the trigger signal is inverted through the inverter 22, that is, the trigger signal changing the high level trigger signal into the low level is outputted to the wake-up input terminal of the controller 30, so as to wake up the controller 30, and the controller 30 starts to initialize after being woken up, so as to meet different demands of the controller 30 for logic levels, and realize interrupt wake-up of the low power consumption device. Of course, in other embodiments, the controller 30 may also wake up at a high level, that is, when the trigger signal received by the wake-up access terminal of the controller 30 is at a high level, the controller 30 may wake up, and the inverter 22 does not need to be set for inversion at this time, which may be specifically set according to the actual application of the controller 30, which is not limited herein.
The utility model also proposes a low power consumption device comprising a tact switch 10 and a controller 30 and the signal holding circuit 20 described above; the specific structure of the signal holding circuit 20 refers to the above embodiment, and since the present low power device adopts all the technical solutions of all the embodiments, at least has all the beneficial effects brought by the technical solutions of the embodiments, and is not described in detail herein.
One end of the signal holding circuit 20 is connected to the output end of the tact switch 10, and the other end of the signal holding circuit 20 is connected to the controller 30. In this embodiment, when the tact switch 10 is triggered, the signal holding circuit 20 outputs the trigger signal to the controller 30 to wake up the controller 30 to start initialization, and performs signal holding on the trigger signal and outputs the trigger signal to the controller 30 after the initialization is completed, so that the controller 30 processes the trigger signal, and the circuit is simple and the cost is lower.
The foregoing description is only of the optional embodiments of the present utility model, and is not intended to limit the scope of the utility model, and all the equivalent structural changes made by the description of the present utility model and the accompanying drawings or the direct/indirect application in other related technical fields are included in the scope of the utility model.
Claims (10)
1. A signal holding circuit, characterized by being applied to a low power consumption device including a tact switch for outputting a trigger signal when triggered, and a controller, the signal holding circuit comprising:
the signal receiving end is used for accessing the tact switch, is also connected with the wake-up signal access end of the controller, and is used for receiving a trigger signal output by the tact switch so as to wake up the controller and output the trigger signal;
the input end of the interrupt signal holding circuit is connected with the signal receiving end, and the output end of the interrupt signal holding circuit is connected with the signal transmission end of the controller; the interrupt signal holding circuit is used for holding the accessed trigger signal and then outputting the trigger signal to the controller after being awakened so that the controller processes the trigger signal.
2. The signal hold circuit of claim 1, wherein the interrupt signal hold circuit comprises a delay circuit, a first end of the delay circuit is connected to the signal receiving end, a second end of the delay circuit is connected to the signal transmitting end of the controller, and the delay circuit is used for delaying the trigger signal to perform signal hold on the trigger signal and then output the trigger signal.
3. The signal holding circuit of claim 2, wherein the delay circuit comprises a first capacitor and a first resistor, a first end of the first capacitor connected in parallel with the first resistor is connected to the signal receiving end, a first end of the first capacitor connected in parallel with the first resistor is further connected to the signal transmitting end of the controller, and a second end of the first capacitor connected in parallel with the first resistor is grounded.
4. The signal holding circuit of claim 2, wherein the interrupt signal holding circuit further comprises a first switch circuit, a controlled end of the first switch circuit is connected to a second end of the delay circuit, a first end of the first switch circuit is connected to a signal transmission end of the controller, the first end of the first switch circuit is further connected to a power supply, a second end of the first switch circuit is grounded, and the first switch circuit is configured to be turned on when receiving a trigger signal output by the delay circuit, so as to output the trigger signal to the controller.
5. The signal holding circuit of claim 4, wherein the first switching circuit comprises a second resistor and a first switching tube, a controlled end of the first switching tube is connected to a second end of the delay circuit, a first end of the first switching tube is connected to a signal transmission end of the controller through the second resistor, and a second end of the first switching tube is grounded.
6. The signal holding circuit of claim 4, wherein the interrupt signal holding circuit further comprises a discharge circuit, one end of the discharge circuit is connected to the second end of the delay circuit, and the other end of the discharge circuit is connected to the signal transmission end of the controller.
7. The signal holding circuit of claim 6, wherein the discharge circuit comprises a third resistor and a second switching tube, a controlled end of the second switching tube is connected to a signal transmission end of the controller, a first end of the second switching tube is connected to a second end of the delay circuit through the third resistor, and a second end of the second switching tube is grounded.
8. The signal holding circuit according to any one of claims 1 to 7, further comprising an inverter, an input terminal of the inverter being connected to an output terminal of the tact switch, an output terminal of the inverter being connected to a wake-up signal access terminal of the controller, the inverter being configured to invert a phase of the trigger signal and output the phase to the controller to wake up the controller.
9. The signal holding circuit of claim 8, wherein the inverter comprises a third switching tube and a fourth resistor, a controlled end of the third switching tube is connected with an output end of the tact switch, a first end of the third switching tube is connected with a wake-up signal access end of the controller, the first end of the third switching tube is further connected with a power supply through the fourth resistor, and a second end of the third switching tube is grounded.
10. A low power consumption device, characterized in that the low power consumption device comprises a tact switch and a controller, and a signal holding circuit according to any one of claims 1-9, one end of the signal holding circuit is connected to an output terminal of the tact switch, and the other end of the signal holding circuit is connected to the controller.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321725324.2U CN220273657U (en) | 2023-07-03 | 2023-07-03 | Signal holding circuit and low power consumption device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321725324.2U CN220273657U (en) | 2023-07-03 | 2023-07-03 | Signal holding circuit and low power consumption device |
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| Publication Number | Publication Date |
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| CN220273657U true CN220273657U (en) | 2023-12-29 |
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| CN202321725324.2U Active CN220273657U (en) | 2023-07-03 | 2023-07-03 | Signal holding circuit and low power consumption device |
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- 2023-07-03 CN CN202321725324.2U patent/CN220273657U/en active Active
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