CN220272130U - Circuit for driving nixie tube to display and key detection - Google Patents
Circuit for driving nixie tube to display and key detection Download PDFInfo
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- CN220272130U CN220272130U CN202321048179.9U CN202321048179U CN220272130U CN 220272130 U CN220272130 U CN 220272130U CN 202321048179 U CN202321048179 U CN 202321048179U CN 220272130 U CN220272130 U CN 220272130U
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Abstract
The utility model discloses a circuit for driving nixie tube display and key detection, which comprises an MCU main control unit, a chip cascading unit, current limiting resistors R1-R8, nixie tubes L1-L10 and keys PB1-PB10, wherein the MCU main control unit is connected with a chip U1, a chip U2 and the nixie tubes L9-L10, the chip U1 is connected with the nixie tubes L1-L10 through the current limiting resistors, the chip U2 is connected with the nixie tubes L1-L8 and PB1-PB8, and the MCU main control unit is connected with the keys PB1-PB10. According to the utility model, the 4 IO ports of the MCU are used, the two chips are cascaded, the display of 10 nixie tubes and the key detection of 10 key switches can be controlled simultaneously, the circuit is simple, the control is convenient, the stability is strong, the output of a plurality of nixie tubes and the input of a plurality of keys can be realized, the cost is low, and the method has a high practical value.
Description
Technical Field
The utility model relates to the technical field of automatic control, in particular to a circuit for driving a nixie tube to display and detecting keys.
Background
In the man-machine interaction mode, the nixie tube is a common display mode and an original display mode, and basic man-machine operation can be completed by matching with a touch switch key.
In practical applications, considering the problems of product size, cost, etc., it is often necessary to use circuits that are as simple as possible to realize the corresponding functions. The most common mode of display and key operation is to use MCU to drive directly, this is the simplest and most convenient mode, but when meeting the occasion that needs a plurality of display and keys, MCU's pin often can not enough, and the MCU of the larger size of selection can cause unnecessary wasting of resources, just needs to add outside extension drive chip this moment.
Disclosure of Invention
The utility model aims to provide a circuit for driving a nixie tube to display and detecting keys, which solves the problem of resource waste caused by using a MCU with larger size due to insufficient pins of the MCU when a plurality of displays and keys are driven in the prior art.
In order to achieve the above purpose, the utility model adopts the following technical scheme:
the circuit for driving the nixie tube to display and key detection comprises an MCU main control unit, a chip cascading unit, current limiting resistors R1-R8, nixie tubes LED1-LED10 and keys PB1-PB10, wherein the chip cascading unit comprises a chip U1 and a chip U2, a shift register and an output register are arranged in the chip U1 and the chip U2, the MCU main control unit is connected with the chip U1, the chip U2 and the nixie tubes L9-L10, the chip U1 is connected with the nixie tubes L1-L10 through the current limiting resistors R1-R8, the chip U2 is connected with the nixie tubes L1-L8 and the keys PB1-PB8, and the MCU main control unit is connected with the keys PB1-PB10;
the MCU master control unit comprises a pin SDA, a pin SCL1, a pin SCL2 and a pin KS, wherein the other end of the pin SDA is connected with a pin SI of a chip U1, the pin SDA is a serial data input end of the chip U1, a pin QH of the chip U1 is connected with a pin SI of a chip U2, data are sent to the chip U2, the pin SCL1 is a data input clock line of the chip U1 and the chip U2, the data are sent to a shift register inside the chip U1 and the chip U2 according to bits during rising, the pin SCL2 is a clock line for latching the internal output registers of the chip U1 and the chip U2, complete data are latched during rising, and the pin KS is used for the MCU master control unit to read key values.
Further, one end of the pin SDA of the MCU master control unit is connected to the capacitor C4, one end of the pin SCL2 of the MCU master control unit is connected to the capacitor C5, one end of the pin SCL1 of the MCU master control unit is connected to the capacitor C6, one end of the pin KS of the MCU master control unit is connected to the capacitor C7, the other pins of the capacitor C4, the capacitor C5, the capacitor C6 and the capacitor C7 are connected in series to each other and are connected to the ground GND together, and the capacitor C4, the capacitor C5, the capacitor C6 and the capacitor C7 are ceramic capacitors of 50V and 200pF for filtering of signal lines and enhancing anti-interference capability;
a filter capacitor C1 is arranged on one side of the chip U1, one end of the capacitor C1 is connected with the ground GND, and the other end of the capacitor C1 is connected with a power supply VCC; one side of the chip U2 is provided with a filter capacitor C2, one end of the capacitor C2 is connected with the ground GND, the other end of the capacitor C1 is connected with a power supply VCC, and the capacitor C1 and the capacitor C2 are ceramic chip capacitors with 50V0.1uF and are used for power supply decoupling.
Further, a pin QA of the chip U1 is connected with a current limiting resistor R1, a pin QB of the chip U1 is connected with a current limiting resistor R2, a pin QC of the chip U1 is connected with a current limiting resistor R3, a pin QD of the chip U1 is connected with a current limiting resistor R4, a pin QE of the chip U1 is connected with a current limiting resistor R5, a pin QF of the chip U1 is connected with a current limiting resistor R6, a pin QG of the chip U1 is connected with a current limiting resistor R7, a pin QH of the chip U1 is connected with a current limiting resistor R8, and the resistors R1-R8 are resistances of 510 ohms and 0.1W;
one end of the current limiting resistor R1-R8 is connected with 8 segment code input ends of the nixie tubes LED1-LED10, a pin A of the current limiting resistor R1 is connected with a pin 7 of the nixie tubes L1-L10, a pin B of the current limiting resistor R2 is connected with a pin 6 of the nixie tubes L1-L10, a pin C of the current limiting resistor R3 is connected with a pin 4 of the nixie tubes L1-L10, a pin D of the current limiting resistor R4 is connected with a pin 2 of the nixie tubes L1-L10, a pin E of the current limiting resistor R5 is connected with a pin 1 of the nixie tubes L1-L10, a pin F of the current limiting resistor R6 is connected with a pin 9 of the nixie tubes L1-L10, a pin G of the current limiting resistor R7 is connected with a pin 10 of the nixie tubes L1-L10, and a pin DP of the current limiting resistor R8 is connected with a pin 5 of the nixie tubes L1-L10.
Further, the nixie tube L1-L10 is a common cathode nixie tube, the common cathode signal S1 of the nixie tube L1 is connected with the pin QA of the chip U2, the common cathode signal S2 of the nixie tube L2 is connected with the pin QB of the chip U2, the common cathode signal S3 of the nixie tube L3 is connected with the pin QC of the chip U2, the common cathode signal S4 of the nixie tube L4 is connected with the pin QD of the chip U2, the common cathode signal S5 of the nixie tube L5 is connected with the pin QF of the chip U2, the common cathode signal S7 of the nixie tube L7 is connected with the pin QG of the chip U2, the common cathode signal S8 of the nixie tube L8 is connected with the pin QH of the chip U2, the common cathode signal multiplexing pin SCL1 of the nixie tube L9 is connected with the MCU master control unit, and the common cathode signal multiplexing pin SDA of the nixie tube L10 is connected with the MCU master control unit.
Further, the common cathode signal S1 of the nixie tube L1 is connected to the cathode of the diode D1, the common cathode signal S2 of the nixie tube L2 is connected to the cathode of the diode D2, the common cathode signal S3 of the nixie tube L3 is connected to the cathode of the diode D3, the common cathode signal S4 of the nixie tube L4 is connected to the cathode of the diode D4, the common cathode signal S5 of the nixie tube L5 is connected to the cathode of the diode D5, the common cathode signal S6 of the nixie tube L6 is connected to the cathode of the diode D6, the common cathode signal S7 of the nixie tube L7 is connected to the cathode of the diode D7, the common cathode signal S8 of the nixie tube L8 is connected to the cathode of the diode D8, the common cathode signal SCL1 of the nixie tube L9 is connected to the cathode of the diode D9, and the common cathode signal SDA of the nixie tube L10 is connected to the cathode of the diode D10.
Further, two ends of the keys PB1-PB10 are respectively connected with the anodes of the diodes D1-D10 and a key detection pin KS of the MCU main control unit, and the pin KS of the MCU main control unit is connected with a resistor R9 which plays a role in pull-up.
Further, the models of the chips U1 and U2 are 74HC595.
The beneficial effects of the utility model are as follows: under the same application occasion, the utility model uses 4 IO ports of the MCU, and the two chips are cascaded, so that 10 nixie tubes can be controlled to display and 10 touch switch keys can be detected simultaneously, the circuit is simple, the control is convenient, the stability is strong, the output of a plurality of nixie tubes and the input of a plurality of keys can be realized, the cost is low, and the utility model has great practical value.
Drawings
FIG. 1 is a schematic block diagram of the present utility model;
fig. 2 is a schematic diagram of a power module circuit according to the present utility model.
Detailed Description
Referring to fig. 1, the circuit for driving nixie tube display and key detection disclosed by the utility model comprises an MCU main control unit, a chip cascade unit, current-limiting resistors R1-R8, nixie tubes L1-L10 and keys PB1-PB10. The chip cascade unit comprises a chip U1 and a chip U2, and the MCU main control unit is connected with keys PB1-PB10 so as to receive key signals. The MCU master control unit sends 16-bit data to the chip U1 and the chip U2 through cascading, and is matched with a pin SCL1 (clock 1), a pin SCL2 (clock 2), a pin SDA (data) and current limiting resistors R1-R8 to finish driving of the nixie tubes L1-L10, meanwhile, the MCU master control unit finishes scanning of keys by detecting the high and low levels of a pin KS, the chip U1 is used for controlling segment code signals output by the nixie tubes, the chip U2 is used for controlling bit selection signals output by the nixie tubes, and the pin SCL1 and the pin SDA of the MCU master control unit are multiplexed into bit selection signals. The model of the chip U1 and the chip U2 is 74HC595, the MCU main control unit is a singlechip MCU, and the model is STC8H3K32S2.
Referring to fig. 2, a capacitor C3, a capacitor C4, a capacitor C5 and a capacitor C6 on the side of the mcu main control unit are used for filtering signal lines, so as to enhance anti-interference capability, and the capacitor C4, the capacitor C5, the capacitor C6 and the capacitor C7 are ceramic chip capacitors of 50V200 pF. The capacitors C1 and C2 on the edges of the chip U1 and the chip U2 are ceramic chip capacitors of 50V0.1uF and are used for power decoupling, so that the power supply of the chip U1 and the chip U2 is stable, and interference is prevented. The parallel output port of the chip U1 flows into the nixie tubes L1-L10 through the current limiting resistors R1-R8, the parallel output port of the chip U1 is a pin QA-QH of the chip U1, the pin QA of the chip U1 is connected with the current limiting resistor R1, the pin QB of the chip U1 is connected with the current limiting resistor R2, the pin QC of the chip U1 is connected with the current limiting resistor R3, the pin QD of the chip U1 is connected with the current limiting resistor R4, the pin QE of the chip U1 is connected with the current limiting resistor R5, the pin QF of the chip U1 is connected with the current limiting resistor R6, the pin QG of the chip U1 is connected with the current limiting resistor R7, and the pin QH of the chip U1 is connected with the current limiting resistor R8; one end of the current limiting resistor R1-R8 is connected with 8 segment code input ends of the nixie tubes L1-L10, a pin A of the current limiting resistor R1 is connected with a pin 7 of the nixie tubes L1-L10, a pin B of the current limiting resistor R2 is connected with a pin 6 of the nixie tubes L1-L10, a pin C of the current limiting resistor R3 is connected with a pin 4 of the nixie tubes L1-L10, a pin D of the current limiting resistor R4 is connected with a pin 2 of the nixie tubes L1-L10, a pin E of the current limiting resistor R5 is connected with a pin 1 of the nixie tubes L1-L10, a pin F of the current limiting resistor R6 is connected with a pin 9 of the nixie tubes L1-L10, a pin DP of the current limiting resistor R7 is connected with a pin 5 of the nixie tubes L1-L10, and the resistor R1-R8 is a resistor of 510 ohm 0.1W.
The MCU master control unit comprises a pin SDA, a pin SCL1 and a pin SCL2, the other end of the pin SDA is connected with a pin SI of a chip U1, the pin SDA is a serial data input end of the chip U1, the chip U1 sends data to a chip U2 through cascading, the pin SCL1 is a U1 and U2 data input clock line, the pin SCL1 is connected with a pin SCK of the U1 and U2, the data is sent to a shift register inside the U1 and U2 according to bits during rising edges, the pin SCL2 is a clock line for latching the output registers inside the U1 and U2, the pin SCL2 is connected with a pin G# and a pin RCK of the chip U1 and U2, complete data is output during rising edges, and a pin QH of the chip U1 is connected with a pin SI of the chip U2 to realize cascading. The power supply VCC is connected to one pin of chip U1 and chip U2, ground GND is connected to one pin of chip U1 and chip U2, power VCC is connected to one pin of MCU master control unit, ground GND is connected to one pin of MCU master control unit, power VCC is +5V's direct current voltage.
The utility model discloses a digital tube, including nixie tube L1-L10, the nixie tube L1' S common cathode signal S1 connects the pin QA of chip U2, the common cathode signal S2 of nixie tube L2 connects the pin QB of chip U2, the common cathode signal S3 of nixie tube L3 connects the pin QC of chip U2, the common cathode signal S4 of nixie tube L4 connects the pin QD of chip U2, the common cathode signal S5 of nixie tube L5 connects the pin QE of chip U2, the common cathode signal S6 of nixie tube L6 connects the pin QF of chip U2, the common cathode signal S7 of nixie tube L7 connects the pin QG of chip U2, the common cathode signal S8 of nixie tube L8 connects the pin QH of chip U2, the common cathode signal multiplexing pin SCL1 of nixie tube L9 connects MCU master control unit, the common cathode signal multiplexing of nixie tube L10 connects MCU master control unit. The common cathode signal S1 of the nixie tube L1 is connected with the cathode of the diode D1, the common cathode signal S2 of the nixie tube L2 is connected with the cathode of the diode D2, the common cathode signal S3 of the nixie tube L3 is connected with the cathode of the diode D3, the common cathode signal S4 of the nixie tube L4 is connected with the cathode of the diode D4, the common cathode signal S5 of the nixie tube L5 is connected with the cathode of the diode D5, the common cathode signal S6 of the nixie tube L6 is connected with the cathode of the diode D6, the common cathode signal S7 of the nixie tube L7 is connected with the cathode of the diode D7, the common cathode signal S8 of the nixie tube L8 is connected with the cathode of the diode D8, the common cathode signal SCL1 of the nixie tube L9 is connected with the cathode of the diode D9, and the common cathode signal SDA of the nixie tube L10 is connected with the cathode of the diode D10.
The diodes D1-D10 play a role in one-way conduction, mutual interference between the keys PB1-PB10 and the nixie tubes L1-L10 is prevented, and the diodes D1-D10 are 1N4148 and have a conduction voltage of 0.6V. The two ends of the keys PB1-PB10 are respectively connected with the anodes of the diodes D1-D10 and a key detection pin KS of the MCU main control unit, the other end of the pin KS is connected with a resistor R9 playing a role of pull-up, one end of the resistor R9 is connected with a power supply VCC, and the pin KS is used for the MCU main control unit to read key values of keys.
The working process of the utility model is as follows:
the MCU master control unit firstly sets a pin SCL2 to be high level to inhibit data output, at the moment, the pin SCL1 and the pin SDA can not influence the display of a nixie tube when transmitting data, sets the code data of a nixie tube L1 section to be high eight bits of 16-bit data, sets the data 0xFE of the nixie tube L1 section to be low eight bits, firstly transmits the low eight bits to a shift register in the chip U2 through the pin SDA and in cascade connection, then transmits the high eight bits to the shift register in the chip U1, then sets the pin SCL2 to be low and then sets the high again, so that the data are totally latched in the shift register but are inhibited from being output, and then the pins SCL1 and SDA are multiplexed into bit selection signals of the nixie tube L9 and the nixie tube L10, at the moment, the level change of the pins SCL1 and the SDA can not influence the data of the output register, the pins SCL1 and the high level are inhibited from being selected, then the pins SCL2 are set to be low level to enable the data of the output register to be the nixie tube L9 and the nixie tube L1, and the display of the nixie tube L1 is completed. Meanwhile, the MCU main control unit detects the level signal of the pin KS, and when the low level is detected, the key PB1 is indicated to be pressed. Similarly, changing the bit selection data of the nixie tubes L1-L8 to 0xFE, 0xFD, 0xFB, 0xF7, 0xEF, 0xDF, 0xBF and 0x7F can finish dynamic display of the nixie tubes L1-L8, then changing the bit selection data of the L1-L8 to 0xFF disables the bit selection of the nixie tubes L1-L8, enables the bit selection of the nixie tubes L9 only when the pin SCL1 is low and enables the bit selection of the nixie tubes L10 only when the pin SDA is low when the pin SCL1 and the pin SDA are multiplexed into bit selection signals, and finish dynamic display of all the nixie tubes L1-L10 and detection of states of the keys PB1-PB10.
It should be noted that the foregoing embodiments are merely illustrative of the technical concept and features of the present utility model, and one end, the vicinity and the like have been described corresponding to the drawings of the present utility model, and are not intended to limit the specific disclosure, so that those skilled in the art can understand the disclosure of the present utility model and implement it accordingly, and the scope of protection of the present utility model is not limited thereto. All equivalent changes or modifications made in accordance with the spirit of the present utility model should be construed to be included in the scope of the present utility model.
Claims (7)
1. The circuit for driving the nixie tube to display and key detection is characterized by comprising an MCU main control unit, a chip cascading unit, current-limiting resistors R1-R8, nixie tubes L1-L10 and keys PB1-PB10, wherein the chip cascading unit comprises a chip U1 and a chip U2, a shift register and an output register are arranged in the chip U1 and the chip U2, the MCU main control unit is connected with the chip U1, the chip U2 and the nixie tubes L9-L10, the chip U1 is connected with the nixie tubes L1-L10 through the current-limiting resistors R1-R8, the chip U2 is connected with the nixie tubes L1-L8 and the keys PB1-PB8, and the MCU main control unit is connected with the keys PB1-PB10;
the MCU master control unit comprises a pin SDA, a pin SCL1, a pin SCL2 and a pin KS, wherein the other end of the pin SDA is connected with a pin SI of a chip U1, the pin SDA is a serial data input end of the chip U1, a pin QH of the chip U1 is connected with a pin SI of a chip U2, data are sent to the chip U2, the pin SCL1 is a data input clock line of the chip U1 and the chip U2, the data are sent to a shift register inside the chip U1 and the chip U2 according to bits during rising, the pin SCL2 is a clock line for latching the internal output registers of the chip U1 and the chip U2, complete data are latched during rising, and the pin KS is used for the MCU master control unit to read key values.
2. The circuit for driving a nixie tube to display and detect a key according to claim 1, wherein one end of the pin SDA is connected to a capacitor C4, one end of the pin SCL2 is connected to a capacitor C5, one end of the pin SCL1 is connected to a capacitor C6, one end of the pin KS is connected to a capacitor C7, the other pins of the capacitor C4, the capacitor C5, the capacitor C6 and the capacitor C7 are connected in series to each other and are connected to the ground GND, the capacitor C4, the capacitor C5, the capacitor C6 and the capacitor C7 are ceramic capacitors of 50V and 200pF, and are used for filtering signal lines and enhancing anti-interference capability;
a filter capacitor C1 is arranged on one side of the chip U1, one end of the capacitor C1 is connected with the ground GND, and the other end of the capacitor C1 is connected with a power supply VCC; one side of the chip U2 is provided with a filter capacitor C2, one end of the capacitor C2 is connected with the ground GND, the other end of the capacitor C1 is connected with a power supply VCC, and the capacitor C1 and the capacitor C2 are ceramic chip capacitors with 50V0.1uF and are used for power supply decoupling.
3. The circuit for driving a nixie tube to display and detect a key according to claim 1, wherein a pin QA of the chip U1 is connected with a current limiting resistor R1, a pin QB of the chip U1 is connected with a current limiting resistor R2, a pin QC of the chip U1 is connected with a current limiting resistor R3, a pin QD of the chip U1 is connected with a current limiting resistor R4, a pin QE of the chip U1 is connected with a current limiting resistor R5, a pin QF of the chip U1 is connected with a current limiting resistor R6, a pin QG of the chip U1 is connected with a current limiting resistor R7, a pin QH of the chip U1 is connected with a current limiting resistor R8, and the resistors R1 to R8 are resistances of 510 ohms and 0.1W;
one end of the current limiting resistor R1-R8 is connected with 8 segment code input ends of the nixie tubes LED1-LED10, a pin A of the current limiting resistor R1 is connected with a pin 7 of the nixie tubes L1-L10, a pin B of the current limiting resistor R2 is connected with a pin 6 of the nixie tubes L1-L10, a pin C of the current limiting resistor R3 is connected with a pin 4 of the nixie tubes L1-L10, a pin D of the current limiting resistor R4 is connected with a pin 2 of the nixie tubes L1-L10, a pin E of the current limiting resistor R5 is connected with a pin 1 of the nixie tubes L1-L10, a pin F of the current limiting resistor R6 is connected with a pin 9 of the nixie tubes L1-L10, a pin G of the current limiting resistor R7 is connected with a pin 10 of the nixie tubes L1-L10, and a pin DP of the current limiting resistor R8 is connected with a pin 5 of the nixie tubes L1-L10.
4. The circuit for driving a nixie tube to display and detect keys according to claim 1, wherein the nixie tube L1-L10 is a common cathode nixie tube, the common cathode signal S1 of the nixie tube L1 is connected with the pin QA of the chip U2, the common cathode signal S2 of the nixie tube L2 is connected with the pin QB of the chip U2, the common cathode signal S3 of the nixie tube L3 is connected with the pin QC of the chip U2, the common cathode signal S4 of the nixie tube L4 is connected with the pin QE of the chip U2, the common cathode signal S6 of the nixie tube L6 is connected with the pin QF of the chip U2, the common cathode signal S7 of the nixie tube L7 is connected with the pin QG of the chip U2, the common cathode signal S8 of the nixie tube L9 is connected with the pin QH of the chip U2, the common cathode signal multiplexing pin SCL1 of the nixie tube L9 is connected with the MCU master control unit, and the common cathode signal S10 of the nixie tube is connected with the MCU.
5. The circuit for driving a nixie tube display and key detection according to claim 4, wherein the common cathode signal S1 of the nixie tube L1 is connected to the cathode of the diode D1, the common cathode signal S2 of the nixie tube L2 is connected to the cathode of the diode D2, the common cathode signal S3 of the nixie tube L3 is connected to the cathode of the diode D3, the common cathode signal S4 of the nixie tube L4 is connected to the cathode of the diode D4, the common cathode signal S5 of the nixie tube L5 is connected to the cathode of the diode D5, the common cathode signal S6 of the nixie tube L6 is connected to the cathode of the diode D6, the common cathode signal S7 of the nixie tube L7 is connected to the cathode of the diode D7, the common cathode signal S8 of the nixie tube L8 is connected to the cathode of the diode D8, the common cathode signal SCL1 of the nixie tube L9 is connected to the cathode of the diode D9, and the common cathode signal of the nixie tube L10 is connected to the anode of the diode D10.
6. The circuit for driving a nixie tube to display and detect keys according to claim 5, wherein two ends of each of the keys PB1-PB10 are respectively connected with the anodes of the diodes D1-D10 and a key detection pin KS of the MCU main control unit, the other end of the key detection pin KS of the MCU main control unit is connected with a resistor R9 for pulling up, one end of the resistor R9 is connected with a power supply VCC, the diodes D1-D10 are 1N4148, and the conducting voltage is 0.6V.
7. The circuit for driving a nixie tube display and key detection according to claim 1, wherein the model numbers of the chip U1 and the chip U2 are 74HC595.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321048179.9U CN220272130U (en) | 2023-04-28 | 2023-04-28 | Circuit for driving nixie tube to display and key detection |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321048179.9U CN220272130U (en) | 2023-04-28 | 2023-04-28 | Circuit for driving nixie tube to display and key detection |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN220272130U true CN220272130U (en) | 2023-12-29 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202321048179.9U Active CN220272130U (en) | 2023-04-28 | 2023-04-28 | Circuit for driving nixie tube to display and key detection |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN220272130U (en) |
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2023
- 2023-04-28 CN CN202321048179.9U patent/CN220272130U/en active Active
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