CN220233199U - Image sensor and semiconductor structure thereof - Google Patents
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- CN220233199U CN220233199U CN202321690007.1U CN202321690007U CN220233199U CN 220233199 U CN220233199 U CN 220233199U CN 202321690007 U CN202321690007 U CN 202321690007U CN 220233199 U CN220233199 U CN 220233199U
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 64
- 238000009792 diffusion process Methods 0.000 claims abstract description 108
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 229910052751 metal Inorganic materials 0.000 claims abstract description 32
- 239000002184 metal Substances 0.000 claims abstract description 32
- 238000006243 chemical reaction Methods 0.000 claims abstract description 19
- 238000002955 isolation Methods 0.000 claims description 17
- 230000003071 parasitic effect Effects 0.000 abstract description 7
- 150000002500 ions Chemical class 0.000 description 42
- 238000000034 method Methods 0.000 description 17
- 238000010586 diagram Methods 0.000 description 7
- 238000005468 ion implantation Methods 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000001465 metallisation Methods 0.000 description 5
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 239000010941 cobalt Substances 0.000 description 3
- 229910017052 cobalt Inorganic materials 0.000 description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 238000005457 optimization Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Abstract
The present application describes a semiconductor structure comprising: a semiconductor substrate having a photoelectric conversion region therein and a gate electrode on the photoelectric conversion region; the active areas are positioned in the semiconductor substrate and distributed on two sides of the grid electrode; the contact diffusion region is positioned in the semiconductor substrate, at least comprises a first contact diffusion region, and the first contact diffusion region is positioned at one side of the active region, which is away from the grid electrode, and only partially overlaps with the active region; the dielectric layer is positioned above the semiconductor substrate and the grid electrode, and a through hole at least partially exposing the contact diffusion region is formed in the dielectric layer; and the metal plug layer is positioned in the through hole. According to the transistor, the first contact diffusion region is arranged on one side, deviating from the grid, of the active region, so that the first contact diffusion region only partially overlaps the active region, the channel is little affected by ion diffusion, the parasitic capacitance of the source electrode and the drain electrode is reduced, and the working efficiency of the transistor is improved.
Description
Technical Field
The present utility model relates to the field of image sensors, and more particularly, to an image sensor and a semiconductor structure thereof.
Background
The current CMOS sensor process evolves from traditional logic circuit processes, where there are many process steps that are interrelated between sensor light sensing device performance and peripheral logic circuit performance. Therefore, the best performance of the image sensor cannot be achieved in the actual production design. With the continuous optimization of the special process of the pixels and the occurrence of stacking, further optimization of the performance of the photosensitive devices is possible. The patent provides a process step for optimizing a receiving and emitting hole of a photosensitive device, which is used for realizing more like-quality performance optimization.
Disclosure of Invention
In view of the above, the present utility model provides a semiconductor structure of an image sensor, comprising: a semiconductor substrate having a photoelectric conversion region therein and a gate electrode on the photoelectric conversion region; the active areas are positioned in the semiconductor substrate and distributed on two sides of the grid electrode; the contact diffusion region is positioned in the semiconductor substrate, at least comprises a first contact diffusion region, and the first contact diffusion region is positioned at one side of the active region, which is away from the grid electrode, and only partially overlaps with the active region; the dielectric layer is positioned above the semiconductor substrate and the grid electrode, and a through hole at least partially exposing the contact diffusion region is formed in the dielectric layer; and the metal plug layer is positioned in the through hole.
Optionally, the overlapping area of the first contact diffusion region and the active region is a, and the non-overlapping area of the first contact diffusion region and the active region is b; wherein a > b.
Optionally, the ion doping concentration of the overlapped area of the first contact diffusion area and the active area is greater than the ion doping concentration of the non-overlapped area of the first contact diffusion area and the active area.
Optionally, the lateral width of the overlapping area of the first contact diffusion area and the active area is n, the lateral width of the active area is m, and the lateral width of the grid side wall is s, wherein m-n is greater than or equal to s.
Optionally, the contact diffusion region further includes a second contact diffusion region, a projection of the second contact diffusion region on the vertical direction being located within the active region.
Optionally, the gate includes one or more of a transfer gate, a reset gate, a source follower gate, and a row select gate.
Optionally, the semiconductor structure further includes: the pixel isolation structure is positioned between the adjacent photoelectric conversion areas; the projection of the first contact diffusion region on the vertical direction partially overlaps the pixel isolation structure.
Optionally, the lateral width of the first contact diffusion region is always greater than the lateral width of the metal plug on the same horizontal plane.
The utility model also provides an image sensor, and a semiconductor structure comprising the image sensor.
Compared with the prior art, the utility model has at least one of the following outstanding advantages:
according to the utility model, the first contact diffusion region is arranged on one side of the active region, which is away from the grid electrode, so that the first contact diffusion region only partially overlaps with the active region, therefore, in the pixel size miniaturization process, even if ions are laterally diffused, the influence of a channel is still small, the parasitic capacitance of a source electrode and a drain electrode is not influenced by the ion diffusion, the working efficiency of the transistor is improved, and the contact resistance between the active region and the metal plug is reduced by enough connection through the ion lateral diffusion of the contact diffusion region.
Drawings
FIG. 1 is a diagram showing steps in a conventional image sensor semiconductor structure;
FIG. 2 is a schematic partial cross-sectional view of a semiconductor structure according to an embodiment of the present utility model;
FIG. 3 is a schematic view of a first contact diffusion region according to an embodiment of the present utility model;
fig. 4 is a schematic structural diagram of a pixel circuit according to an embodiment of the present utility model;
FIG. 5 is a schematic partial cross-sectional view of another semiconductor structure according to an embodiment of the present utility model;
fig. 6 is a schematic diagram showing steps of a method for manufacturing a semiconductor structure according to an embodiment of the present utility model;
fig. 7 is a step diagram of a method of fabricating the semiconductor structure shown in fig. 2;
fig. 8 illustrates steps of another method for fabricating a semiconductor structure according to an embodiment of the present utility model;
fig. 9 is a process step diagram of the fabrication of the semiconductor structure shown in fig. 5.
Detailed Description
In order that the above objects, features and advantages of the utility model will be readily understood, a further description of the utility model will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
It is noted that in the following description, specific details are set forth in order to provide a thorough understanding of the present utility model. The present utility model may be embodied in many other forms than those herein described, and those skilled in the art may readily devise numerous other arrangements that do not depart from the spirit of the utility model. Therefore, the present utility model is not limited by the specific embodiments disclosed below.
Referring to fig. 2, fig. 2 is a schematic diagram of a semiconductor structure according to an embodiment of the present utility model, including:
a semiconductor substrate 10 having a photoelectric conversion region (not shown) therein and a gate electrode 20 located on the photoelectric conversion region; the gate 20 further includes a sidewall 201 at a side surface thereof, so as to increase the width of the gate 20 and the drain LDD region, thereby effectively controlling the parasitic capacitance effect.
An active region 12 located in the semiconductor substrate 10 and distributed on both sides of the gate 20; the active regions of different doping types may form an n-type active region or a p-type active region, and the active regions may be divided into a source region and a drain region.
A contact diffusion region 14 in the semiconductor substrate 10, the contact diffusion region 14 comprising at least a first contact diffusion region 140, and the first contact diffusion region 140 being located on a side of the active region 12 facing away from the gate and only partially overlapping the active region; the formation of the contact diffusion region in the active region is a preliminary step of forming the metal plug, and the ion doping concentration of the active region has a great influence on the contact resistance between the metal plug and the active region, so that the contact resistance between the active region and the metal plug can be reduced by further ion doping on the active region to form a contact diffusion region with higher ion concentration, and the ion doping type of the contact diffusion region is consistent with that of the corresponding active region.
A dielectric layer 30 located above the semiconductor substrate 10 and the gate 20, the dielectric layer 30 having a via 32 therein at least partially exposing the contact diffusion region 14; it is understood that the dielectric layer 30 herein may comprise more than one dielectric layer, and may comprise, for example, a combination of one or more of an oxide, a silicon oxide, a nitride, a silicon nitride, or an oxynitride, without limitation.
A metal plug layer 40 is located within the via 32. The process of depositing a metal or metallization within the via 32 to form a metal connection layer is referred to as a local interconnect process, and in some embodiments, at least one of nickel, cobalt, aluminum, copper, titanium, or tungsten may be selected.
In the prior art, as shown in the step diagram of the conventional image sensor semiconductor structure of fig. 1, after forming an active region 112 in a semiconductor substrate 110, further ion doping is performed in the active region 112 to form a contact diffusion region 114, then a dielectric layer 130 is disposed, a contact hole pattern is defined in the dielectric layer 130 by a photolithography process, self-aligned etching of the contact hole is performed according to the contact hole pattern, a contact hole is formed to expose the contact diffusion region 114, and finally a metal or a metallization is deposited in the contact hole to form a metal plug layer 140. However, as the size of the pixel unit decreases, the distance between the gates decreases, and the process of forming a contact diffusion region by ion doping in the active region directly, the lateral diffusion of ions affects the length of the channel, the integration level and performance of the device, and secondly, the diffusion of ions affects the parasitic capacitance of the source and drain, thereby affecting the working efficiency of the transistor.
Therefore, in the present utility model, by disposing the first contact diffusion region 140 on the side of the active region 12 facing away from the gate 20, the first contact diffusion region 140 only partially overlaps the active region 12, so that in the pixel size miniaturization process, even if the channel is affected by the lateral diffusion of the ions, the parasitic capacitance of the source and the drain is not affected by the lateral diffusion of the ions, so that the working efficiency of the transistor is improved, and the metal plug and the active region can be sufficiently connected by the lateral diffusion of the ions of the contact diffusion region, so as to reduce the contact resistance between the active region and the metal plug.
In some embodiments, as shown in fig. 3, the area of the overlapping area of the first contact diffusion region 140 and the active region 12 is a, and the area of the non-overlapping area of the first contact diffusion region 140 and the active region 12 is b; wherein a > b. The overlapping area of the first contact diffusion region and the active region is increased, so that the conductivity of the first contact diffusion region can be improved, and the contact resistance between the metal plug and the active region is further reduced.
Further, the ion doping concentration of the overlapped region of the first contact diffusion region 140 and the active region 12 is greater than the ion doping concentration of the non-overlapped region of the first contact diffusion region 140 and the active region 12. Since the first contact diffusion region 140 is based on the ion doping concentration of the active region 12 itself, and the subsequent ion doping concentration is superimposed, the ion doping concentration in the overlapping region of the first contact diffusion region 140 and the active region 12 is greater than the ion doping concentration in the non-overlapping region of the first contact diffusion region 140 and the active region 12.
In some embodiments, referring to fig. 2 and 3, the lateral width of the overlapping region of the first contact diffusion region 140 and the active region 12 is n, the lateral width of the active region 12 is m, and the lateral width of the gate sidewall 201 is s, wherein m-n is greater than or equal to s. It is understood that the lateral width herein refers to the direction in which the source corresponding to the gate points to the drain corresponding to the gate. In the embodiment of the utility model, the length of the channel is kept as far as possible by limiting the sizes of the active region and the first contact diffusion region, so that the channel is not influenced by the lateral diffusion of ions of the first contact diffusion region.
In some embodiments, as shown in fig. 4, the pixel unit of the CMOS image sensor generally includes a photoelectric conversion element, a transfer transistor TX, a reset transistor RST, a source follower transistor SF, and a row selection transistor RS, where the photoelectric conversion element includes, but is not limited to, a photodiode PD, which may be a Pin-type photodiode PD, and meanwhile, the number of the photoelectric conversion element, the transfer transistor TX, the reset transistor RST, the source follower transistor SF, and the row selection transistor RS may be one or more, that is, the structure of the pixel unit may be correspondingly selected, and the specific structure is not limited. Correspondingly, in the semiconductor structure of the CMOS image sensor, a transmission gate, a reset gate, a source follower gate and a row selection gate can be arranged on the semiconductor substrate, and corresponding active regions are arranged on two sides of each gate to form a source electrode and a drain electrode.
In the application of the utility model, the first contact diffusion regions corresponding to the transmission gate, the reset gate, the source follower gate and the row selection gate on the semiconductor substrate can be only partially overlapped with the active region, so that the influence of the lateral diffusion of ion doping on the channel is reduced, the parasitic capacitance of the source drain region is reduced, and the metal plug and the active region are sufficiently connected through the lateral diffusion of ions of the contact diffusion regions.
In some embodiments, referring to fig. 2, the contact diffusion regions further comprise a second contact diffusion region 142, the projection of the second contact diffusion region 142 in the vertical direction being located within the active region 12; it is understood that the projection in the vertical direction refers to the projection of the dielectric layer 30 in the direction of the semiconductor substrate 10. I.e., the active regions on both sides of the gate, one is doped with a first contact diffusion region 140 and the other is doped with a second contact diffusion region 142. The semiconductor structure design based on the CMOS pattern sensor generally sets the active regions corresponding to the transfer gate, the reset gate, the source follower gate and the row select gate on the semiconductor substrate as N-type ion doped regions, that is, the contact diffusion regions corresponding to the transfer gate, the reset gate, the source follower gate and the row select gate may be all set as N-type ion doped first contact diffusion regions, so that the N-type ion doped first contact diffusion regions only partially overlap with the active regions. The semiconductor substrate itself is a P-type semiconductor substrate, and the corresponding contact diffusion region may be configured as a second contact diffusion region 142 located in the active region, and a voltage is applied through the external connection trace.
In some embodiments, as shown in fig. 5, the semiconductor structure further comprises: a pixel isolation structure 50 located between adjacent photoelectric conversion regions (not shown); the projection of the first contact diffusion 140 in the vertical direction partially overlaps the pixel isolation structure 50. It is understood that the projection in the vertical direction refers to the projection of the dielectric layer 30 in the direction of the semiconductor substrate 10.
Alternatively, the lateral width of the first contact diffusion region 140 is always larger than the lateral width of the metal plug 40 on the same horizontal plane. It is understood that the lateral width herein refers to the direction in which the source corresponding to the gate points to the drain corresponding to the gate. Further, since the first contact diffusion region is not disposed on the same level of the metal plug above the pixel isolation structure 50, i.e., the metal plug on the same level does not include the metal plug in the dielectric layer, by increasing the lateral width of the first contact diffusion region 14 in the via hole 32, the contact area between the metal plug and the active region can be increased, thereby reducing the contact resistance.
In the process of the image sensor, a part of the pixel isolation structure 50 may be etched, so that the contact diffusion region is laterally diffused into the etched region of the pixel isolation structure 50, so that the pixel unit area is further reduced by fully utilizing the space of the pixel isolation structure, and the miniaturization of the pixel size is realized.
The utility model also discloses a manufacturing method of the semiconductor structure, which comprises the following steps:
s11: providing a semiconductor substrate, wherein the semiconductor substrate is internally provided with a photoelectric conversion region, a grid electrode positioned on the photoelectric conversion region and active regions distributed on two sides of the grid electrode;
wherein in some embodiments the semiconductor substrate may be monocrystalline silicon, monocrystalline germanium, or monocrystalline germanium silicon substrate. In other embodiments, the substrate 10 may be a monocrystalline silicon, monocrystalline germanium, or monocrystalline germanium-silicon substrate doped with p-type ions or n-type ions.
S12: forming a dielectric layer over a semiconductor substrate;
the dielectric layer herein may comprise more than one dielectric layer, and may comprise, for example, a combination of one or more of an oxide, a silicon oxide, a nitride, a silicon nitride, or an oxynitride.
S13: patterning the dielectric layer to generate a through hole partially exposing the active region;
s14: performing ion implantation on the part of the active region exposed by the through hole to generate a contact diffusion region;
the ion implantation is performed with the ion type identical to that of the active region exposed by the through hole, for example, if the active region is an N-type ion doped region, N-type ions are selected to further implant the active region to form a contact diffusion region.
S15: and depositing metal in the through hole, wherein the metal reacts with the contact diffusion region to form a metallization, so that a metal plug layer is finally formed.
Wherein the metal can be at least one of nickel, cobalt, aluminum, copper, titanium or tungsten.
In the embodiment of the utility model, the dielectric layer is covered first, the through hole exposing the active region is formed in the dielectric layer, and then the ion implantation is carried out through the through hole, so that the transverse diffusion range of the contact diffusion region is reduced, and further the miniaturization of the pixel size is realized.
The utility model also includes a method for manufacturing the semiconductor structure, which comprises the following steps:
s21: providing a semiconductor substrate, wherein the semiconductor substrate is internally provided with a photoelectric conversion region, a grid electrode positioned on the photoelectric conversion region, active regions distributed on two sides of the grid electrode and a pixel isolation structure distributed between adjacent photoelectric conversion regions;
wherein in some embodiments the semiconductor substrate may be monocrystalline silicon, monocrystalline germanium, or monocrystalline germanium silicon substrate. In other embodiments, the substrate 10 may be a monocrystalline silicon, monocrystalline germanium, or monocrystalline germanium-silicon substrate doped with p-type ions or n-type ions.
S22: forming a dielectric layer over a semiconductor substrate;
the dielectric layer herein may comprise more than one dielectric layer, and may comprise, for example, a combination of one or more of an oxide, a silicon oxide, a nitride, a silicon nitride, or an oxynitride.
S23: patterning the dielectric layer and the pixel isolation structure to generate a through hole partially exposing the active region;
s24: performing ion implantation on the part of the active region exposed by the through hole to generate a contact diffusion region;
the ion implantation is performed with the ion type identical to that of the active region exposed by the through hole, for example, if the active region is an N-type ion doped region, N-type ions are selected to further implant the active region to form a contact diffusion region.
In this embodiment, the dielectric layer is patterned and part of the pixel isolation structure is etched, and ion implantation is performed on the side of the active region away from the gate electrode, so that ions are laterally diffused to the etched pixel isolation structure, and the partial area of the pixel isolation structure is utilized, so that the miniaturization of the pixel size is further realized.
S25: and depositing metal in the through hole, wherein the metal reacts with the contact diffusion region to form a metallization, so that a metal plug layer is finally formed.
Wherein the metal can be at least one of nickel, cobalt, aluminum, copper, titanium or tungsten.
In the utility model, the dielectric layer is covered, the through hole exposing the active region is arranged in the dielectric layer, part of the pixel isolation structure is etched, and then the through hole is used for ion implantation, so that the transverse diffusion range of the contact diffusion region is reduced, the contact diffusion region and the pixel isolation structure are also partially overlapped, the area of the pixel unit is fully utilized, and further, the miniaturization of the pixel size is further realized.
The application further provides an image sensor, in which the semiconductor structure is as described in the above embodiment, the first contact diffusion region is disposed on a side of the active region away from the gate, so that the first contact diffusion region only partially overlaps the active region, and therefore, in the pixel size miniaturization process, even if the ions laterally diffuse, the channel is still less affected, and the ion diffusion does not affect the parasitic capacitance of the source and the drain, so that the working efficiency of the transistor is improved, and the contact resistance between the active region and the metal plug is further reduced by sufficient connection through the ion laterally diffuse of the contact diffusion region.
The foregoing is a further detailed description of the utility model in connection with the preferred embodiments, and it is not intended that the utility model be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the utility model, and these should be considered to be within the scope of the utility model.
Claims (9)
1. A semiconductor structure of an image sensor, comprising:
a semiconductor substrate having a photoelectric conversion region therein and a gate electrode located above the photoelectric conversion region;
the active areas are positioned in the semiconductor substrate and distributed on two sides of the grid electrode;
a contact diffusion region in the semiconductor substrate, the contact diffusion region including at least a first contact diffusion region, the first contact diffusion region being located on a side of the active region facing away from the gate and only partially overlapping the active region;
the dielectric layer is positioned above the semiconductor substrate and the grid electrode, and a through hole which at least partially exposes the contact diffusion region is formed in the dielectric layer;
and the metal plug layer is positioned in the through hole.
2. The semiconductor structure of the image sensor as claimed in claim 1, wherein,
the area of the overlapping area of the first contact diffusion region and the active region is a, and the area of the non-overlapping area of the first contact diffusion region and the active region is b;
wherein a > b.
3. The semiconductor structure of the image sensor as claimed in claim 2, wherein,
the ion doping concentration of the overlapped area of the first contact diffusion area and the active area is larger than that of the non-overlapped area of the first contact diffusion area and the active area.
4. The semiconductor structure of the image sensor as claimed in claim 1, wherein,
the transverse width of the overlapping area of the first contact diffusion area and the active area is n, the transverse width of the active area is m, and the transverse width of the side wall of the grid electrode is s, wherein m-n is more than or equal to s.
5. The semiconductor structure of the image sensor as claimed in claim 1, wherein,
the contact diffusion region further includes a second contact diffusion region, a projection of the second contact diffusion region in a vertical direction being located within the active region.
6. The semiconductor structure of claim 1, wherein the gate comprises one or more of a transfer gate, a reset gate, a source follower gate, and a row select gate.
7. The semiconductor structure of the image sensor of claim 1, wherein the semiconductor structure further comprises: a pixel isolation structure located between adjacent photoelectric conversion regions;
a projection of the first contact diffusion region on the vertical direction partially overlaps the pixel isolation structure.
8. The semiconductor structure of claim 7, wherein a lateral width of the first contact diffusion is always greater than a lateral width of the metal plug on a same horizontal plane.
9. An image sensor, characterized in that the image sensor comprises a semiconductor structure of the image sensor according to any one of claims 1-8.
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| CN202321690007.1U CN220233199U (en) | 2023-06-29 | 2023-06-29 | Image sensor and semiconductor structure thereof |
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| CN202321690007.1U CN220233199U (en) | 2023-06-29 | 2023-06-29 | Image sensor and semiconductor structure thereof |
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| CN220233199U true CN220233199U (en) | 2023-12-22 |
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