CN220232419U - Circuit for solving writing ESD and active capacitance pen - Google Patents

Abstract

The application relates to the technical field of static electricity discharge and discloses a circuit and an initiative capacitance pen for solving the problem of writing to generate ESD, wherein the circuit comprises: the capacitive pen chip, the receiving circuit, the transmitting circuit and the ESD processing circuit; the capacitive pen chip is respectively connected with the receiving circuit and the transmitting circuit, the receiving circuit is connected with a receiving interface, and the transmitting circuit is respectively connected with the processing ESD circuit or the transmitting interface; wherein the processing ESD circuit is a grounding circuit; the processing ESD circuit is used for releasing ESD when being connected with the sending circuit. The writing efficiency of initiative electric capacity pen and dull and stereotyped is not high problem has been solved to this application.

Description

Circuit for solving writing ESD and active capacitance pen

Technical Field

The utility model relates to the technical field of static discharge, in particular to a circuit for solving the problem of ESD generated during writing and an active capacitance pen.

Background

With the rapid development of society, active capacitance pens and flat plates are used more and more frequently in various fields, and meanwhile, the working accuracy of the active capacitance pens is also more and more important.

The conventional active capacitance pen works by writing directly on a tablet without considering the generated ESD (Electro-Static discharge). The working mode of the active capacitance pen has great defects, and the problem that the line breakage between the active capacitance pen and the flat plate occurs due to no consideration of ESD exists. That is, the working mode of the active capacitance pen can cause disconnection between the active capacitance pen and the tablet due to no consideration of ESD, so that the writing efficiency of the active capacitance pen and the tablet is low.

Disclosure of Invention

The utility model mainly aims to provide a circuit for solving the problem of ESD (electro-static discharge) generated during writing and an active capacitance pen, and aims to solve the problem of low writing efficiency of the active capacitance pen and a tablet.

In order to achieve the above object, the present utility model provides a circuit for solving the problem of writing to generate ESD, which includes a capacitive pen chip, a receiving circuit, a transmitting circuit, and a circuit for processing ESD;

the capacitive pen chip is respectively connected with the receiving circuit and the transmitting circuit, the receiving circuit is connected with a receiving interface, and the transmitting circuit is respectively connected with the processing ESD circuit or the transmitting interface; wherein the processing ESD circuit is a grounding circuit;

the processing ESD circuit is used for releasing ESD when being connected with the sending circuit.

Optionally, the first end of the first resistor is connected with the first end of the first diode and the receiving interface respectively, the second end of the first resistor is connected with the receiving port of the capacitance pen chip, and the second end of the first diode is connected with the system power supply ground.

Optionally, the transmitting circuit includes a second resistor and a second diode, where a first end of the second resistor is connected to a first end of the second diode, the first end of the second resistor is further connected to the transmitting interface or the processing ESD circuit, a second end of the second resistor is connected to a transmitting port of the capacitive pen chip, and a second end of the second diode is connected to the system power supply.

Optionally, the first diode and the second diode are bidirectional transient suppression diodes.

Optionally, one end of the processing ESD circuit is connected to the system power supply, and when the transmitting circuit is connected to the transmitting interface, the transmitting circuit is disconnected from the other end of the processing ESD circuit.

Optionally, when the transmitting circuit is disconnected from the transmitting interface, the transmitting circuit is connected to the other end of the ESD handling circuit.

Optionally, the circuit for solving the problem of generating the ESD during writing further comprises a bypass circuit, wherein the bypass circuit comprises a first capacitor and a second capacitor, and the grounding end of the capacitive pen chip is connected with the system power ground through the first capacitor and the second capacitor respectively.

In addition, the application also provides an active capacitance pen, which comprises the circuit for solving the problem of writing to generate ESD.

Optionally, the active capacitance pen includes a receiving interface, a transmitting interface, a capacitance pen fixing device and a capacitance pen housing, and the capacitance pen fixing device fixes the receiving interface and the transmitting interface in the capacitance pen housing.

Optionally, the capacitive pen fixing device further includes a fixing spring, and the fixing spring fixes the front end of the receiving interface and the front end of the transmitting interface at the front end position of the capacitive pen housing.

The application provides a circuit for solving the problem of ESD generated by writing, which comprises a capacitance pen chip, a receiving circuit, a transmitting circuit and an ESD processing circuit; the capacitive pen chip is respectively connected with the receiving circuit and the transmitting circuit, the receiving circuit is connected with a receiving interface, and the transmitting circuit is respectively connected with the processing ESD circuit or the transmitting interface; wherein the processing ESD circuit is a grounding circuit; the processing ESD circuit is used for releasing ESD when being connected with the sending circuit. The ESD processing circuit is designed to be a grounding circuit, and when the ESD processing circuit is connected with the receiving circuit, the ESD is released, so that the phenomenon that the line breakage between the active capacitance pen and the flat plate occurs due to the fact that the ESD is not considered in the prior art is avoided, and when the ESD processing circuit is connected with the receiving circuit, the ESD is released, the problem that the line breakage is caused by the ESD between the active capacitance pen and the flat plate is solved, and the writing efficiency of the active capacitance pen and the flat plate is improved.

Drawings

FIG. 1 is a schematic diagram of a circuit for solving the problem of writing ESD generation in the present utility model;

FIG. 2 is a schematic diagram of the connection of a receiving circuit and a transmitting circuit in a circuit for solving the problem of writing an ESD;

FIG. 3 is a schematic diagram illustrating the connection of the ESD release circuit for solving the problem of writing ESD generation in the present utility model;

FIG. 4 is a schematic diagram of another connection of the circuit for solving the problem of writing ESD generation according to the present utility model;

fig. 5 is a schematic structural diagram of an active capacitive pen according to the present utility model.

Reference numerals illustrate:

reference numerals	Name of the name	Reference numerals	Name of the name
				10	Capacitance pen chip	20	Receiving circuit
30	Transmitting circuit	40	Handling ESD circuits
				200	Receiving interface	300	Transmission interface
M1	First diode	M2	Second diode
				R1	First resistor	R2	Second resistor

The achievement of the objects, functional features and advantages of the present utility model will be further described with reference to the accompanying drawings, in conjunction with the embodiments.

Detailed Description

It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

It should be noted that all directional indicators (such as up, down, left, right, front, and rear … …) in the embodiments of the present application are merely used to explain the relative positional relationship, movement, etc. between the components in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indicator is correspondingly changed.

In the present application, unless explicitly specified and limited otherwise, the terms "coupled," "secured," and the like are to be construed broadly, and for example, "secured" may be either permanently attached or removably attached, or integrally formed; can be mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art as the case may be.

In addition, descriptions such as those related to "first," "second," and the like, are provided for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated in this application. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be regarded as not exist and not within the protection scope of the present application.

The utility model provides a circuit for solving the problem of writing to generate ESD, referring to a structural schematic diagram of the circuit for solving the problem of writing to generate ESD of FIG. 1, the circuit for solving the problem of writing to generate ESD comprises a capacitance pen chip 10, a receiving circuit 20, a transmitting circuit 30 and an ESD processing circuit 40;

the capacitive pen chip 10 is respectively connected with the receiving circuit 20 and the transmitting circuit 30, the receiving circuit 20 is connected with the receiving interface 200, and the transmitting circuit 30 is respectively connected with the processing ESD circuit 40 or the transmitting interface 300; wherein the process ESD circuit 40 is a ground circuit;

wherein the processing ESD circuit 40 is configured to release ESD when connected to the transmitting circuit 30.

In this embodiment, when the capacitive pen writes continuously on the tablet, the capacitive pen core rubs against the tablet surface to generate ESD, which cannot be released in time. Reception by the receiving circuit 20 may cause reception errors due to ESD, thereby causing disconnection, which may cause a problem of low writing efficiency using an active capacitance pen and a tablet. By designing the ESD handling circuit 40, the ESD handling circuit 40 is connected to ground, and the simplest is to directly connect to ground through a wire, so that ESD generated during writing can be released after passing through the ESD handling circuit 40 (actually connected to ground), and ESD can be released during writing and transmitting time periods, i.e. one cycle, during writing and transmitting time periods. And further, the influence caused by incapability of timely releasing the ESD can be avoided, and the writing efficiency of the active capacitance pen and the tablet is improved.

Further, in still another embodiment of the circuit for solving the problem of generating ESD during writing, referring to fig. 2, fig. 2 is a schematic diagram illustrating connection between a receiving circuit and a transmitting circuit in the circuit for solving the problem of generating ESD during writing, the receiving circuit includes a first resistor R1 and a first diode M1, a first end of the first resistor R1 is connected to a first end of the first diode M1 and the receiving interface 200, a second end of the first resistor R1 is connected to a receiving port of the capacitive pen chip 10, and a second end of the first diode M1 is connected to a system power supply.

Specifically, the transmitting circuit 30 includes a second resistor R2 and a second diode M2, where a first end of the second resistor R2 is connected to a first end of the second diode M2, a first end of the second resistor R2 is further connected to the transmitting interface 200 or the processing ESD circuit 40, a second end of the second resistor R2 is connected to a transmitting port of the capacitive pen chip 10, and a second end of the second diode M2 is connected to the system power supply.

Specifically, the first diode M1 and the second diode M2 are bidirectional transient suppression diodes.

In the present embodiment, the circuit connection structures of the receiving circuit 20 and the transmitting circuit 30 are similar, the only difference being that the receiving circuit 20 is not connected to the processing ESD circuit 40, and the transmitting circuit 30 is connected to the processing ESD circuit 40. Further, the ESD may be released (connected to the process ESD circuit 40) after the operation of the transmission circuit 30, or the last ESD may be released when the transmission circuit 30 is connected to the process ESD circuit 40 at this time during the operation of the reception circuit 20. The bi-directional transient suppression diode acts to eliminate circuit surges. The advantage of the control is that the problem that the receiving circuit 20 works to release ESD simultaneously to cause the received signal to be interfered is avoided, so that the writing efficiency of the active capacitance pen and the tablet can be improved while the normal work is ensured.

Further, in still another embodiment of the circuit for solving the problem of ESD generated by writing, referring to fig. 3, fig. 3 is a schematic diagram illustrating a connection of the circuit for solving the problem of ESD released by writing, wherein one end of the ESD processing circuit 40 is electrically connected to the system, and the transmitting circuit 30 is disconnected from the other end of the ESD processing circuit 40 when the transmitting circuit 30 is connected to the transmitting interface 300.

Specifically, when the transmission circuit 30 is disconnected from the transmission interface 300, the transmission circuit 30 is connected to the other end of the ESD processing circuit 40.

In this embodiment, the generated ESD is not determined, the ESD processing circuit is not controlled by the control switch, and a control switch may be added to selectively connect the transmitting circuit 30 and the other end of the ESD processing circuit 40, so as to achieve the effect of releasing ESD. The ESD can be released periodically, because the ESD is accumulated, the ESD release and the TX circuit are switched in each period, the circuit cannot be damaged, and the control time can be ensured. And further, the writing efficiency and accuracy of the active capacitance pen and the tablet can be greatly improved.

Further, in still another embodiment of the circuit for solving the problem of generating ESD during writing, referring to fig. 4, fig. 4 is a schematic diagram of still another connection of the circuit for solving the problem of generating ESD during writing, the circuit for solving the problem of generating ESD during writing further includes a bypass circuit, the bypass circuit includes a first capacitor C1 and a second capacitor C2, and the ground terminal of the capacitive pen chip 10 is connected to the system power ground through the first capacitor C1 and the second capacitor C2 respectively.

In this embodiment, other interfaces may exist in the capacitive pen chip 10, such as GPIO1 in fig. 4, and each interface may be connected to a single chip or other chips, which is not limited herein. The grounding end of the capacitive pen chip 10 can be connected with the system power ground through the first capacitor C1 and the second capacitor C2, so that the chip can be protected. In the figure, TP12 is an output interface of the transmitting circuit 40, TP11 is an input interface of the receiving circuit 30, and TP13 is the other end of the ESD processing circuit 40. After the other end of the ESD circuit 40 is connected with the output interface of the transmitting circuit 40, the ESD generated by the receiving circuit 30 and the transmitting circuit 40 is released, so that the problem of writing efficiency of the active capacitance pen and the tablet due to the ESD effect is avoided, and meanwhile, the writing accuracy of the active capacitance pen and the tablet is improved.

The embodiment provides a circuit for solving the problem of ESD generated by writing, which comprises a capacitance pen chip, a receiving circuit, a transmitting circuit and an ESD processing circuit; the capacitive pen chip is respectively connected with the receiving circuit and the transmitting circuit, the receiving circuit is connected with a receiving interface, and the transmitting circuit is respectively connected with the processing ESD circuit or the transmitting interface; wherein the processing ESD circuit is a grounding circuit; the processing ESD circuit is used for releasing ESD when being connected with the sending circuit. The ESD processing circuit is designed to be a grounding circuit, and when the ESD processing circuit is connected with the receiving circuit, the ESD is released, so that the phenomenon that the line breakage between the active capacitance pen and the flat plate occurs due to the fact that the ESD is not considered in the prior art is avoided, and when the ESD processing circuit is connected with the receiving circuit, the ESD is released, the problem that the line breakage is caused by the ESD between the active capacitance pen and the flat plate is solved, and the writing efficiency of the active capacitance pen and the flat plate is improved.

In addition, referring to fig. 5, fig. 5 is a schematic structural diagram of an active capacitance pen, and the application further provides an active capacitance pen, which includes the circuit for solving the problem of writing to generate ESD.

In an embodiment, the active capacitance pen further comprises a circuit board, wherein the circuit for solving the problem of generating ESD during writing is arranged on the circuit board and is connected with a power line in the active capacitance pen;

in an embodiment, the active capacitance pen further comprises a circuit board, wherein a capacitance pen chip, a receiving circuit and a transmitting circuit in the circuit for solving the problem of generating the ESD during writing are arranged on the circuit board, and a processing ESD circuit in the circuit for solving the problem of generating the ESD during writing is arranged outside the active capacitance pen;

in an embodiment, the active capacitance pen further includes a circuit board, a capacitance pen chip in the circuit for solving the problem of generating ESD is disposed on the circuit board, a receiving circuit and a transmitting circuit in the circuit for solving the problem of generating ESD are disposed outside the circuit board and inside the active capacitance pen, and a processing ESD circuit in the circuit for solving the problem of generating ESD is disposed outside the active capacitance pen. The above is an embodiment of an active capacitance pen, and is not limited herein.

In this embodiment, the active capacitance pen may have the circuit for solving the problem of writing to generate ESD disposed on the internal PCB board, or may be directly disposed outside the PCB, or may have a wire directly connected to the transmitting circuit and connected to the internal system power ground. And then can release the ESD that produces through connecting power ground, and then guarantee the writing efficiency of initiative capacitance pen and dull and stereotyped.

Specifically, the active capacitance pen comprises a receiving interface, a transmitting interface, a capacitance pen fixing device and a capacitance pen shell, wherein the capacitance pen fixing device fixes the receiving interface and the transmitting interface in the capacitance pen shell.

Specifically, the capacitive pen fixing device further comprises a fixing spring, and the front end of the receiving interface and the front end of the sending interface are fixed at the front end position of the capacitive pen shell by the fixing spring.

In this embodiment, referring to fig. 5, rx is a receiving interface of the receiving circuit. TX is the transmitting interface of the transmitting circuit, the capacitance pen fixing device is a device for fixing the receiving interface and the transmitting interface, namely the circuit board, and the inside also comprises a processing ESD circuit, the processing ESD circuit can directly ground the transmitting interface or the system power supply ground through a wire, and the capacitance pen shell is an external fixed shell in the upper diagram in FIG. 5. The fixing device further comprises a fixing spring, the front end of the receiving interface and the front end of the transmitting interface are fixed at the front end position of the capacitive pen shell by the fixing spring, so that the whole active capacitive pen can conveniently process received signals and transmitted signals, and meanwhile, the RX ring and the RX spring are connected together, so that the receiving capacity can be increased. The above is a schematic structure of the active capacitance pen, and other structures may exist, which are not limited herein. The transmitting interface realizes ESD release by processing the ESD circuit ground or the system power ground, and the writing efficiency of the active capacitance pen and the tablet is improved.

The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the scope of the claims, and all equivalent structural changes made in the present application and the accompanying drawings or direct/indirect application in other related technical fields are included in the scope of the present application.

Claims (10)

1. The circuit for solving the problem of writing to generate the ESD is characterized by comprising a capacitance pen chip, a receiving circuit, a transmitting circuit and an ESD processing circuit;

the capacitive pen chip is respectively connected with the receiving circuit and the transmitting circuit, the receiving circuit is connected with a receiving interface, and the transmitting circuit is respectively connected with the processing ESD circuit or the transmitting interface; wherein the processing ESD circuit is a grounding circuit;

the processing ESD circuit is used for releasing ESD when being connected with the sending circuit.

2. The circuit for addressing the ESD of claim 1 wherein said receiver circuit comprises a first resistor and a first diode, said first resistor having a first terminal connected to said first diode first terminal and said receiver interface, respectively, a second terminal connected to said capacitive pen chip receiving port, and a first diode second terminal connected to system power ground.

3. The circuit for addressing the ESD of writing of claim 2 wherein said transmission circuit comprises a second resistor and a second diode, said second resistor having a first terminal connected to said first terminal of said second diode, said second resistor having a first terminal further connected to said transmission interface or said processing ESD circuit, said second resistor having a second terminal connected to a transmission port of said capacitive pen chip, said second diode having a second terminal connected to said system power ground.

4. The circuit for addressing the ESD of claim 3 wherein said first diode and said second diode are bidirectional transient suppression diodes.

5. The circuit for addressing the ESD of claim 4 wherein one end of said ESD handling circuit is electrically connected to said system and said transmitting circuit is disconnected from the other end of said ESD handling circuit when said transmitting circuit is connected to said transmitting interface.

6. The circuit for addressing the ESD of claim 5 wherein said transmitting circuit is connected to the other end of said ESD handling circuit when said transmitting circuit is disconnected from said transmitting interface.

7. The circuit for addressing the writing to ESD of claim 6 further comprising a bypass circuit comprising a first capacitor and a second capacitor, the ground terminal of the capacitive pen chip being connected to the system power ground through the first capacitor and the second capacitor, respectively.

8. An active capacitive pen, characterized in that it comprises the circuit for solving the problem of writing to generate ESD according to any one of claims 1 to 7.

9. The active capacitive pen of claim 8, wherein the active capacitive pen comprises a receiving interface, a transmitting interface, a capacitive pen securing device, and a capacitive pen housing, the capacitive pen securing device securing the receiving interface and the transmitting interface within the capacitive pen housing.

10. The active capacitive pen of claim 9, wherein the capacitive pen securing means further comprises a securing spring that secures the front end of the receiving interface and the front end of the transmitting interface in a front position on the capacitive pen housing.