CN220156599U - Pixel circuit of pulse sequence type image sensor, image sensor and device - Google Patents

Pixel circuit of pulse sequence type image sensor, image sensor and device Download PDF

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Publication number
CN220156599U
CN220156599U CN202223532655.2U CN202223532655U CN220156599U CN 220156599 U CN220156599 U CN 220156599U CN 202223532655 U CN202223532655 U CN 202223532655U CN 220156599 U CN220156599 U CN 220156599U
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voltage
pulse
module
voltage signal
buffer
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韩润泽
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Pulse Vision Beijing Technology Co ltd
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Pulse Vision Beijing Technology Co ltd
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Abstract

The embodiment of the utility model discloses a pixel circuit of a pulse sequence type image sensor, the image sensor and equipment, wherein the pixel circuit comprises: the optical pulse generation module is used for converting the optical signal into a pulse signal; the pulse width time integration module is connected with the light pulse generation module and is used for converting pulse interval time between two continuous pulse signals into corresponding first voltage signals; the voltage buffer module is connected with the pulse width time integration module and is used for buffering a second voltage signal meeting preset buffer conditions based on the first voltage signal output by the pulse width time integration module; and the buffer voltage output module is connected with the voltage buffer module and is used for outputting a second voltage signal. The embodiment of the utility model can lead the sensitization frequency of the pixels to be higher than the output frequency of the data, thereby effectively reducing the output data volume on the basis of guaranteeing the time sensitivity of the pixels and solving the problem of overlarge output data volume in the prior art.

Description

Pixel circuit of pulse sequence type image sensor, image sensor and device
Technical Field
The present utility model relates to image sensor technology, and more particularly, to a pixel circuit of a pulse sequence type image sensor, an image sensor, and a device.
Background
The pulse sequence type image sensor is used as a neuromorphic vision sensor, has the characteristic of high frame frequency, can meet the requirement of high-speed imaging, and can capture and record a high-speed moving target, so that the pulse sequence type image sensor has great application value in the aspects of machine vision, dynamic scene capture and the like, but in the related art, the pulse sequence type image sensor can face the problem of overlarge output data quantity if the pulse sequence type image sensor needs to realize high frame frequency.
Disclosure of Invention
The embodiment of the utility model provides a pixel circuit of a pulse sequence type image sensor, the image sensor and equipment, which are used for effectively reducing the output data quantity while ensuring high frame rate.
In one aspect of an embodiment of the present utility model, there is provided a pixel circuit of a pulse train image sensor, including:
the optical pulse generation module is used for converting the optical signal into a pulse signal;
the pulse width time integration module is connected with the light pulse generation module and is used for converting pulse interval time between two continuous pulse signals into corresponding first voltage signals;
the voltage buffer module is connected with the pulse width time integration module and used for buffering a second voltage signal meeting a preset buffer condition based on the first voltage signal output by the pulse width time integration module;
And the buffer voltage output module is connected with the voltage buffer module and is used for outputting the second voltage signal.
In another aspect of an embodiment of the present utility model, there is provided a pulse sequence type image sensor including:
the pixel circuits of the pulse sequence type image sensor provided by any one of the embodiments above, corresponding to each pixel respectively;
a bias current module for providing a constant current to the pixel circuit;
and the readout circuit is used for controlling the pixel circuits of the pulse sequence type image sensor corresponding to the pixels to output a second voltage signal.
In yet another aspect of an embodiment of the present utility model, there is provided an apparatus including: the pixel circuit of the pulse sequence type image sensor provided in any one of the above embodiments and/or the pulse sequence type image sensor provided in any one of the above embodiments.
According to the pixel circuit, the image sensor and the device of the pulse sequence type image sensor, the optical pulse generation module is used for converting the optical signals into the pulse signals, the pulse time integration module is used for converting the pulse interval time between two continuous pulse signals into the corresponding first voltage signals, the voltage buffer module is used for buffering the second voltage signals meeting the preset conditions, and the buffer voltage output module is used for outputting the second voltage signals, so that the photosensitive frequency of the pixel is higher than the output frequency of data, the output data quantity is effectively reduced on the basis of guaranteeing the time sensitivity of the pixel, and the problem that the output data quantity is overlarge in the prior art is solved.
The technical scheme of the utility model is further described in detail through the drawings and the embodiments.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the utility model and together with the description, serve to explain the principles of the utility model.
The utility model may be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
fig. 1 is a schematic diagram of a pixel circuit of a pulse sequence image sensor according to an exemplary embodiment of the present utility model;
fig. 2 is a schematic diagram of a pixel circuit of a pulse sequence image sensor according to another exemplary embodiment of the present utility model;
fig. 3 is a schematic diagram of a pixel circuit of a pulse sequence image sensor according to another exemplary embodiment of the present utility model;
FIG. 4 is a schematic diagram of an exemplary configuration of a pulse width time integration module 22 provided in accordance with an exemplary embodiment of the present utility model;
fig. 5 is a schematic diagram of a voltage buffer module 23 according to an exemplary embodiment of the present utility model;
fig. 6 is a schematic diagram of a pixel circuit of a pulse train image sensor according to still another exemplary embodiment of the present utility model;
Fig. 7 is a schematic diagram of a pixel circuit of a pulse train image sensor according to another exemplary embodiment of the present utility model;
FIG. 8 is a schematic diagram of a critical node voltage timing relationship provided by an exemplary embodiment of the present utility model;
fig. 9 is a schematic diagram of a pixel circuit of a pulse train image sensor according to still another exemplary embodiment of the present utility model;
fig. 10 is a schematic diagram of a pixel circuit of a pulse train image sensor according to still another exemplary embodiment of the present utility model;
fig. 11 is a schematic diagram of a pixel circuit of a pulse train image sensor according to still another exemplary embodiment of the present utility model;
fig. 12 is a schematic diagram of a pixel circuit of a pulse train image sensor according to still another exemplary embodiment of the present utility model;
fig. 13 is a schematic diagram of a pixel circuit of a pulse train image sensor according to still another exemplary embodiment of the present utility model;
FIG. 14 is a schematic diagram of a critical node voltage timing relationship provided by another exemplary embodiment of the present utility model;
FIG. 15 is a schematic diagram of simulation results of a pixel circuit according to an exemplary embodiment of the present utility model;
fig. 16 is a schematic diagram of a pulse train image sensor according to an exemplary embodiment of the present utility model;
FIG. 17 is a schematic diagram of an embodiment of an application of the electronic device of the present utility model;
fig. 18 is a schematic structural diagram of a pulse camera according to an exemplary embodiment of the present utility model.
Reference numerals:
10-an electronic device;
11-a processor;
12-memory;
13-an input device;
14-an output device;
pixel circuit of 20-pulse sequence type image sensor
A 21-light pulse generation module;
211-a fourth reset unit;
212-a photodiode;
213-a second comparator;
22-pulse width time integration module;
221-a bias current input unit;
222-a first capacitance;
223-an operational amplifier;
224-a first reset unit;
225-a bias current unit;
226-a second capacitance;
227-a second reset unit;
a 23-voltage buffer module;
23 a-a first voltage buffer unit;
231-a first gating unit;
232-a first judgment unit;
2321-a first source follower;
233-a first cache unit;
2331-a third capacitance;
234-a third reset unit;
235-voltage buffer;
236-fourth capacitance;
237-a fifth reset unit;
238-a sixth reset unit;
23 b-a second voltage buffer unit;
23b 1-a first cache subunit;
23b 2-a second cache subunit;
24-a buffer voltage output module;
24 a-a first output unit;
24 b-a second output unit;
241-first row select unit;
242-a second row selection unit;
243-a second source follower;
244-a third source follower;
245-a third comparator;
25-a time delay module;
30-pulse sequence type image sensor;
31-a bias current module;
a 32-readout circuit;
1201-lens;
1202-a pulse signal circuit;
1203-data processing circuitry;
1204-a non-volatile memory;
1205-power supply circuitry;
1206-volatile memory;
1207-control circuitry;
1208-I/O interface.
Detailed Description
Various exemplary embodiments of the present utility model will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present utility model unless it is specifically stated otherwise.
It will be appreciated by those of skill in the art that the terms "first," "second," etc. in embodiments of the present utility model are used merely to distinguish between different steps, devices or modules, etc., and do not represent any particular technical meaning nor necessarily logical order between them.
It should also be understood that in embodiments of the present utility model, "plurality" may refer to two or more, and "at least one" may refer to one, two or more.
It should also be appreciated that any component, data, or structure referred to in an embodiment of the utility model may be generally understood as one or more without explicit limitation or the contrary in the context.
In addition, the term "and/or" in the present utility model is merely an association relationship describing the association object, and indicates that three relationships may exist, for example, a and/or B may indicate: a exists alone, A and B exist together, and B exists alone. In the present utility model, the character "/" generally indicates that the front and rear related objects are an or relationship.
It should also be understood that the description of the embodiments of the present utility model emphasizes the differences between the embodiments, and that the same or similar features may be referred to each other, and for brevity, will not be described in detail.
Meanwhile, it should be understood that the sizes of the respective parts shown in the drawings are not drawn in actual scale for convenience of description.
The following description of at least one exemplary embodiment is merely exemplary in nature and is in no way intended to limit the utility model, its application, or uses.
Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification where appropriate.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further discussion thereof is necessary in subsequent figures.
Embodiments of the utility model are operational with numerous other general purpose or special purpose computing system environments or configurations with electronic devices, such as terminal devices, computer systems, servers, etc. Examples of well known terminal devices, computing systems, environments, and/or configurations that may be suitable for use with the terminal device, computer system, server, or other electronic device include, but are not limited to: personal computer systems, server computer systems, thin clients, thick clients, hand-held or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, network personal computers, minicomputer systems, mainframe computer systems, and distributed cloud computing technology environments that include any of the above systems, and the like.
Electronic devices such as terminal devices, computer systems, servers, etc. may be described in the general context of computer system-executable instructions, such as program modules, being executed by a computer system. Generally, program modules may include routines, programs, objects, components, logic, data structures, etc., that perform particular tasks or implement particular abstract data types. The computer system/server may be implemented in a distributed cloud computing environment in which tasks are performed by remote processing devices that are linked through a communications network. In a distributed cloud computing environment, program modules may be located in both local and remote computing system storage media including memory storage devices.
Summary of the utility model
In the process of realizing the utility model, the inventor finds that the pulse sequence type image sensor is used as a neuromorphic vision sensor, has the characteristic of high frame frequency, can meet the requirement of high-speed imaging, and can realize the capture and recording of a high-speed moving target, so that the pulse sequence type image sensor has great application value in the aspects of machine vision, dynamic scene capture and the like, but in the related art, the pulse sequence type image sensor can face the problem of overlarge output data quantity if the pulse sequence type image sensor needs to realize high frame frequency.
Exemplary overview
In the scene of recording information by a camera based on the pulse sequence type image sensor, the pixel circuit of the pulse sequence type image sensor can be used for outputting a voltage signal meeting the preset buffer condition according to the preset buffer condition, so that the sensitization frequency of pixels is higher than the output frequency of data, the output data volume is effectively reduced on the basis of ensuring the time sensitivity of the pixels, and the problem of overlarge output data volume in the prior art is solved.
Fig. 1 is a schematic diagram of a pixel circuit of a pulse train image sensor according to an exemplary embodiment of the present utility model. The pixel circuit of the pulse train image sensor (hereinafter referred to as a pixel circuit) may be applied to a pulse train image sensor. As shown in fig. 1, the pixel circuit includes: the device comprises an optical pulse generating module 21, a pulse width time integrating module 22, a voltage buffering module 23 and a buffering voltage output module 24.
An optical pulse generation module 21 for converting an optical signal into a pulse signal; a pulse width time integration module 22, connected to the optical pulse generation module 21, for converting the pulse interval time between two continuous pulse signals into corresponding first voltage signals; the voltage buffer module 23 is connected with the pulse width time integration module 22 and is used for buffering second voltage signals meeting preset buffering conditions based on each first voltage signal output by the pulse width time integration module 22; the buffer voltage output module 24 is connected with the voltage buffer module 23 and is used for outputting a second voltage signal.
The optical pulse generating module 21 may be implemented by any applicable circuit structure, for example, may include a photodiode and a comparator, and may further include a reset unit, for example, may be a reset transistor, where the photodiode senses light intensity when exposed, converts an optical signal into an electrical signal, so that a voltage at one end of the photodiode changes, and when the voltage reaches a threshold value, the comparator outputs a pulse signal, thereby converting the optical signal into the pulse signal. The pulse signal of the utility model refers to a high-level signal, and in practical application, the exposure intensity may be weaker, and if the condition of outputting the high-level signal is not met, a low-level signal may be output, and the low-level signal does not trigger the buffer function of the voltage buffer module.
The pulse width time integration module 22 may generally implement integration based on an integrator, such as a capacitor, which may be specifically set according to practical requirements. The pulse width time integrating module 22 integrates the pulse interval time between two continuous pulse signals according to a fixed speed, when the light intensity is large, the light pulse generating module 21 can generate the pulse signals in a shorter time, so that the pulse interval time between the pulse signals and the previous pulse signals is shorter, the integrating time of the pulse width time integrating module 22 is shorter, the voltage (namely the first voltage signal) at one end of the integrator after integration is larger, and therefore the voltage can be used for representing the intensity degree of the light intensity, and the pulse interval time between the two continuous pulse signals is converted into the corresponding first voltage signal.
It should be noted that, in order to ensure that the pwm integration module 22 can integrate at a fixed rate, a constant bias current needs to be provided to the pwm integration module 22, and the specific providing manner may be set according to practical requirements.
The voltage buffer module 23 may buffer the voltage signal in any implementation manner, for example, voltage buffer based on capacitance, or may also buffer in other manners, which may be specifically set according to actual requirements. The preset buffer condition can also be set according to actual requirements, for example, the preset buffer condition is a voltage signal corresponding to the maximum light intensity in a preset period, for example, the preset buffer condition is that the exposure intensity is changed relative to the previous exposure, and the like.
The specific structure of the buffer voltage output module 24 may be set according to actual requirements, so long as the buffer voltage output module 23 can output the second voltage signal in the preset period, and may also output other signals according to actual requirements, for example, if the exposure intensity changes, a high-level pulse is output, which may be specifically set according to actual requirements.
In practical application, the pixel circuits corresponding to each pixel may be set according to the number of pixels of the sensor in the pulse sequence image sensor, and the readout circuit controls the pixel circuits corresponding to each pixel respectively, so as to read out the second voltage signal meeting the preset buffer condition.
According to the pixel circuit of the pulse sequence type image sensor provided by the embodiment of the utility model, the optical pulse generation module is used for converting the optical signal into the pulse signal, the pulse time integration module is used for converting the pulse interval time between two continuous pulse signals into the corresponding first voltage signal, the voltage buffer module is used for buffering the second voltage signal meeting the preset buffer condition, and the buffer voltage output module is used for outputting the buffered second voltage signal, so that the sensitization frequency of the pixel is higher than the output frequency of the data, the output data volume is effectively reduced on the basis of ensuring the time sensitivity of the pixel, and the problem of overlarge output data volume in the prior art is solved.
Fig. 2 is a schematic diagram of a pixel circuit of a pulse train image sensor according to another exemplary embodiment of the present utility model.
In an alternative embodiment, the voltage buffer module 23 includes: the first voltage buffer unit 23a is configured to buffer, based on each first voltage signal output by the pulse width time integration module in a preset period, a second voltage signal corresponding to a maximum light intensity in the preset period; the buffer voltage output module 24 includes: the first output unit 24a is configured to output a second voltage signal when reaching an end time of a preset period.
In order to further reduce the output data amount of the image sensor, the embodiment sets a preset period as an output period, where the duration of the preset period may be set according to actual needs, for example, the preset period needs to include at least two exposure periods, which is not limited in particular. Each exposure, if a pulse signal can be generated, a first voltage signal can be generated, a plurality of first voltage signals may be generated in a preset period, the voltage buffer module 23 only buffers the voltage signal corresponding to the maximum value in the first voltage signal generated currently in the current period after each exposure, the buffered voltage signal may be the first voltage signal of the maximum value, or may be the voltage signal of the maximum value after certain consumption, for example, when a certain device judges whether the first voltage signal generated currently needs to be buffered, the device itself needs to consume a certain voltage, the first voltage signal is reduced by a certain amount after passing through the device, so that the buffered voltage signal can be smaller than the first voltage signal of the current maximum value, and because the consumption of the judging device is fixed, compared with the first voltage signal, the buffered voltage signal can also represent the magnitude of the exposure intensity, and based on this, when a time of a preset period is completed, the voltage buffer module 23 buffers the voltage signal corresponding to the maximum light intensity in the preset period, and the voltage signal is called as a second voltage signal.
The specific structure of the buffer voltage output module 24 may be set according to actual requirements, so long as the buffer voltage output module 23 can output a second voltage signal in a preset period, for example, the buffer voltage output module 24 may include a source follower and a row selection tube, the row selection tube is controlled by a peripheral readout circuit, when the readout circuit detects that the readout circuit has reached the end time of one preset period currently, the readout circuit controls the row selection tube to be turned on (or called to be turned on) so as to characterize that the pixel is selected to be output, and the source follower is used for following the buffered second voltage signal to realize outputting the second voltage signal to the readout circuit.
The pixel circuit of this embodiment may select, through the row and column, a second voltage signal corresponding to a maximum light intensity of a pixel to be read out in a preset period, and be used to characterize the maximum light intensity felt by the pixel in the preset period.
According to the pixel circuit of the pulse sequence type image sensor, the optical pulse generating module is used for converting an optical signal into a pulse signal, the pulse time integrating module is used for converting pulse interval time between two continuous pulse signals into a corresponding first voltage signal, the voltage buffering module is used for buffering a second voltage signal corresponding to the first voltage signal with the maximum light intensity in a preset period, and the buffer voltage output module is used for outputting the buffered second voltage signal with the maximum light intensity after the preset period is finished, so that the photosensitive frequency of a pixel is higher than the output frequency of data, the output data quantity is effectively reduced on the basis of guaranteeing the time sensitivity of the pixel, and the problem that the output data quantity is overlarge in the prior art is solved.
Fig. 3 is a schematic diagram of a pixel circuit of a pulse train image sensor according to another exemplary embodiment of the present utility model.
In one alternative example, the pulse width time integration module 22 includes: a bias current input unit 221, a first capacitor 222, and an operational amplifier 223.
A bias current input unit 221 for outputting a first constant current; the first end of the first capacitor 222 is connected with the bias current input unit 221, and the first capacitor 222 is used for charging under the action of a first constant current in the pulse interval time; the operational amplifier 223 has a first input terminal connected to the bias current input unit 221 and a first terminal of the first capacitor 222, a first output terminal connected to a second terminal of the first capacitor 222, a second input terminal for inputting a first reference voltage, and a first output terminal for outputting a first voltage signal after the first capacitor 222 is charged for a pulse interval time.
Wherein Vref1 represents a first reference voltage, I1 represents a first constant current, and when the light signal in the light pulse generating module 21 is accumulated to a certain threshold during exposure, a pulse signal is output, and between the two pulse signals, the first constant current I1 charges the first capacitor 222 to convert the pulse interval into a voltage signal. Specifically, the operational amplifier 223 fixes the voltage at the first end of the first capacitor 222 at the first reference voltage, when the first capacitor 222 is not charged, the voltage at the second end of the first capacitor 222 is the first reference voltage, when the first capacitor 222 is charged, the first end voltage is fixed, as the first end of the first capacitor 222 is charged, the electrode plate at the first end of the first capacitor 222 is positively charged, the electrode plate at the second end is negatively charged, so that the voltage Vc at the second end of the first capacitor 222 drops from the first reference voltage Vref1 at a fixed rate, for example, to V1, then V1 is the first voltage signal, the light pulse generating module 21 outputs the pulse signal, the voltage buffering module 23 is triggered to enter the buffering stage, the voltage buffering module 23 buffers the voltage at 0, and after the pulse signal is generated during the preset period for the first time, the buffering voltage signal corresponding to V1 is buffered to the voltage buffering module 23 based on the first voltage signal V1 output by the time integration module 22. After the buffering is finished, the first capacitors 222 of the light pulse generating module 21 and the pulse width time integrating module 22 are triggered to reset, and the mode of triggering the resetting can be set according to actual requirements, for example, pulse signals are transmitted to the light pulse generating module 21 and the pulse width time integrating module 22 after being delayed for a certain time to trigger the resetting, and the mode can be specifically set according to the actual requirements. After reset, the first capacitor 222 starts to charge again, the optical pulse generating module generates a second pulse signal through the second exposure, the voltage Vc at the second end of the first capacitor 222 decreases to V2 when the second pulse signal is generated, if the second exposure light intensity is greater than the first exposure, the optical pulse generating module generates the second pulse signal in a shorter time, so that the pulse interval time between the second pulse signal and the first pulse signal is shorter than the pulse interval time between the first pulse signal and the previous pulse signal, the integration time of the first capacitor 222 is also shorter, so that the Vc decreases to a small extent, V2 is greater than V1, and the voltage buffer module 23 buffers the buffer voltage signal corresponding to V2. Conversely, if the light intensity of the second exposure is smaller than that of the first exposure, V2 is smaller than V1, and V2 is not buffered, so that the voltage signal buffered by the voltage buffer module 23 at any time is the voltage signal corresponding to the maximum light intensity generated in the current preset period, and when the preset period is over, the voltage buffer module 23 buffers the second voltage signal corresponding to the maximum light intensity in the preset period.
According to the utility model, the bias current input unit is used for providing constant current for the first capacitor, so that the first capacitor can be charged at a fixed rate, and then the operational amplifier is combined, so that the first voltage signal of the second end voltage Vc of the first capacitor after the charging is completed can represent the exposure intensity, the voltage signal corresponding to the maximum light intensity in a preset period is conveniently cached in the follow-up step, the second voltage signal corresponding to the maximum light intensity in the preset period can be output at the end time of the preset period, and the output data quantity of the pixel circuit is effectively reduced.
In an alternative example, the pulse width time integration module 22 further includes: the first reset unit 224 is connected to the light pulse generating module 21 and the first and second ends of the first capacitor 222, respectively, and is configured to reset the first capacitor under the action of the pulse signal.
The first reset unit 224 may adopt any practical reset structure, for example, a reset transistor, where a gate of the reset transistor is connected to the light pulse generating module 21, so that the reset transistor is turned on under the action of a pulse signal, and the first capacitor 222 is discharged to reset to an uncharged state.
Optionally, the pulse signal used for triggering the first reset unit 224 to be turned on may be a signal generated by the optical pulse generating module 21 after a certain delay, so as to provide enough time for the buffering of the voltage buffering module 23, and ensure the accuracy of the buffering result of the voltage buffering module 23.
The first capacitor is reset through the reset unit, so that the first capacitor can be repeatedly used for converting new pulse interval time into the voltage signal, and the output first voltage signal is ensured to be accurate and effective.
Fig. 4 is a schematic diagram of an exemplary configuration of the pulse width time integration module 22 according to an exemplary embodiment of the present utility model.
In one alternative example, the pulse width time integration module 22 includes: a bias current unit 225 for supplying a second constant current; the first end of the second capacitor 226 is connected with the bias current unit 225, the voltage of the second end is set to be a second reference voltage, the second capacitor 226 is used for charging under the action of a second constant current in the pulse interval time, and after the charging in the pulse interval time is completed, the first end of the second capacitor 226 outputs a first voltage signal; the second reset unit 227 is connected to the light pulse generating module 21 and the first and second ends of the second capacitor 226, respectively, and is configured to reset the second capacitor 226 under the action of the pulse signal.
Wherein Vref2 represents a second reference voltage, I2 represents a second constant current, and at a pulse width interval, the second constant current I2 charges the second capacitor 226, so that the second end electrode plate of the second capacitor is positively charged, and the first end electrode plate is negatively charged, and since the second end voltage of the second capacitor 226 is the fixed second manipulation voltage Vref2, the first end voltage of the second capacitor 226 is a variable Vc, and as the second capacitor 226 is continuously charged, vc decreases from Vref2 to a certain value, such as V1 or V2, as described above, at a fixed rate, and the voltage Vc (the decreased value) of the first end of the charged second capacitor 226 is outputted as the first voltage signal. The specific structure and operation principle of the second reset unit 227 are similar to those of the first reset unit 224 described above, and will not be described again here. The bias current unit 225 may employ any practicable device as long as it can supply the second capacitor 226 with the required second constant current I2.
The utility model realizes the conversion from the pulse interval time of the pulse width time integration module to the voltage signal based on the bias current unit, the second reset unit and the second capacitor, and compared with the previous example, the utility model saves the operational amplifier, thereby reducing the cost and the circuit area.
In an alternative example, the voltage buffer module 23 includes: a first gating unit 231, a first judging unit 232, and a first buffer unit 233.
The first gating unit 231 is respectively connected with the light pulse generating module 21 and the pulse width time integrating module 22 and is used for conducting under the action of a pulse signal; a first judging unit 232 connected to the first gating unit 231, for determining whether the first voltage signal needs to be buffered when the first gating unit 231 is turned on; the first buffer unit 233 is connected to the first judging unit 232, and is configured to buffer the buffer voltage signal corresponding to the first voltage signal in response to the first voltage signal needing buffering, and buffer the buffer voltage signal to be the second voltage signal after reaching the end time of the preset period.
The first gating unit 231 may be any gating device, for example, a gate tube, where a gate of the gate tube is connected to the light pulse generating module 21, and after the light pulse generating module 21 generates a pulse signal, the pulse signal triggers the gate tube to be turned on, and outputs the first voltage signal generated by the pulse width time integration module 22 to the first judging unit 232. The first determining unit 232 may be implemented by any applicable device, so long as it can determine whether to buffer the first voltage signal based on the voltage signal currently buffered by the first buffer unit 233 and the first voltage signal. For example, the first determining unit 232 may be implemented by a source follower or a comparator, which may be specifically set according to actual requirements, and the embodiment is not limited. The first buffer unit 233 may be any device having a buffer function, for example, a capacitor device, and may be specifically set according to actual requirements. When the first judging unit 232 determines that the first voltage signal needs to be buffered, the buffered voltage signal corresponding to the first voltage signal is buffered to the first buffer unit 233, for example, the capacitor is charged by the first voltage signal, so that the capacitor voltage is equal to the buffered voltage signal corresponding to the first voltage signal. The buffered buffer voltage signal may be equal to or less than the first voltage signal, and is specifically determined according to a specific device of the first determining unit 232, for example, when the first determining unit 232 adopts a source follower, because there is a certain threshold voltage consumption between the gate and the source of the source follower, the buffered buffer voltage signal is equal to the difference between the first voltage signal and the gate-source threshold voltage signal of the source follower. When the first determining unit 232 does not need to consume, the first voltage signal may be directly buffered in the first buffer unit 233, for example, by charging the capacitor to make the capacitor voltage equal to the voltage corresponding to the first voltage signal.
According to the utility model, the first gating unit is used for conducting the buffer of the trigger voltage signal under the action of the pulse signal, the first judging unit is combined to judge whether the buffer of the first voltage signal is needed, the buffer voltage signal is ensured to be the voltage signal corresponding to the maximum light intensity generated in the current period, and when the buffer is needed, the buffer of the buffer voltage signal corresponding to the first voltage signal is realized through the first buffer unit, so that the buffer of the second voltage signal corresponding to the maximum light intensity in the preset period is ensured when the preset period is finished.
In an alternative example, the voltage buffer module 23 further includes: and a third reset unit 234 connected to the peripheral readout circuit, the first terminal and the second terminal of the first buffer unit 233, respectively, for resetting the first buffer unit 233 after outputting the second voltage signal every preset period.
The specific structure and principle of the third reset unit 234 may be set according to actual requirements, and referring to the foregoing first reset unit 224, in this example, the triggering of the third reset unit 234 is controlled by a readout circuit, and after the readout circuit detects that the end time of the preset period is reached, the second voltage signal is read from the buffer voltage output module 24, the third reset unit 234 may be controlled to reset the first buffer unit 233, so that the first buffer unit 233 can enter the voltage buffer of the next period.
According to the utility model, the first buffer unit is reset after each preset period is finished, so that the first buffer unit can be repeatedly used for voltage buffer of a new period, further, the pixel circuit can continuously output a second voltage signal corresponding to the maximum light intensity in each period, and the continuous normal operation of the image sensor is ensured.
Fig. 5 is a schematic diagram of a voltage buffer module 23 according to an exemplary embodiment of the present utility model.
In an alternative example, the first determining unit 232 includes a first source follower 2321, and the first buffer unit 233 includes a third capacitor 2331; a first end of the first source follower 2321 is connected with the first gating unit 231, a second end of the first source follower 2321 is connected with a first end of the third capacitor 2331, a third end of the first source follower 2321 is connected with a preset power supply, so that the voltage of the third end is a preset voltage, and a second end of the third capacitor 2331 is grounded; the first source follower 2321 is configured to charge the third capacitor 2331 based on the first voltage signal if a difference between the first voltage signal at the first end and the current voltage signal at the second end is greater than a first threshold voltage of the first source follower 2321 when the first gating unit 231 is turned on, so that the third capacitor 2331 caches a buffered voltage signal corresponding to the first voltage signal.
Wherein Vpulse represents a pulse signal, vdd represents a preset voltage provided by a preset power supply, the first judging unit 232 is implemented by a first source follower 2321, and the first buffer storage unit 233 is implemented by a third capacitor 2331. The second end of the third capacitor 2331 is grounded, the first end of the third capacitor 2331 is connected to the second end (source) of the first source follower 2321, the first end (gate) of the first source follower 2321 is connected to the first gate unit 231, when the first gate unit 231 is turned on, the first end of the first source follower 2321 inputs a first voltage signal, before the first voltage signal is input, the voltage at the second end of the first source follower 2321 is the voltage Vout buffered by the third capacitor 2331, after the first voltage signal is input, if the difference between the first voltage signal (such as vc=v1) and Vout is greater than the first threshold voltage Vt of the first source follower 2321, the third capacitor 2331 is triggered to be charged, so that Vout is a buffered voltage signal corresponding to the current maximum light intensity buffered by the third capacitor 2331, and as the number of times of exposure increases, the buffered voltage signal corresponding to the maximum light intensity is ensured to be always equal to the voltage Vout buffered by the first voltage signal, and the buffered voltage Vout is ensured to be the preset period corresponding to the preset light intensity signal when the preset period is the preset. If the current first voltage signal is smaller than the previous first voltage signal, the current exposure light intensity is smaller than the previous light intensity, so that the difference between the gate voltage and the source voltage of the first source follower 2321 cannot meet the gate-source threshold voltage Vt of the first source follower 2321, and therefore the third capacitor 2331 cannot be charged, so that the third capacitor 2331 keeps buffering the buffer voltage signal corresponding to the previous higher light intensity.
According to the utility model, the judgment of whether the first voltage signal is cached or not is realized through the source follower, and the caching of the voltage signal with the maximum light intensity in the period is realized by combining with the capacitor charging, so that the pixel circuit can output the second voltage signal corresponding to the maximum light intensity in the period, and the output data quantity is further reduced.
In an alternative example, the third reset unit 234 is connected to the peripheral readout circuit, the first terminal and the second terminal of the third capacitor, respectively, and is configured to reset the third capacitor 2331 after outputting the second voltage signal every preset period.
Wherein Vrst represents the control voltage of the third reset unit 234, which is controlled by the readout circuit, when the third capacitor 2331 needs to be reset, vrst is controlled to be at a high level, so that the third reset unit 234 is turned on, and the third capacitor 2331 is discharged, so that the third capacitor 2331 is reset to an uncharged state, and after the reset is completed, vrst is controlled to be at a low level, so that the third reset unit 234 is turned off, and preparation is made for the next preset period of the third capacitor 2331 by charging the buffer voltage signal. Specifically, the readout circuit is responsible for detecting whether the end time of the preset period is reached, and when the end time of the preset period is detected, the control buffer voltage output module 24 outputs the second voltage signal buffered by the voltage buffer module 23, and after the readout circuit reads the second voltage signal, the third reset unit 234 is controlled to be turned on by controlling the state of Vrst, so as to reset the third capacitor 2331.
According to the utility model, the third capacitor is periodically reset through the third reset unit, so that the third capacitor can be repeatedly used for voltage buffering of a new period, further, the pixel circuit can continuously output a second voltage signal corresponding to the maximum light intensity in each period, and the continuous normal operation of the image sensor is ensured.
In an alternative example, the first determining unit 232 may also be implemented by a comparator, for example, the first determining unit 232 is a first comparator, two input ends of the first comparator are respectively connected to the first gating unit and the second end of the third capacitor, the first voltage signal newly generated by the pulse width time integrating module is compared with the current voltage of the third capacitor, and when the first voltage signal is greater than the current voltage of the third capacitor, the third capacitor is controlled to be charged based on the first voltage signal, so that the voltage signal corresponding to the new greater light intensity is buffered to the third capacitor.
In one alternative example, the buffer voltage output module 24 includes: a first row selection unit 241, a second row selection unit 242, a second source follower 243, and a third source follower 244.
A first row selection unit 241 for being turned on or off under the control of a peripheral readout circuit; a second row selection unit 242 for being turned on or off under control of the readout circuit; the second source follower 243 has a first end connected to the voltage buffer module 23, a second end connected to the first row selection unit 241, and a third end connected to a preset power source, and the second source follower 243 is configured to output the second voltage signal buffered by the voltage buffer module 23 to the readout circuit when the first row selection unit 241 is turned on; the third source follower 244 has a first end connected to the light pulse generating module 21, a second end connected to the second row selecting unit 242, and a third end connected to a preset power source, and the third source follower 244 is configured to output a third voltage signal of the photodiode in the light pulse generating module 21 to the readout circuit when the second row selecting unit 244 is turned on.
Wherein Vdd represents a preset voltage provided by a preset power supply, the second source follower 243 and the third source follower 244 operate in a similar manner to the first source follower, and will not be described herein. The first row selecting unit 241 and the second row selecting unit 242 may be implemented by using a gate tube, taking the first row selecting unit 241 as an example, where the gate electrode is connected to the controllable voltage Vs1, and the readout circuit detects that the pulse signal is generated in the current preset period, then the controllable voltage Vs1 of the first row selecting unit 241 may be controlled to be at a high level, so that the first row selecting unit 241 is turned on, and the second source follower 243 transmits the second voltage signal buffered by the voltage buffering module 23 to the readout circuit through the bus, so that the readout circuit finishes reading the second voltage signal of the pixel circuit, and other pixels are similar and are not repeated one by one. When the readout circuit detects that the pulse signal is not generated within the current preset period, the buffering result in the voltage buffering module 23 is 0, the readout circuit may control the gate controllable voltage Vs2 of the second row selection unit 242 to be at a high level, and keep the gate controllable voltage Vs1 of the first row selection unit 241 at a low level, so as to indicate that the second row selection unit 242 is selected, and the gate of the third source follower 244 connected to the second row selection unit 242 is connected to the optical pulse generation module 21, so that the third voltage signal of the photodiode of the optical pulse generation module 21 is output to the readout circuit through the column bus.
The utility model realizes that if pulse signals are generated in any preset period, the second voltage signal corresponding to the maximum light intensity is read out, and if no pulse signals are generated, the third voltage signal of the photodiode can be read out, and the third voltage signal can be used for subsequent analysis of the change of the photodiode voltage, thereby improving the user experience.
Fig. 6 is a schematic diagram of a pixel circuit of a pulse train image sensor according to still another exemplary embodiment of the present utility model.
In an alternative example, the pixel circuit of the pulse train image sensor of the present utility model further includes: a delay module 25; the delay module 25 is connected to the light pulse generating module 21 and the pulse width time integrating module 22, and is configured to delay the pulse signal by a first time and then transmit the delayed pulse signal to the light pulse generating module 21 and the pulse width time integrating module 22, so as to reset the light pulse generating module 21 and the pulse width time integrating module 22.
The delay module 25 may be implemented in any implementation manner, for example, an inverter chain may be used to implement delay triggering reset of the pulse signal. Can be specifically set according to actual requirements.
The utility model delays the pulse signal generated by the light pulse generating module for a certain time and then uses the delayed pulse signal to trigger the reset of the light pulse generating module and the pulse width time integrating module, so as to ensure that the voltage caching module can successfully finish the voltage caching, thereby ensuring the accuracy and the effectiveness of the output second voltage signal.
In an alternative example, the light pulse generating module 21 includes: a fourth reset unit 211, a photodiode 212, and a second comparator 213.
The first end of the fourth reset unit 211 is connected with the output end of the delay module 25, the second end of the fourth reset unit 211 is connected with the second end of the photodiode 212, and the third end of the fourth reset unit 211 is connected with a preset power supply; a photodiode 212, the first end of which is grounded, the photodiode 212 being configured to convert an optical signal into an electrical signal, such that a voltage signal at the second end of the photodiode 212 varies with an exposure time; a second comparator 213 for comparing the voltage signal of the second terminal of the photodiode 212 with a second threshold voltage signal and outputting a pulse signal when the voltage signal of the second terminal of the photodiode 212 is equal to the second threshold voltage signal; the input end of the delay module 25 is connected to the output end of the second comparator 213, the output end of the delay module 25 is further connected to the first reset unit 224 of the pulse width time integration module 22, and the delay module 25 is configured to delay the pulse signal output by the second comparator 213 for a first time and then transmit the delayed pulse signal to the first reset unit 224 and the fourth reset unit 211, so as to reset the capacitance of the photodiode and the pulse width time integration module 22.
Wherein Vth represents the second threshold voltage signal, and Vdd represents a preset voltage provided by a preset power supply. The first time may be set according to actual requirements, and the first time setting principle is that the buffering time of the voltage buffering module 23 is longer than the buffering time of the voltage buffering module 23, so as to ensure that the voltage buffering module 23 can successfully complete buffering of the voltage signal, which is not limited in detail. The specific structure of the fourth reset unit 211 may be set according to actual requirements, and reference is made to the aforementioned first reset unit 224, which is not described herein again. The photodiode 212 may be any available photodiode, and may be specifically set according to practical requirements. After the reset, the first terminal voltage Vpd of the photodiode 212 is the reset voltage Vdd, when no pulse signal arrives at the fourth reset unit 211, the fourth reset unit 211 is turned off, and when the voltage buffer module 23 receives the optical signal, the optical signal is converted into an electrical signal, so that Vpd continuously drops from the reset voltage, when the voltage buffer module receives the optical signal and drops to Vth after a certain time, the second comparator 213 is triggered to output the pulse signal vpulse=vh (high level), the first gating unit 231 is turned on, and then the buffer stage, the time required for the buffer stage can be denoted as tw, the specific value of tw is determined according to the buffer device in the voltage buffer module 23, such as a capacitor, a certain time is required for charging, when the voltage buffer module 23 enters the reset stage after the buffer is completed, the integrated capacitor of the photodiode of the optical pulse generating module 21 and the pulse width time integrating module 22 resets, the specific value of the tr is determined according to the delay time of the delay module and the time required for the buffer stage, and since the delay time (the first time required for the delay stage is greater than the time required for the delay time tw), and the time required for the reset pulse width of the buffer module reaches the reset pulse width integrating module, and the pulse width of the reset pulse generating unit 21 and the reset pulse width of the reset unit 22 after the reset pulse is completed, the reset time of the reset pulse generating module and the reset pulse time of the first pulse generating module and the reset unit 211 reaches the reset time is required for the reset.
The utility model realizes that the optical pulse generating module converts the optical signal into the pulse signal through the photodiode, the second comparator and the fourth reset unit, thereby ensuring the continuous operation of the optical pulse generating module through reset and providing necessary support for the normal operation of the image sensor.
In an alternative example, the delay module 25 may also be a module in the light pulse generating module 21, and may be specifically set according to actual requirements.
In an alternative example, the delay module 25 may be implemented by an inverter chain, or may be implemented by other structures, for example, by a clock-based counter, and may specifically be set according to practical requirements, so long as the capacitor of the photodiode and the pulse width time integration module can be reset after delaying the pulse signal by a certain time.
In an alternative example, fig. 7 is a schematic structural diagram of a pixel circuit of a pulse train image sensor according to still another exemplary embodiment of the present utility model. Wherein col_bus represents a column bus, is connected to a readout circuit, C1 represents a first capacitor 222, vref represents a first reference voltage, SF0, SF1, SF2 represent a first source follower 2321, a second source follower 243, and a third source follower 244, respectively, C2 represents a third capacitor 2331, T1 represents a first gating unit 231, T2 represents a bias current input unit 221, T3 is a peripheral bias current introduction tube, id represents a constant current source, T3 is symmetrical to T2, and a first constant current I provided by the constant current source Id is input to a pulse width time integration module; row_sel indicates a Row selection unit, and the left side is the first Row selection unit 241 and the right side is the second Row selection unit 242; PD denotes a photodiode 212; r1 denotes a first reset unit 224, R2 denotes a third reset unit 234, and R3 denotes a fourth reset unit 211; the time delay module is realized by an inverter chain, in particular by cascading two inverters; vth corresponds to the second threshold voltage signal of the second comparator 213, and Vref corresponds to the first reference voltage of the operational amplifier 223. The working principle of each part is referred to the foregoing, and will not be described in detail herein.
Fig. 8 is a schematic diagram illustrating a voltage timing relationship of a key node according to an exemplary embodiment of the present utility model. Wherein V3 represents the value to which Vc after the third exposure C1 is charged falls, t1 represents the time required for the first exposure Vpd to reach Vth, t2 represents the time required for the second exposure Vpd to reach Vth, and t3 represents the time required for the third exposure Vpd to reach Vth; the specific meaning of each symbol is referred to in the foregoing, and will not be described in detail herein. In the time t1, vc decreases from Vref to V1 at a fixed rate and Vpd reaches Vth, vpulse changesIs high level (pulse signal), triggers T1 to conduct, enters into a buffer stage, charges V1 to V1-Vt through a source follower SF0, then SF0 is cut off, C2 is not charged, and the time required by the buffer stage is tw (i.e. T w ) Then enter the reset phase, reset Vpd and Vc, the time needed by the reset phase is t r (i.e., tr), the above-described process is repeated, and if the light is increased at the time of the second exposure, the time required for Vpd to reach Vth is shortened, and the magnitude of Vc drop becomes smaller, i.e., V2>V1, then the gate-source voltage of source follower SF0 is greater than its threshold voltage Vt, source follower SF0 turns on, charging Vout to V2-Vt. If the light is reduced in the third exposure, V3 <V2, then the gate-source voltage of source follower SF0 is less than its threshold voltage Vt, source follower SF0 is turned off, vout will continue to remain at V2-Vt. After a readout period (preset period) is completed, the buffered voltage on Vout indicates the strongest light intensity in that period.
Fig. 9 is a schematic diagram of a pixel circuit of a pulse train image sensor according to still another exemplary embodiment of the present utility model.
In an alternative embodiment, the voltage buffer module 23 includes: the second voltage buffer unit 23b is configured to determine a current second voltage signal based on the first voltage signal output by the pulse width time integration module 22, and buffer the current second voltage signal as a new second voltage signal. The buffer voltage output module 24 includes: and a second output unit 24b for outputting the buffered second voltage signal satisfying the preset condition.
Wherein the current second voltage signal may be a difference between the buffered second voltage signal and a current integration value, the current integration value is an integration value of the pulse width time integration module 22 in a current last exposure time, and the second voltage signal buffered by the voltage buffer module 23 after the pulse width time integration module 22 is reset after the first exposure is exemplified as follows V ref Represents the reference voltage, t 1 Represents the integration time of the first capacitor 222 at the first exposure, I c Representing the charging current to the first capacitor, etcAt the first constant current I1, C 1 Representing the capacitance value of the first capacitor, the second exposure, the integration amount of the pulse width time integration module 22 is +.>t 2 Indicating the integration time of the first capacitor 222 during the second exposure, the second voltage signal is +.> The buffering of the second voltage signal may be realized by means of a capacitor. The preset condition may be the difference between the buffered second voltage signal and the reference voltage (e.g.)>) If the absolute value of the difference is not 0 or is greater than the threshold, the buffer voltage output module 24 may output a buffered second voltage signal that satisfies the preset condition, where it can be seen that the difference between the second voltage signal and the reference voltage characterizes the intensity of the second exposure relative to the intensity of the first exposure, when the difference is greater than 0, the intensity of the second exposure is greater than the first exposure, and when the difference is less than 0, the intensity of the second exposure is less than the first exposure. And outputting the buffered second voltage signal when the difference value meets a preset condition.
In an alternative embodiment, the new second voltage signal and the reference voltage v can also be buffered ref And comparing, and outputting a target voltage signal used for representing that the latest exposure intensity changes relative to the previous exposure intensity or the change exceeds a threshold value in response to the comparison result meeting a preset condition, wherein the target voltage signal can be set according to actual requirements, for example, can be a high-level pulse, so that sparse pulses can be output along with continuous exposure.
Fig. 10 is a schematic diagram of a pixel circuit of a pulse train image sensor according to another exemplary embodiment of the present utility model.
In an alternative embodiment, the second voltage buffer unit 23b includes: the first buffer subunit 23b1 is configured to buffer, based on the first voltage signal output by the pulse width time integration module 22, a difference value between a current exposure and a pulse width time integration amount of a previous exposure corresponding to the first voltage signal as a new second voltage signal, or buffer a difference value between a previous exposure and a pulse width time integration amount of a current exposure as a new second voltage signal.
The current exposure refers to the last exposure, and the previous exposure refers to the exposure before the current exposure, for example, the current exposure is the third exposure, and the previous exposure is the second exposure. The pulse width time integration amount refers to an integration amount generated by the pulse width time integration module 22 during exposure, for example, the first capacitor of the pulse width time integration module charges at a fixed rate under the action of a constant current. For example, the pulse width time integration of the i-1 th exposure is The pulse width time integration amount of the ith exposure is +.>If the current exposure is the ith exposure, then +.>Or (b)As a new second voltage signal. The specific cache mode and the cache structure can be set according to actual requirements.
The embodiment realizes the buffer storage of the difference value of the pulse width time integral quantity of the two exposures, and is convenient for outputting sparse pulses with changed light intensity.
Fig. 11 is a schematic diagram of a pixel circuit of a pulse train image sensor according to still another exemplary embodiment of the present utility model.
In an alternative embodiment, the second voltage buffer unit 23b includes: the second buffer subunit 23b2 is configured to buffer, based on the first voltage signal output by the pulse width time integration module, the pulse width time integration amount of the current exposure corresponding to the first voltage signal as a new second voltage signal if it is determined that the pulse width time integration amount of the current exposure is different from the pulse width time integration amount of the previous exposure.
After the previous exposure, the pulse width time integral of the previous exposure can be cached, after the previous exposure, the pulse width time integral of the current exposure can be compared with the cached pulse width time integral of the previous exposure, whether the pulse width time integral of the current exposure is the same as the pulse width time integral of the previous exposure or not is determined, if the pulse width time integral of the current exposure is the same as the pulse width time integral of the previous exposure, the cached integral can be maintained, if the pulse width time integral of the current exposure is different, the pulse width time integral of the current exposure can be cached as a new second voltage signal, and a specific caching mode and a caching structure can be set according to actual requirements.
Exemplary, the pulse width time integration amount for the i-1 th exposure isThe pulse width time integration amount of the ith exposure is +.>If the current exposure is the ith exposure, it can be judged +.>Or->If 0, if not 0, it can be +.>As a new second voltage signal.
The embodiment realizes the buffer storage of the pulse width time integral quantity of the light intensity change, and is convenient for a user to know the light intensity change condition and output sparse pulses of the light intensity change.
Fig. 12 is a schematic diagram of a pixel circuit of a pulse train image sensor according to still another exemplary embodiment of the present utility model.
In an alternative embodiment, the voltage buffer module 23 includes: a voltage buffer 235 and a fourth capacitor 236; the buffer voltage output module 24 includes a third comparator 245.
The first input terminal of the voltage buffer 235 is connected to the pulse width time integration module 22, the second input terminal of the voltage buffer 235 is connected to the first output terminal of the voltage buffer 235, the first output terminal of the voltage buffer 235 is connected to the first terminal of the fourth capacitor 236, and the voltage buffer 235 is configured to transmit the first voltage signal to the first terminal of the fourth capacitor 236.
A second terminal of the fourth capacitor 236 is connected to the first input terminal of the third comparator 245, and the fourth capacitor 236 is configured to buffer the current second voltage signal as a new second voltage signal.
The second input end of the third comparator 245 is connected to a third reference voltage, and the third comparator 245 is configured to compare the new second voltage signal with the third reference voltage, and output a light intensity variation pulse signal if the comparison result meets a preset condition.
The voltage buffer module 23 is further configured to output a first voltage signal.
Wherein the voltage buffer 235 can be implemented in any practical structure and is operative to maintain the voltage V at the first output terminal thereof c2 ＝V c1 The first voltage signal output by the pulse width time integration module 22 is transmitted to the first end of the fourth capacitor 236. The third comparator 245 may be implemented in any practicable structure, and Vref3 represents the third reference voltage. The output of the light intensity change pulse signal indicates that the current exposure intensity is changed relative to the previous exposure intensity or the change quantity meets the preset condition. After the ith exposure is finished, vc2 is reduced to Vi along with Vc1, and Vc3 is obtained from the buffered second voltage signalBecome to buffer new second voltage signal +.>
In this embodiment, after each exposure is finished, the cached second voltage signal is updated once, and a new second voltage signal can be output, and a sparse pulse representing the exposure intensity change or the exposure intensity change meeting a certain condition can be output through the third comparator, so that the exposure intensity change condition can be conveniently known.
In an alternative embodiment, the circuit of the present utility model further comprises a delay module 25; the voltage buffer module further includes a fifth reset unit 237 and a sixth reset unit 238.
The delay module 25 is configured to delay the pulse signal output by the optical pulse generating module 21 by a first time and then transmit the delayed pulse signal to the sixth reset unit.
The fifth reset unit 237 is connected to the second terminal of the fourth capacitor 236 and the optical pulse generating module 21, and is configured to reset the voltage at the second terminal of the fourth capacitor 236 to the third reference voltage under the action of the pulse signal of the optical pulse generating module 21.
The sixth reset unit 238 is connected to the delay module 25, the second input terminal and the first output terminal of the voltage buffer 235, respectively, and is configured to reset the voltage of the first output terminal of the voltage buffer 235 to the third reference voltage under the action of the delayed pulse signal.
When the voltage at the first output terminal of the voltage buffer 235 is reset to the third reference voltage, the voltage at the second terminal of the fourth capacitor 236 becomes the third voltage, and the third voltage is buffered as a new second voltage signal.
The specific structure and operation principle of the fifth reset unit 237 and the sixth reset unit 238 are similar to those of the first reset unit 224, and are not described herein. After the exposure is finished and the second voltage signal and the sparse pulse are output, the fifth reset unit 237 is driven to be conducted by the pulse signal output by the optical pulse generating module 21, the second end voltage Vc3 of the fourth capacitor 236 is reset to the third reference voltage, the pulse signal is delayed by the delay module 25 for a first time to trigger the first reset unit 224 of the first capacitor and the sixth reset unit 238 of the voltage buffer 235 to be conducted, the first capacitor 222 and the voltage buffer 235 are reset, and the first output end voltage of the voltage buffer 235 is measured Is reset to the third reference voltage V ref3 Variation of resetting Vc2 at the same time>Is coupled to Vc3 such that Vc3 buffers a third voltage +.>As a buffered second voltage signal required at the next exposure. />
Fig. 13 is a schematic diagram illustrating a pixel circuit of a pulse train image sensor according to still another exemplary embodiment of the present utility model. Wherein Vref3 represents the third reference voltage, vref1 represents the first reference voltage, vref 3=vref 1, vc1 represents the output voltage of the operational amplifier 223 of the pulse width time integrating module 22, the output event detection result represents the light intensity variation pulse signal output by the third comparator, and the meaning of other symbols is referred to the foregoing, and will not be described in detail herein.
FIG. 14 is a schematic diagram of a critical node voltage timing relationship provided by another exemplary embodiment of the present utility model. Wherein, vref represents the third reference voltage Vref3, and the specific flow is as follows:
1. at the end of the first exposure, the exposure time of the first exposure is denoted as t 1 Determined by the characteristics of the photodiode and the exposure intensity,resetting Vc3, resetting Vc1 and Vc2, i.e. the buffered second voltage signal at the second exposure.
2. At the end of the second exposure, the exposure time is denoted as t 2 ，
3. The third comparator judges and decides whether to output the light intensity variation pulse signal.
4. And resetting Vc3, wherein Vc3=Vref 3.
5. Resetting Vc1 and Vc2, and Vc2=Vc1=Vref 3 simultaneously
6. The end of the third exposure time is reached,
7. vc3 is reset, vc1 and Vc2 are reset after delaying the first time,
fig. 15 is a schematic diagram of simulation results of a pixel circuit according to an exemplary embodiment of the present utility model. Wherein Vspike represents an inverse delay pulse signal output by the delay module, and the coefficient pulse is a light intensity variation pulse signal output by the third comparator. It can be seen that, after the exposure is finished, if the updated second voltage signal is near the third reference voltage, it indicates that the current light intensity and the previous light intensity variation do not meet the preset condition, so that the light intensity variation pulse signal is not output. Thereby reducing the amount of output data.
It should be noted that the foregoing embodiments or optional examples of the present utility model may be implemented separately, or may be implemented in any combination without conflict, and may be specifically set according to actual needs.
Fig. 16 is a schematic diagram of a pulse train image sensor according to an exemplary embodiment of the present utility model. The pulse sequence type image sensor may include: the pixel circuit 20 of the pulse sequence image sensor provided in any of the above embodiments or alternative examples, where each pixel corresponds to a respective pixel; a bias current module 31 for supplying a constant current to the pixel circuit; the readout circuit 32 is configured to control the pixel circuit 20 of the pulse train image sensor corresponding to each pixel to output the second voltage signal.
The specific structure of the pixel circuit 20 of the pulse sequence image sensor is referred to in the foregoing embodiments or alternative examples, and will not be described herein. The bias current module 31 may be set according to practical requirements, for example, referring to fig. 7, T3 and Id constitute a bias current module 31. Other embodiments may be used in practical applications, and the utility model is not limited thereto. The specific structure of the reading circuit can be based on the conventional reading circuit structure, the control function related to the utility model is added, and the specific structure can be set according to actual requirements.
Optionally, the readout circuit 32 is further configured to detect whether the ending time of the current preset period is reached, determine whether a pulse signal is generated in the current preset period when the ending time of the current preset period is detected, and control the pixel circuit 20 corresponding to each pixel to output the second voltage signal when the pulse signal is determined to be generated, and control the pixel circuit 20 to output the third voltage signal of the photodiode when the pulse signal is determined to be not generated in the current preset period, where the specific control principle is referred to the foregoing embodiment and is not described herein again.
In practical applications, the pulse sequence image sensor may also include other possible components, which are not limited by the present utility model.
In addition, the embodiment of the utility model also provides electronic equipment, which comprises: the pulse sequence type image sensor provided in any one of the embodiments above. The electronic device may further include: a memory for storing a computer program; and a processor for executing the computer program stored in the memory, and when the computer program is executed, processing the output signal of the pulse sequence image sensor according to any of the above embodiments of the present utility model is implemented to realize a desired function.
Fig. 17 is a schematic structural view of an application embodiment of the electronic device of the present utility model. As shown in fig. 17, the electronic device 10 includes one or more processors 11 and a memory 12, and the pulse train image sensor 30 provided by the foregoing embodiment.
The processor 11 may be a Central Processing Unit (CPU) or other form of processing unit having data processing and/or instruction execution capabilities, and may control other components in the electronic device to perform desired functions.
The memory 12 may store one or more computer program products, and the memory 12 may include various forms of computer-readable storage media, such as volatile memory and/or nonvolatile memory. The volatile memory may include, for example, random Access Memory (RAM) and/or cache memory (cache), and the like. The non-volatile memory may include, for example, read Only Memory (ROM), hard disk, flash memory, and the like. One or more computer program products may be stored on the computer readable storage medium that can be run by a processor to achieve the desired functionality described above.
In one example, the electronic device 10 may further include: an input device 13 and an output device 14, which are interconnected by a bus system and/or other forms of connection mechanisms (not shown).
In addition, the input device may include, for example, a keyboard, a mouse, and the like.
The output device 14 may output various information to the outside, including the determined distance information, direction information, and the like. The output means may include, for example, a display, speakers, a printer, and a communication network and remote output devices connected thereto, etc.
Of course, only some of the components of the electronic device relevant to the present utility model are shown in fig. 17 for simplicity, components such as buses, input/output interfaces, and the like being omitted. In addition, the electronic device may include any other suitable components depending on the particular application.
In another embodiment of the present utility model, an apparatus is provided, where the apparatus includes the pixel circuit of the pulse train image sensor and/or includes the pulse train image sensor and/or a chip having the pixel circuit of the pulse train image sensor.
Specifically, the apparatus includes at least one of: cameras, audio/video players, navigation devices, fixed location terminals, entertainment devices, smartphones, communication devices, mobile devices, vehicles or facilities, industrial devices, medical devices, security devices, flight devices, home appliances.
In embodiments of the present utility model, cameras include, but are not limited to, pulse cameras, high speed cameras, industrial inspection cameras, and the like. Cameras include, but are not limited to: vehicle-mounted camera, mobile phone camera, traffic camera, install camera, medical camera, security protection camera or household electrical appliances camera on can flying object.
Taking a pulse camera as an example, the device provided by the embodiment of the utility model is described in detail. Fig. 18 is a schematic structural diagram of a pulse camera according to an exemplary embodiment of the present utility model. As shown in fig. 18, the pulse camera includes: lens 1201, pulse signal circuit 1202, data processing circuit 1203, nonvolatile memory 1204, power supply circuit 1205, volatile memory 1206, control circuit 1207, and I/O interface 1208.
Wherein the lens 1201 is for receiving incident light from a subject, i.e., an optical signal.
A pulse signal circuit 1202 for converting an optical signal received through the lens 1201 into an electrical signal and generating a pulse signal from the electrical signal. The pulse signal circuit 1202 includes, for example, a pixel circuit of the pulse train type image sensor described above, and/or a chip having a pixel circuit of the pulse train type image sensor described above.
The data processing circuit 1203 is configured to control a pulse signal reading process, and the data processing circuit 1203 includes, for example: an arithmetic processing unit (e.g., CPU) and/or an image processing unit (GPU), for example, controls a pulse signal readout process of the pulse signal readout circuit, controls a readout row selector therein to transmit a row readout signal, resets the row selector to transmit a column reset signal, and the like.
1206 is a volatile memory, such as a Random Access Memory (RAM), 1204 is a non-volatile memory device, such as a Solid State Disk (SSD), hybrid Hard Disk (HHD), secure Digital (SD) card, mini SD card, or the like.
In an embodiment of the present invention, the pulse camera further includes: and the display unit is used for carrying out real-time/playback display on the pulse signal/image information. The pulse camera according to the embodiment of the present invention may further include at least one of the following: wired/wireless transmission interfaces, such as WiFi interfaces, bluetooth interfaces, usb interfaces, RJ45 interfaces, mobile Industry Processor Interfaces (MIPI) interfaces, low Voltage Differential Signaling (LVDS) interfaces, and other interfaces with wired or wireless transmission capabilities.
The pulse camera provided by the embodiment of the invention can be used for detecting visible light, infrared light, ultraviolet light, X rays and the like, and can be applied to various scenes, and common scenes comprise but are not limited to:
the camera can be used as a vehicle-mounted camera to be installed in various vehicles or facilities, for example, used for information acquisition and control of vehicle-road coordination, intelligent traffic and automatic driving. For example, as a high-speed rail travel recorder installed in a rail vehicle such as a high-speed rail or on a rail traffic line; it may also be installed in an autonomous vehicle or a vehicle equipped with an Advanced Driving Assistance System (ADAS), for example, to detect and alert information of a vehicle, a pedestrian, a lane, a driver, or the like.
The camera can be used as a traffic camera to be installed on a traffic signal rod for shooting, early warning, cooperative control and the like of vehicles and pedestrians on urban roads and expressways.
Can be used as an industrial detection camera, for example, installed on a high-speed railway traffic line for high-speed railway line patrol and for high-speed railway safety detection; the method can also be used for detection, early warning and the like of specific industrial scenes such as coal mine conveyor belt fracture detection, substation arc detection, real-time detection of wind power generation blades, high-speed turbine non-stop detection and the like.
Is mounted on a flyable object, such as an airplane, satellite or the like, and is used for high-definition imaging of the object in a high-speed flight or even high-speed rotation scene.
Industry (machine vision in smart manufacturing, etc.), civilian (judicial evidence, sports penalties, etc.), and consumer electronics (cameras, video media, etc.).
Can be used as a medical camera for high-definition medical imaging in clinical diagnosis and treatment such as medical treatment, beauty treatment, health care and the like.
The camera can be used as a sports camera or a wearable camera, for example, a head-mounted camera or a camera embedded in a wristwatch, and can be used for shooting scenes of various sports fields, daily leisure sports and the like.
The camera can also be used as a security camera, a mobile phone camera or a household appliance camera and the like.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams or flowchart illustration, and combinations of blocks in the block diagrams or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The basic principles of the present utility model have been described above in connection with specific embodiments, however, it should be noted that the advantages, benefits, effects, etc. mentioned in the present utility model are merely examples and not intended to be limiting, and these advantages, benefits, effects, etc. are not to be considered as essential to the various embodiments of the present utility model. Furthermore, the specific details disclosed herein are for purposes of illustration and understanding only, and are not intended to be limiting, as the utility model is not necessarily limited to practice with the above described specific details.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different manner from other embodiments, so that the same or similar parts between the embodiments are mutually referred to. For system embodiments, the description is relatively simple as it essentially corresponds to method embodiments, and reference should be made to the description of method embodiments for relevant points.
The block diagrams of the devices, apparatuses, devices, systems referred to in the present utility model are only illustrative examples and are not intended to require or imply that the connections, arrangements, configurations must be made in the manner shown in the block diagrams. As will be appreciated by one of skill in the art, the devices, apparatuses, devices, systems may be connected, arranged, configured in any manner. Words such as "including," "comprising," "having," and the like are words of openness and mean "including but not limited to," and are used interchangeably therewith. The terms "or" and "as used herein refer to and are used interchangeably with the term" and/or "unless the context clearly indicates otherwise. The term "such as" as used herein refers to, and is used interchangeably with, the phrase "such as, but not limited to.
It is also noted that in the apparatus, devices and methods of the present utility model, the components or steps may be disassembled and/or assembled. Such decomposition and/or recombination should be considered as equivalent aspects of the present utility model.
The previous description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present utility model. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects without departing from the scope of the utility model. Thus, the present utility model is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
The foregoing description has been presented for purposes of illustration and description. Furthermore, this description is not intended to limit embodiments of the utility model to the form disclosed herein. Although a number of example aspects and embodiments have been discussed above, a person of ordinary skill in the art will recognize certain variations, modifications, alterations, additions, and subcombinations thereof.

Claims (19)

1. A pixel circuit of a pulse train image sensor, comprising:
The optical pulse generation module is used for converting the optical signal into a pulse signal;
the pulse width time integration module is connected with the light pulse generation module and is used for converting pulse interval time between two continuous pulse signals into corresponding first voltage signals;
the voltage buffer module is connected with the pulse width time integration module and used for buffering a second voltage signal meeting a preset buffer condition based on the first voltage signal output by the pulse width time integration module;
and the buffer voltage output module is connected with the voltage buffer module and is used for outputting the second voltage signal.
2. The circuit of claim 1, wherein the voltage buffer module comprises:
the first voltage buffer unit is used for buffering a second voltage signal corresponding to the maximum light intensity in a preset period based on each first voltage signal output by the pulse width time integration module in the preset period;
the buffer voltage output module includes:
and the first output unit is used for outputting the second voltage signal when the ending time of the preset period is reached.
3. The circuit of claim 1, wherein the pulse width time integration module comprises:
A bias current input unit for outputting a first constant current;
the first end of the first capacitor is connected with the bias current input unit, and the first capacitor is used for charging under the action of the first constant current in the pulse interval time;
and the first input end of the operational amplifier is respectively connected with the bias current input unit and the first end of the first capacitor, the first output end of the operational amplifier is connected with the second end of the first capacitor, the second input end of the operational amplifier inputs a first reference voltage, and the first output end outputs the first voltage signal after the first capacitor finishes charging at the pulse interval time.
4. The circuit of claim 3, wherein the pulse width time integration module further comprises:
and the first reset unit is respectively connected with the light pulse generation module, the first end and the second end of the first capacitor and is used for resetting the first capacitor under the action of the pulse signal.
5. The circuit of claim 1, wherein the pulse width time integration module comprises:
a bias current unit for providing a second constant current;
the first end of the second capacitor is connected with the bias current unit, the voltage of the second end is set to be a second reference voltage, the second capacitor is used for charging under the action of the second constant current in the pulse interval time, and after the charging in the pulse interval time is completed, the first end of the second capacitor outputs the first voltage signal;
And the second reset unit is respectively connected with the light pulse generation module, the first end and the second end of the second capacitor and is used for resetting the second capacitor under the action of the pulse signal.
6. The circuit of claim 2, wherein the voltage buffer module comprises:
the first gating unit is respectively connected with the light pulse generating module and the pulse width time integrating module and is used for conducting under the action of the pulse signals;
the first judging unit is connected with the first gating unit and is used for determining whether the first voltage signal needs to be cached or not when the first gating unit is conducted;
the first buffer unit is connected with the first judging unit and is used for responding to the first voltage signal to be buffered, buffering the buffer voltage signal corresponding to the first voltage signal and enabling the buffer voltage signal to be the second voltage signal after reaching the end time of the preset period.
7. The circuit of claim 6, wherein the first determination unit comprises a first source follower and the first buffer unit comprises a third capacitor;
the first end of the first source follower is connected with the first gating unit, the second end of the first source follower is connected with the first end of the third capacitor, the third end of the first source follower is connected with a preset power supply, the voltage of the third end is a preset voltage, and the second end of the third capacitor is grounded;
And the first source follower is configured to charge the third capacitor based on the first voltage signal if a difference between the first voltage signal at the first end and the current voltage signal at the second end is greater than a first threshold voltage of the first source follower when the first gating unit is turned on, so that the third capacitor caches the cache voltage signal corresponding to the first voltage signal.
8. The circuit of claim 7, wherein the voltage buffer module further comprises:
and the third reset unit is respectively connected with the peripheral read-out circuit, the first end and the second end of the third capacitor and is used for resetting the third capacitor after outputting the second voltage signal in each preset period.
9. The circuit of claim 2, wherein the buffer voltage output module comprises:
a first row selection unit for being turned on or off under the control of a peripheral readout circuit;
a second row selection unit for being turned on or off under the control of the readout circuit;
the first end of the second source follower is connected with the voltage buffer module, the second end of the second source follower is connected with the first row selection unit, the third end of the second source follower is connected with a preset power supply, and the second source follower is used for outputting the second voltage signal buffered by the voltage buffer module to the readout circuit when the first row selection unit is conducted;
And the first end of the third source follower is connected with the light pulse generating module, the second end of the third source follower is connected with the second row selecting unit, the third end of the third source follower is connected with the preset power supply, and the third source follower is used for outputting a third voltage signal of a photodiode in the light pulse generating module to the reading circuit when the second row selecting unit is conducted.
10. The circuit of claim 1, further comprising: and the time delay module is respectively connected with the light pulse generation module and the pulse width time integration module and is used for delaying the pulse signal for a first time and then transmitting the delayed pulse signal to the light pulse generation module and the pulse width time integration module so as to reset the light pulse generation module and the pulse width time integration module.
11. The circuit of claim 10, wherein the light pulse generation module comprises:
the first end of the fourth reset unit is connected with the output end of the time delay module, the second end of the fourth reset unit is connected with the second end of the photodiode, and the third end of the fourth reset unit is connected with a preset power supply;
a photodiode, the first end of which is grounded, the photodiode being used for converting an optical signal into an electrical signal, so that a voltage signal of the second end of the photodiode changes with exposure time;
A second comparator for comparing a voltage signal of the second terminal of the photodiode with a second threshold voltage signal and outputting the pulse signal when the voltage signal of the second terminal of the photodiode is equal to the second threshold voltage signal;
the input end of the time delay module is connected with the output end of the second comparator, the output end of the time delay module is also connected with the first reset unit of the pulse width time integration module, and the time delay module is used for delaying the pulse signal output by the second comparator for a first time and then transmitting the delayed pulse signal to the first reset unit and the fourth reset unit so as to reset the photodiode and the capacitor of the pulse width time integration module.
12. The circuit of claim 1, wherein the voltage buffer module comprises:
the second voltage buffer unit is used for determining a current second voltage signal based on the first voltage signal output by the pulse width time integration module, and buffering the current second voltage signal as a new second voltage signal;
the buffer voltage output module includes:
and the second output unit is used for outputting the buffered second voltage signal meeting the preset condition.
13. The circuit of claim 12, wherein the second voltage buffer unit comprises:
and the first buffer subunit is used for buffering the difference value of the pulse width time integration quantity of the current exposure and the previous exposure corresponding to the first voltage signal as a new second voltage signal based on the first voltage signal output by the pulse width time integration module, or buffering the difference value of the pulse width time integration quantity of the previous exposure and the current exposure as a new second voltage signal.
14. The circuit of claim 12, wherein the second voltage buffer unit comprises:
and the second buffer subunit is used for buffering the pulse width time integration quantity of the current exposure as a new second voltage signal if the pulse width time integration quantity of the current exposure corresponding to the first voltage signal is different from the pulse width time integration quantity of the previous exposure based on the first voltage signal output by the pulse width time integration module.
15. The circuit of claim 12, wherein the voltage buffer module comprises: a voltage buffer and a fourth capacitor;
The buffer voltage output module comprises a third comparator;
the first input end of the voltage buffer is connected with the pulse width time integration module, the second input end of the voltage buffer is connected with the first output end of the voltage buffer, the first output end of the voltage buffer is connected with the first end of the fourth capacitor, and the voltage buffer is used for transmitting the first voltage signal to the first end of the fourth capacitor;
the second end of the fourth capacitor is connected with the first input end of the third comparator, and the fourth capacitor is used for caching the current second voltage signal as a new second voltage signal;
the second input end of the third comparator is connected with a third reference voltage, and the third comparator is used for comparing the new second voltage signal with the third reference voltage, and outputting a light intensity change pulse signal if the comparison result meets a preset condition;
the voltage buffer module is further configured to output the first voltage signal.
16. The circuit of claim 15, further comprising a delay module; the voltage buffer module further comprises a fifth reset unit and a sixth reset unit;
The time delay module is used for delaying the pulse signal output by the light pulse generation module for a first time and then transmitting the delayed pulse signal to the sixth reset unit;
the fifth reset unit is respectively connected with the second end of the fourth capacitor and the light pulse generation module and is used for resetting the voltage of the second end of the fourth capacitor to the third reference voltage under the action of the pulse signal;
the sixth reset unit is respectively connected with the time delay module, the second input end and the first output end of the voltage buffer and is used for resetting the voltage of the first output end of the voltage buffer to the third reference voltage under the action of the delayed pulse signal;
when the voltage of the first output end of the voltage buffer is reset to the third reference voltage, the voltage of the second end of the fourth capacitor becomes a third voltage, and the third voltage is used as a new second voltage signal to be buffered.
17. A pulse train image sensor, comprising:
a pixel circuit of the pulse sequence image sensor according to any one of claims 1 to 16, wherein each pixel corresponds to a respective pixel;
a bias current module for providing a constant current to the pixel circuit;
And the readout circuit is used for controlling the pixel circuits of the pulse sequence type image sensor corresponding to the pixels to output a second voltage signal.
18. An apparatus, the apparatus comprising: a pixel circuit of a pulse train image sensor according to any one of claims 1-16, and/or a pulse train image sensor according to claim 17.
19. The apparatus of claim 18, wherein the apparatus comprises at least one of:
cameras, audio/video players, navigation devices, fixed location terminals, entertainment devices, communication devices, mobile devices, vehicles or facilities, industrial devices, medical devices, security devices, flight devices, home appliances.
CN202223532655.2U 2022-12-28 2022-12-28 Pixel circuit of pulse sequence type image sensor, image sensor and device Active CN220156599U (en)

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Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202223532655.2U CN220156599U (en) 2022-12-28 2022-12-28 Pixel circuit of pulse sequence type image sensor, image sensor and device

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