CN220154907U - Storage device - Google Patents
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- CN220154907U CN220154907U CN202321276089.5U CN202321276089U CN220154907U CN 220154907 U CN220154907 U CN 220154907U CN 202321276089 U CN202321276089 U CN 202321276089U CN 220154907 U CN220154907 U CN 220154907U
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Abstract
The utility model provides a storage device. The memory device includes a first memory block, a second memory block, and a controller. The controller is coupled to the first memory block and the second memory block. When the first erasing operation of the first memory is executed and the second erasing requirement of the second memory is set, the controller determines whether to reset or pause the first erasing operation and executes the second erasing operation for the second memory block according to the second erasing requirement. The memory device provided by the utility model can effectively complete the erasing action of a plurality of memory blocks.
Description
Technical Field
The present utility model relates to a memory device, and more particularly, to a memory device capable of effectively performing a data writing operation.
Background
In the prior art, a nonvolatile Memory (NVM) may perform a data writing operation by performing an erasing operation and a programming operation. The larger the size of the memory block, the longer the erase operation of the non-volatile memory with respect to the memory block will require. Therefore, when the erasing operations of the memory blocks conflict in time, the erasing operations of the memory blocks may not be performed, and the writing operations may fail.
It should be noted that the content of the "background art" section is intended to aid in understanding the present utility model. Some (or all) of the disclosure in the background section may not be known to those of skill in the art. The disclosure in the background section is not intended to represent that which has been previously known by those of ordinary skill in the art prior to the application of the present utility model.
Disclosure of Invention
The utility model provides a storage device and a control method thereof, which can effectively complete the erasing action of a plurality of memory blocks.
The memory device of the utility model comprises a first memory block, a second memory block and a controller. The controller is coupled to the first memory block and the second memory block, and when a first erase operation of the first memory is performed, it is determined whether to reset or suspend the first erase operation when a second erase requirement of the second memory is set, and the second erase operation is performed on the second memory block according to the second erase requirement.
In an embodiment of the present utility model, the controller determines whether to reset or suspend the first erase operation according to the execution completion of the first erase operation.
In an embodiment of the present utility model, the controller measures an already running time of the first erase operation, calculates a required running time according to an expected completion time and the already running time, and decides whether to reset or suspend the first erase operation according to the required running time and the expected completion time.
In an embodiment of the utility model, the controller subtracts the run-time from the required run-time to produce the required run-time.
In an embodiment of the present utility model, the controller resets or pauses the first erase operation when a ratio of the required run time to the expected completion time is greater than a threshold.
In an embodiment of the present utility model, the controller resets or pauses the first erase operation when the difference between the expected completion time and the required running time is less than a threshold.
In an embodiment of the present utility model, the controller further counts a time required for a third erase operation of the first memory, and updates the expected completion time according to the required time.
In an embodiment of the present utility model, when the first erase operation is reset or suspended, the controller stores first command information of the first erase operation in a command queue.
In an embodiment of the present utility model, after the second erasing operation is completed, the controller reads the first command information in the command queue, and re-executes the first erasing operation according to the first command information.
In an embodiment of the present utility model, the controller further counts a required time when the first erase operation of the first memory is reset or paused.
In an embodiment of the utility model, the controller comprises: a time calculator for calculating an expected completion time of the first erase operation of the first memory block and a required time when reset or suspended; a control signal generator coupled to the first memory block and the second memory block for providing control signals for access operations of the first memory block and the second memory block; and a command queue for storing at least command information.
In an embodiment of the present utility model, it is characterized by further comprising: the processor is arranged in the controller or hung outside the controller.
In an embodiment of the present utility model, further comprising: the first counter and the second counter correspond to the first memory block and the second memory block respectively.
In the embodiment of the utility model, when receiving the power-off signal, the controller records the current erasing position of the first memory block; when the complex electric signal is received, the controller restarts the first erasing action of the first memory block according to the current erasing position.
Based on the above, the memory device of the present utility model can determine whether to reset or suspend the first erase operation according to the status of the first erase operation, and perform the second erase operation. Therefore, the phenomenon that any one of the erasing actions cannot be executed when the erasing actions conflict with each other, and the access error is caused can be avoided.
In order to make the above features and advantages of the present utility model more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a circuit diagram of a memory device according to an embodiment of the present utility model;
fig. 2 is a diagram of the internal configuration of a controller according to an embodiment of the present utility model.
Description of the reference numerals
100 storage device
110 first memory block
120 second memory block
130 controller
131. 131': processor
132 time calculator
133 control signal generator
134 Command queue
Detailed Description
Referring to fig. 1, fig. 1 is a circuit diagram of a memory device according to an embodiment of the utility model. The memory device 100 includes a first memory block 110, a second memory block 120, and a controller 130. The first Memory block 110 and the second Memory block 120 are Non-Volatile Memory (NVM) blocks, such as flash Memory (flash Memory) blocks. The controller 130 is coupled to the first memory block 110 and the second memory block 120. When the controller 130 receives the erasing request of the second memory block 120 during the first erasing operation of the first memory block 110, the controller 130 can directly interrupt and determine the first erasing operation of the first memory block 110, and perform the second erasing operation on the second memory block 120 according to the erasing request of the second memory block 120. Alternatively, the controller 130 may determine the execution degree of the first erase operation of the first memory block 110 to determine whether to interrupt the first erase operation of the first memory block 110. And the controller 130 can perform a second erase operation with respect to the second memory block 120 according to the erase requirement of the second memory block 120 after the first erase operation of the first memory block 110 is reset or paused.
Regarding the determination of the execution degree of the first erase operation of the first memory block 110, in detail, the controller 130 may measure the running time of the first erase operation during the execution of the first erase operation. And, the controller 130 can record the required running time of the first erasing operation. Thus, the controller 130 can determine the execution degree of the first erase operation of the first memory block 110 according to the running time of the first erase operation and the expected completion time of the first erase operation.
Further, the controller 130 may subtract the run time from the expected completion time of the first erase operation to generate the desired run time. And, the controller 130 may calculate a ratio of the required operation time to the expected completion time, and compare the ratio of the required operation time to the expected completion time with a preset first threshold. When the ratio of the required running time to the expected completion time is greater than the first threshold, the controller 130 may reset or suspend the first erase operation of the first memory block 110, and perform the second erase operation on the second memory block 120 according to the erase requirement of the second memory block 120. In contrast, when the ratio of the required running time to the expected completion time is not greater than the first threshold, it indicates that the first erase operation is completed soon. Therefore, the controller 130 can continuously perform the first erase operation of the first memory block 110, and perform the second erase operation on the second memory block 120 after the first erase operation is completed.
In another embodiment of the present utility model, the controller 130 can calculate the difference between the required running time and the expected completion time, and determine whether the difference between the required running time and the expected completion time is less than a second threshold to determine whether to reset or suspend the first erase operation. Specifically, when the difference between the expected completion time and the required running time is smaller than the second threshold, the controller 130 may reset or suspend the first erase operation and perform the second erase operation on the second memory block 120 according to the erase requirement of the second memory block 120. In contrast, when the difference between the expected completion time and the required running time is not less than the second threshold, the controller 130 may continuously perform the first erase operation of the first memory block 110, and perform the second erase operation on the second memory block 120 after the first erase operation is completed.
It should be noted that, in the embodiment of the present utility model, after the controller 130 resets or pauses the first erasing operation of the first memory block 110, the controller 130 may store the first command information corresponding to the first erasing operation into the command queue. After the second erasing operation of the second memory block 120 is completed and the memory block in the memory device 100 is idle, the controller 130 can read the command queue and re-execute the first erasing operation on the first memory block 110 according to the read first command information.
After the first memory block 110 performs the first erase operation again, the controller 130 may clear the first command information in the command queue.
Incidentally, when the first erase operation of the first memory block 110 is performed again, the expected completion time of the first erase operation is not changed in order to ensure that the first memory block 110 can be completely erased.
It should be noted that, due to the change of the first memory block 110 and the second memory block 120 caused by environmental factors and/or the influence caused by the use time and the access times, the expected completion time of the corresponding erasing operation may be changed. Therefore, when another (e.g., third) erase operation of the first memory block 110 is performed, the controller 130 can calculate the actual time required for completing the third erase operation in synchronization, and update the expected completion time according to the required time. Of course, the controller 130 may also update the second memory block 120.
In addition, the controller 130 may also calculate the time required for the first erase operation to be reset or suspended when the first erase operation of the first memory block 110 is reset or suspended.
Referring to fig. 2, fig. 2 is a schematic diagram of a controller according to an embodiment of the utility model. The controller 130 includes a processor 131, a control signal generator 132, a command queue 133, and a time calculator 134. Furthermore, in the present embodiment, the processor 131 may be disposed inside the controller 130, or in other embodiments of the present utility model, the processor 131' may be externally hung outside the controller 130.
In this embodiment, the processor 131 can perform the related actions of the programming and erasing actions with respect to the first memory block 110 and the second memory block 120. The processor 131 is, for example, a central processing unit (central processing unit, CPU), or other programmable general purpose or special purpose microcontrol unit (micro control unit, MCU), microprocessor (microprocessor), digital signal processor (digital signal processor, DSP), programmable controller, application specific integrated circuit (application specific integrated circuit, ASIC), graphics processor (graphics processing unit, GPU), image signal processor (image signal processor, ISP), image processing unit (image processing unit, IPU), arithmetic logic unit (arithmetic logic unit, ALU), complex programmable logic device (complex programmable logic device, CPLD), field programmable logic gate array (field programmable gate array, FPGA), or other similar component or combination of the above components.
The time calculator 132 may be configured to measure the run time of the first erase operation, the expected completion time of the first erase operation, and the time required for the first erase operation to be reset or paused. In addition, the time calculator 132 is also configured to subtract the expected completion time from the run time to generate the demand run time. The time calculator 132 may be further configured to calculate a ratio of the required run time to the expected completion time and compare the ratio with a first threshold to generate a first result. The time calculator 132 may also calculate a difference between the required run time and the expected completion time and compare it to a second threshold to produce a second result. The time calculator 132 also transmits the first result or the second result to the processor 131.
Of course, in other embodiments of the present utility model, the difference between the required running time, the running time and the expected completion time, the first comparison result and the second comparison result may also be calculated and obtained by the processor 131, without limitation.
The control signal generator 133 is coupled to the first memory block 110 and the second memory block 120 to provide control signals for the access operations of the first memory block 110 and the second memory block 120. For example, when the processor 131 is performing the first erase operation on the first memory block 110, the processor 131 receives the request of the second erase operation of the second memory block 120, and determines whether to reset or suspend the first erase operation according to the first result or the second result transmitted by the time calculator 132. At this time, if the first erase operation is to be reset or suspended, the control signal generator 133 sends a first control signal to the first memory block 110, and resets or suspends the first erase operation. The control signal generator 133 also sends a second control signal to the second memory block 120, and causes the second memory block 120 to start a second erase operation. In addition, the control signal generator 133 also stores the first erase operation requirement in the command queue 134. After the processor 131 finishes executing the second erase operation, the processor 131 may also read the command information of the command queue 134, send another (e.g., third) control signal to the first memory block 110 through the control signal generator 133, and start another (e.g., third) erase operation.
The command queue 134 is used to store command information. For example, the command queue 134 stores the first erase operation request from the control signal generator 133 when the first erase operation is reset or suspended. In another embodiment, the command queue 134 stores the second erase operation requirement if the first erase operation is not reset or suspended when the processor 131 determines whether to reset or suspend the first erase operation by the first result or the second result transmitted by the time calculator 132.
In addition, in the present embodiment, when the controller 130 receives the power-off signal, the controller 130 can record the first erasing operation of the first memory block 110. So that the controller 130 restarts the first erase operation of the first memory block 110 when receiving the complex power signal.
In an embodiment of the present utility model, the storage device 100 further includes a first counter corresponding to the first memory block 110 and a second counter corresponding to the second memory block 120. The first counter and the second counter respectively count the erase times of the first memory block 110 and the second memory block 120. When the first erase count of the first memory block 110 or the upper limit is reached, the controller 130 does not erase the first memory block 110. Similarly, when the second erase count of the second memory block 120 or the upper limit is reached, the controller 130 does not erase the second memory block 120. In the embodiment of the utility model, the upper limit of the erasing times can be set according to the life cycle of the memory block.
The above description of the storage device is applicable to the following control method of the storage device.
In summary, the present utility model can determine whether to reset or suspend the first erase operation and execute the erase requirement of the second memory block according to the completion of the first erase operation when the first memory block in the storage device receives the erase requirement of the second memory block during the first erase operation. Meanwhile, after the erasing requirement of the second memory block is completed, the controller restarts or continues to execute the first erasing action. Therefore, the erasing operation time of one memory block can be saved, and the requirement of executing other memory blocks is not influenced.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present utility model, and not for limiting the same; although the utility model has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the utility model.
Claims (14)
1. A memory device, comprising:
a first memory block and a second memory block; and
the controller is coupled to the first memory block and the second memory block, and when a first erasing operation of the first memory is performed and a second erasing requirement of the second memory is set, the controller determines whether to reset or suspend the first erasing operation, and executes the second erasing operation for the second memory block according to the second erasing requirement.
2. The memory device of claim 1, wherein the controller determines whether to reset or suspend the first erase operation based on a completion of the execution of the first erase operation.
3. The memory device of claim 2, wherein the controller measures an already running time of the first erase operation, calculates a required running time based on an expected completion time and the already running time, and decides whether to reset or suspend the first erase operation based on the required running time and the expected completion time.
4. The storage device of claim 3, wherein the controller subtracts the run time from the required run time to produce the required run time.
5. The memory device of claim 3, wherein the controller resets or pauses the first erase operation when a ratio of the required run time to the expected completion time is greater than a threshold.
6. The memory device of claim 3, wherein the controller resets or pauses the first erase operation when the difference between the expected completion time and the required run time is less than a threshold.
7. The memory device of claim 3 wherein the controller further counts a time required for a third erase operation of the first memory and updates the expected completion time based on the time required.
8. The memory device of claim 1, wherein the controller stores first command information for the first erase operation in a command queue when the first erase operation is reset or paused.
9. The memory device of claim 8, wherein the controller reads the first command information in the command queue and re-executes the first erase operation according to the first command information after the second erase operation is completed.
10. The memory device of claim 1, wherein the controller further counts a required time when the first erase operation of the first memory is reset or paused.
11. The storage device of claim 1, wherein the controller comprises:
a time calculator for calculating an expected completion time of the first erase operation of the first memory block and a required time when reset or suspended;
a control signal generator coupled to the first memory block and the second memory block for providing control signals for access operations of the first memory block and the second memory block; and
and a command queue for storing at least command information.
12. The storage device of claim 11, further comprising:
the processor is arranged in the controller or hung outside the controller.
13. The storage device of claim 1, further comprising:
the first counter and the second counter correspond to the first memory block and the second memory block respectively.
14. The storage device of claim 1, wherein the memory is configured to store the data,
when a power-off signal is received, the controller records the current erasing position of the first memory block;
when the complex electric signal is received, the controller restarts the first erasing action of the first memory block according to the current erasing position.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US202263398538P | 2022-08-17 | 2022-08-17 | |
| US63/398,538 | 2022-08-17 | ||
| TW112202442 | 2023-03-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN220154907U true CN220154907U (en) | 2023-12-08 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202321276089.5U Active CN220154907U (en) | 2022-08-17 | 2023-05-24 | Storage device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN220154907U (en) |
| TW (1) | TWM647701U (en) |
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2023
- 2023-03-17 TW TW112202442U patent/TWM647701U/en unknown
- 2023-05-24 CN CN202321276089.5U patent/CN220154907U/en active Active
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| TWM647701U (en) | 2023-11-01 |
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