JP2010205167A - Nonvolatile memory, and control method and program thereof - Google Patents

Nonvolatile memory, and control method and program thereof Download PDF

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JP2010205167A
JP2010205167A JP2009052521A JP2009052521A JP2010205167A JP 2010205167 A JP2010205167 A JP 2010205167A JP 2009052521 A JP2009052521 A JP 2009052521A JP 2009052521 A JP2009052521 A JP 2009052521A JP 2010205167 A JP2010205167 A JP 2010205167A
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time
calculation
erased
predetermined block
nonvolatile memory
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Satoru Fujii
了 藤井
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Nec Corp
日本電気株式会社
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Abstract

A non-volatile memory that can statically estimate a minimum memory life, a control method thereof, and a program are provided.
A non-volatile memory in which electrical data is written and erased for each of a plurality of blocks, the counter means for measuring time, and when the last erase is performed for each of a plurality of blocks Recording means for recording a predetermined time, and when a predetermined block is erased, the current time measured by the counting means and the time recorded in the recording means corresponding to the predetermined block And a calculation unit that performs calculation based on the weight signal. When the calculation result of the calculation unit is smaller than a predetermined value, the wait signal is activated.
[Selection] Figure 1

Description

  The present invention relates to a nonvolatile memory capable of electrically writing and erasing data, a control method thereof, and a program.

  As an example of a nonvolatile memory that can electrically write and erase data, there are flash memories disclosed in Patent Documents 1 and 2, for example. Flash memory is now widely used due to its features that it is smaller and harder to impact than a hard disk and does not require a backup power supply. The flash memory is used for a main memory, a memory card, a USB (Universal Serial Bus) memory, a BIOS (Basic Input / Output System) in an information processing device such as a mobile phone, a game machine, a digital camera, and a personal computer. Yes.

  In a flash memory, a plurality of blocks (storage elements) are provided, and data is erased and written (referred to as rewriting) in units of blocks, but the number of times of rewriting is limited. Since the number of times of rewriting is not the number of times for the entire flash memory but the number of times for one block, if the data rewriting concentrates on a specific block, the life of the flash memory is shortened. . For this reason, the flash memory needs to have a mechanism called wear leveling as a technique for extending the lifetime. This wear leveling is a technique for evenly distributing data rewriting so that it does not concentrate on a specific block. Thereby, the number of rewrites in each block is made uniform, and as a result, the life of the flash memory can be extended.

JP-A-2005-99983 JP 2007-156862 A

  Implementing wear leveling using hardware in a flash memory is not realistic in view of the recent widespread use of flash memory because of the problem of increased cost and size. Therefore, it is desirable to implement wear leveling using software instead of hardware.

  However, when the wear leveling is implemented using software, there may be a problem that rewriting occurs remarkably due to a software bug or the like. When such a problem occurs, the number of times of rewriting is unnecessarily consumed, resulting in a problem that the life of the flash memory is shortened. In addition, since the detection of the defect often requires a long test such as covering all cases, it is difficult to detect the defect in advance and take measures against it.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a non-volatile memory that can statically estimate the minimum memory life, a control method thereof, and a program.

  In order to achieve such an object, the nonvolatile memory of the present invention is a nonvolatile memory in which electrical data is written and erased for each of a plurality of blocks, and includes a counter means for measuring time, and a plurality of Corresponds to the recording means for recording the time when the last erase was performed for each block, the current time measured by the counting means when the predetermined block was erased, and the predetermined block And calculating means for calculating based on the time recorded in the recording means, and when the calculation result by the calculating means is smaller than a preset specified value, the wait signal is activated. It is characterized by.

  The non-volatile memory control method of the present invention is a non-volatile memory control method in which electrical data is written and erased for each of a plurality of blocks, and is an electronic device connected to the non-volatile memory or the non-volatile memory. The device measures the time, records the time when the last erase was performed for each of a plurality of blocks, and the current measured when a predetermined block is erased. And a step of performing a calculation based on the time recorded in correspondence with a predetermined block, and a step of activating a wait signal when a result of the calculation is smaller than a predetermined value, It is characterized by having.

  The program of the present invention is a program for controlling a nonvolatile memory in which electrical data is written and erased for each of a plurality of blocks, and includes a process for measuring time, and for each of the plurality of blocks. The process of recording the time when the last erase was performed, the current time measured when the predetermined block was erased, and the time recorded corresponding to the predetermined block The computer is caused to execute a process of performing a calculation based on the above and a process of activating a wait signal when the result of the calculation is smaller than a predetermined value set in advance.

  According to the present invention, it is possible to statically estimate the minimum lifetime of a memory in a nonvolatile memory.

It is a block diagram which shows the structural example of the non-volatile memory which concerns on one Embodiment of this invention. It is a figure which shows the example of the area | region used with RAM of the non-volatile memory which concerns on one Embodiment of this invention. 4 is a flowchart illustrating an operation example of the nonvolatile memory according to the embodiment of the present invention.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments (embodiments) for carrying out the present invention will be described in detail with reference to the accompanying drawings. As an embodiment of the nonvolatile memory of the present invention, a flash memory capable of electrically erasing and writing data will be described as an example.

  First, the configuration of the flash memory according to the present embodiment will be described with reference to FIG.

  As shown in FIG. 1, the flash memory according to the present embodiment includes a counter (counter means) 3, a RAM (recording means) 4, an arithmetic unit, in addition to a memory array 1 and an I / F circuit 2 having a general configuration. (Calculation means) 5 is provided. Although not shown, it is assumed that the flash memory according to the present embodiment is connected (including embedded) to a predetermined electronic device. Examples of the electronic device include information processing devices such as a mobile phone, a game device, a digital camera, and a personal computer.

  The I / F circuit 2 is connected to signal lines (buses) through which address, data, and WAIT signals are transmitted. Further, the I / F circuit 2 in this embodiment is also connected to a signal line through which an interrupt signal is transmitted. A signal line through which each of the address, data, and WAIT signal is transmitted is connected to a CPU (Central Processing Unit) (not shown). This CPU is a CPU of an electronic device to which the flash memory according to this embodiment is connected (embedded).

  A counter clock is input to the counter 3. As an example, the clock input is 32.768 kHz, which is a crystal frequency used for convenience and a normal clock, and the specified value is 0x40000 (8 seconds). The counter 3 counts time and acquires a time stamp. The acquired time stamp is recorded (set) in a predetermined area of the RAM 4 as a counter value.

  In FIG. 1, for example, the memory array 1 is assumed to be composed of 128 blocks (storage elements), the counter 3 is set to 64 bits that do not overflow in actual specifications, and the RAM 4 is 64 bits × (128 + 1) = 1032 bytes. And all are initialized to 0 when the power is turned on.

  In the RAM 4, a time stamp at the time of last erasing is recorded for each block of the memory array 1. Here, the area used in the RAM 4 is illustrated in FIG. In the RAM 4, the counter value holding area is divided for each of the blocks 0 to 128. The counter value holding area is an area for recording and holding the counter value (time stamp) acquired by the counter 3. As shown in FIG. 2, the address “0” is a counter value holding area for block 0 and the address “8” is a counter value holding area for block 1. In this manner, 128 counter value holding areas from block 1 to block 128 are used in the RAM 4. In the RAM 4, a specified value setting holding area is used. As described above, the specified value 0x40000 (8 seconds) is held in this area as an example.

  Next, the operation of the flash memory of this embodiment (one embodiment of the flash memory control method and program of the present invention) will be described with reference to FIG. A program for executing the operation shown in FIG. 3 is stored in the flash memory. This program is read into the CPU of an electronic device (not shown). The CPU is controlled by the program and performs the operation of FIG.

  For example, when block 0 is erased, the CPU determines whether or not it is the first erase after the electronic device is powered on (step S1). The CPU refers to the counter value recorded (set) in the counter value holding area for block 0 in the RAM 4. Then, as a result of the reference, if the counter value is 0, the CPU determines that it is the first erasing after the power is turned on, and if the counter value is not 0, the CPU judges that it is not the first erasing after the power is turned on. .

  Here, as an example, it is assumed that the counter value recorded in the counter value holding area for block 0 in the RAM 4 is zero. Therefore, the CPU determines that this is the first erasure after the electronic device is powered on (step S1 / YES), obtains the current counter value from the counter 3, and holds the value for the counter value for the block 0 of the RAM 4 Recording in the area (step S2). Here, as an example, this counter value is set to 0x8000.

  Assume that block 0 is erased again 10 seconds after the previous erase. The CPU again determines whether or not it is the first erase after the power is turned on (step S1). At this time, the counter value 0x8000 is recorded in the counter value holding area for the block 0 of the RAM 4. Therefore, as a result of referring to the counter value holding area for block 0, the CPU determines that it is not the first erasing after the power is turned on because the counter value is not 0 (step S1 / NO).

  The CPU calculates a mathematical expression (current counter value−counter value in the counter value holding area) using the calculator 5, and the calculation result and a specified value recorded in advance in the holding area for setting the specified value in the RAM 4. Are compared (step S3). This operation is as follows, for example. First, the CPU acquires the current counter value 0x50000 (10 seconds) from the counter 3, acquires the counter value 0x8000 in the counter value holding area from the RAM 4, and inputs both the acquired values to the calculator 5. Next, (0x50000-0x8000) is calculated in the calculator 5. The result of this calculation is 0x42000. On the other hand, the specified value is 0x40000 (8 seconds) as described above. The CPU compares the calculation result 0x42000 with the specified value 0x40000.

  As a result of the comparison in step S3, the calculation result is larger than the specified value (step S4 / YES). After erasing is executed, the counter value 0x8000 recorded in the counter value holding area for the CPU and block 0 is executed. Is updated to 0x58000 (0x8000 + 0x50000) (step S5).

  Then, assume that block 0 is erased again one second after the previous erase. The CPU again determines whether or not it is the first erase after the power is turned on (step S1). At this time, the counter value 0x58000 is recorded in the counter value holding area for the block 0 of the RAM 4. Therefore, as a result of referring to the counter value holding area for block 0, the CPU determines that it is not the first erasing after the power is turned on because the counter value is not 0 (step S1 / NO).

  The CPU again calculates the mathematical formula (current counter value−counter value of the counter value holding area) using the calculator 5, and the result of the calculation is recorded in advance in the holding area for setting the specified value in the RAM 4. The specified value is compared (step S3). This operation is as follows, for example. First, the CPU acquires the current counter value 0x55000 (11 seconds) from the counter 3, acquires the counter value 0x58000 in the counter value holding area from the RAM 4, and inputs both the acquired values to the calculator 5. The calculator 5 calculates (0x55000-0x58000). The result of this calculation is -0x3000. On the other hand, the specified value is 0x40000. Therefore, the CPU compares the calculation result −0x3000 with the specified value 0x40000.

  As a result of the comparison in step S3, the calculation result is smaller than the specified value (step S4 / NO), so the CPU sets the WAIT signal to ACTIVE (step S6). The ACTIVE of the WAIT signal is performed while the calculation result is smaller than the specified value. In this way, by setting the WAIT signal to ACTIVE, it is possible to statically estimate the minimum lifetime (allowing a static lifetime design).

  In step S6 in FIG. 3, instead of setting the WAIT signal to ACTIVE, the interrupt signal may be set to ACTIVE to notify the CPU of the abnormality. This makes it possible to detect software defects. Alternatively, in step S6 of FIG. 3, the CPU may be notified of the abnormality by setting the WAIT signal to ACTIVE and simultaneously setting the interrupt signal to ACTIVE. As a result, it is possible to statically estimate the minimum lifetime and to detect software defects.

  In the above description, the main body performing the operation of FIG. 3 has been described as the CPU of the electronic device, but the present invention is not limited to this. For example, the operation subject may be the computing unit 5.

  As described above, in the flash memory according to the present embodiment, in the case of re-erasing within a specified time (specified value), the bus master is made to wait using the WAIT signal. That is, in this embodiment, when a predetermined block is erased, compared with the time erased last time, if the predetermined time (specified value) has not passed, the WAIT signal is set to ACTIVE to statically minimize the minimum life. Make an estimate possible. In other words, by adding a small amount of RAM of about 1 kilobyte, a counter, and an arithmetic unit to a general flash memory, the minimum lifetime of the flash memory can be guaranteed even if there is a problem with the software. For example, in the flash memory according to the present embodiment, when there are 128 blocks and 100,000 times of rewriting is possible, if the specified time is 20 seconds, even if each block is accessed in sequence, at least It is possible to guarantee a period of 100,000 times × 20 seconds = about 8 years.

  In the flash memory according to the present embodiment, in the case of re-erasing within a specified time (specified value), an interrupt signal is used to notify the CPU. That is, in the flash memory according to the present embodiment, when a predetermined block is erased, compared to the time erased last time, if the predetermined time (specified value) has not passed, the interrupt signal is set to ACTIVE to notify the CPU of the abnormality. In this way, software defects can be detected.

  As mentioned above, although embodiment of this invention was described, it is not limited to the said embodiment, A various deformation | transformation is possible in the range which does not deviate from the summary. For example, it is configured not only to be executed in time series according to the processing operation described in the above embodiment, but also to be configured so as to be executed in parallel or individually as required by the processing capability of the apparatus that executes the processing. Is also possible.

  The present invention can be applied to devices, apparatuses, and systems in general that can use a nonvolatile memory.

1 Memory array 2 I / F circuit 3 Counter 4 RAM
5 Calculator

Claims (9)

  1. A nonvolatile memory in which electrical data is written and erased for each of a plurality of blocks,
    Counter means for measuring time;
    For each of the plurality of blocks, recording means for recording the time when the last erasure was performed,
    Calculation means for performing calculation based on the current time measured by the counting means and the time recorded in the recording means corresponding to the predetermined block when a predetermined block is erased And having
    A non-volatile memory, wherein a wait signal is activated when a calculation result obtained by the calculation means is smaller than a predetermined value set in advance.
  2.   2. The non-volatile memory according to claim 1, wherein when the calculation result by the calculation means is smaller than a preset specified value, an abnormality signal is notified by activating an interrupt signal.
  3.   If the calculation result by the calculation means is greater than a preset specified value, the time recorded in the recording means corresponding to the predetermined block after erasing the predetermined block is 3. The nonvolatile memory according to claim 1, wherein the nonvolatile memory is updated to a new value based on the current time measured by the counting means.
  4. Whether the predetermined block is erased for the first time after power-on is determined based on the time recorded in the recording means,
    The computing means is
    4. The nonvolatile memory according to claim 1, wherein the calculation is performed when the predetermined block is not erased for the first time. 5.
  5.   The erasing of the predetermined block is performed for the first time, and the current time measured by the counter unit is recorded in the recording unit corresponding to the predetermined block. 4. The non-volatile memory according to 4.
  6. A method for controlling a nonvolatile memory in which electrical data is written and erased for each of a plurality of blocks,
    The nonvolatile memory or the electronic device connected to the nonvolatile memory is
    A step of measuring time;
    For each of the plurality of blocks, recording the time when the last erasure was performed;
    When the predetermined block is erased, performing a calculation based on the measured current time and the time recorded corresponding to the predetermined block;
    When the result of the calculation is smaller than a preset specified value, activating a wait signal;
    A method for controlling a non-volatile memory, comprising:
  7.   7. The method of controlling a nonvolatile memory according to claim 6, further comprising a step of notifying an abnormality by activating an interrupt signal when a result of the calculation is smaller than a predetermined value set in advance. .
  8. A program for controlling a nonvolatile memory in which electrical data is written and erased for each of a plurality of blocks,
    Processing to measure time,
    For each of the plurality of blocks, processing for recording the time when the last erasure was performed,
    When the predetermined block is erased, a process of performing an operation based on the measured current time and the time recorded corresponding to the predetermined block;
    When the result of the calculation is smaller than a preset specified value, a process of activating the wait signal;
    A program that causes a computer to execute.
  9.   9. The program according to claim 8, wherein when the result of the calculation is smaller than a predetermined value set in advance, the computer is caused to perform a process of notifying an abnormality by activating an interrupt signal.
JP2009052521A 2009-03-05 2009-03-05 Nonvolatile memory, and control method and program thereof Withdrawn JP2010205167A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9286990B1 (en) 2014-12-22 2016-03-15 Samsung Electronics Co., Ltd. Storage device, nonvolatile memory and method operating same
US9870160B2 (en) 2014-03-26 2018-01-16 Samsung Electronics Co., Ltd. Method of operating memory system including nonvolatile memory and memory controller

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9870160B2 (en) 2014-03-26 2018-01-16 Samsung Electronics Co., Ltd. Method of operating memory system including nonvolatile memory and memory controller
US9286990B1 (en) 2014-12-22 2016-03-15 Samsung Electronics Co., Ltd. Storage device, nonvolatile memory and method operating same

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