CN220137930U - Receiving equipment, receiving system and electronic equipment - Google Patents
Receiving equipment, receiving system and electronic equipment Download PDFInfo
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- CN220137930U CN220137930U CN202321024158.3U CN202321024158U CN220137930U CN 220137930 U CN220137930 U CN 220137930U CN 202321024158 U CN202321024158 U CN 202321024158U CN 220137930 U CN220137930 U CN 220137930U
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Abstract
The utility model belongs to the technical field of interaction, and provides receiving equipment, a receiving system and electronic equipment, wherein a first plug connector and a second plug connector are formed on a circuit board, the first plug connector comprises a first data output pin group, the second plug connector comprises a second data output pin group, the sum of the number of pins in the first data output pin group and the number of pins in the second data output pin group is set to be 12N, and a plurality of bonding pad groups are respectively and electrically connected with a plurality of pins in the first plug connector and the second plug connector in a one-to-one correspondence manner, so that the receiving equipment can be compatible with virtual pixel display supporting sub-pixel RGBV under the condition of supporting RGB three-color real pixel signals for display.
Description
Technical Field
The utility model belongs to the technical field of interaction, and particularly relates to receiving equipment, a receiving system and electronic equipment.
Background
With the development of the LED display industry, the use of a display screen is required to display more pixels on the premise of low cost, and in order to adapt to such market demands, the receiving card product needs to display more pixels under the same load condition.
However, the conventional interface only supports data output of RGB real pixels, but cannot support data output of other pixel formats, so that display products need to be customized and cannot be universal, manufacturing cost is increased, and application range of the receiving card is greatly limited.
Disclosure of Invention
The embodiment of the utility model provides receiving equipment, a receiving system and electronic equipment, which can solve the problem that the conventional interface only supports the data output of RGB real pixels and cannot support the data output of other pixel formats.
In order to solve the above technical problem, a first aspect of an embodiment of the present utility model provides a receiving apparatus, including: the circuit board, the first plug connector and the second plug connector; wherein,
the first plug connector and the second plug connector are arranged on the circuit board;
the first plug connector comprises a first data output pin group, the second plug connector comprises a second data output pin group, the sum of the number of pins in the first data output pin group and the number of pins in the second data output pin group is 12N, and N is a positive integer;
and a plurality of pins in the first plug connector and the second plug connector are electrically connected with a plurality of bonding pad groups on the circuit board in a one-to-one correspondence manner.
In one embodiment, the first and second connectors further comprise at least one of a control signal pin set, a serial peripheral interface signal pin set, a clock signal pin set, a power pin set, a ground pin set, and a load signal pin set.
In one embodiment, the number of pins in the first data output pin group is the same as the number of pins in the second data output pin group.
In one embodiment, the circuit board includes a first set of data pads and a second set of data pads thereon;
the plurality of bonding pads in the first data bonding pad group are connected with pins in the first data output pin group in a one-to-one correspondence manner, and the plurality of bonding pads in the second data bonding pad group are connected with pins in the second data output pin group in a one-to-one correspondence manner.
In one embodiment, the number of pins in the first data output pin group and the number of pins in the second data output pin group are 12m, where m is a positive integer.
In one embodiment, the sum of the number of pins in the first data output pin group and the number of pins in the second data output pin group is 96.
In one embodiment, the first connector is coupled to a microprocessor and a memory chip.
In one embodiment, the microprocessor is an FPGA chip.
The second aspect of the embodiment of the present utility model also provides a receiving system, including: a receiving device as claimed in any preceding claim.
A third aspect of an embodiment of the present utility model further provides an electronic device, including:
a display panel; and
the receiving system according to the above embodiment, the receiving system is connected to the display panel.
Compared with the prior art, the embodiment of the utility model has the beneficial effects that: the first plug connector and the second plug connector are formed on the circuit board, the first plug connector comprises a first data output pin group, the second plug connector comprises a second data output pin group, the sum of the number of pins in the first data output pin group and the number of pins in the second data output pin group is set to be 12N, and the plurality of bonding pad groups are respectively and electrically connected with the plurality of pins in the first plug connector and the second plug connector in a one-to-one correspondence manner, so that the receiving device can be compatible with virtual pixel display supporting sub-pixel RGBV under the condition of supporting RGB three-color real pixel signals for display.
Drawings
Fig. 1 is a schematic structural diagram of an application scenario of a receiving card according to an embodiment of the present utility model;
fig. 2 is a schematic structural diagram of a receiving device according to an embodiment of the present utility model;
fig. 3 is a schematic structural diagram of a receiving device in RGB pin output mode according to an embodiment of the present utility model;
fig. 4 is a schematic structural diagram of a receiving device in RGBV pin output mode according to an embodiment of the present utility model.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the utility model is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the utility model.
It will be understood that when an element is referred to as being "mounted" or "disposed" on another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
It is to be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are merely for convenience in describing and simplifying the description based on the orientation or positional relationship shown in the drawings, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus are not to be construed as limiting the utility model.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present utility model, the meaning of "a plurality" is one or more than one unless specifically defined otherwise.
As shown in fig. 1, in an application scenario of the display screen 200, it is generally required that the receiving card 100 is connected to the display screen to provide pixel signals for the display screen 200. The conventional interface adopted at present only supports the data output of RGB real pixels, and cannot support the data output of other pixel formats, so that the display product needs to be customized and cannot be universal, the manufacturing cost is increased, and the application range of the receiving card 100 is greatly limited.
In order to solve the above technical problem, an embodiment of the present utility model provides a receiving apparatus, as shown in fig. 2, where the receiving apparatus in this embodiment includes: the circuit board 300, the first connector JH1 and the second connector JH2.
Referring to fig. 2, a first connector JH1 and a second connector JH2 are disposed on a circuit board 300, where the first connector JH1 includes a first data output pin group, the second connector JH2 includes a second data output pin group, and a sum of a number of pins in the first data output pin group and a number of pins in the second data output pin group is 12n, where n is a positive integer; the pins of the first connector and the second connector are electrically connected to the plurality of bonding pad groups on the circuit board 300 in a one-to-one correspondence manner.
In this embodiment, the first connector JH1 and the second connector JH2 may be used as a mother card, and receive signals input by a male card (e.g. a processing chip), and in application, the male card is inserted into the first connector JH1 and the second connector JH2, and outputs signals to the first connector JH1 and the second connector JH2. The first plug connector JH1 comprises a first data output pin group, the second plug connector JH2 comprises a second data output pin group, the first data output pin group and the second data output pin group are connected to a data output interface in a sharing mode, a plurality of contacts in the data output interface are welded and fixed with corresponding bonding pad groups on the circuit board 300, the data output interface is used for being connected with an external display panel, and pixel display signals accessed by the first plug connector JH1 and the second plug connector JH2 are forwarded and output to the corresponding display panel through the data output interface. The sum of the pin number in the first data output pin group and the pin number in the second data output pin group is 12N, and the plurality of bonding pad groups are respectively and correspondingly electrically connected with the plurality of pins in the first plug connector JH1 and the second plug connector JH2, so that the receiving equipment can be compatible with virtual pixel display supporting sub-pixel RGBV under the condition of supporting RGB three-color real pixel signals for display.
In one embodiment, the circuit board 300 may be an FPGA board.
In one embodiment, the first connector JH1 and the second connector JH2 are high-density connectors, and the number of pins in the first connector JH1 and the second connector JH2 is 120.
In one embodiment, the number of pins in the first data output pin group is the same as the number of pins in the second data output pin group, that is, the number of the first connectors JH1 and the second connectors JH2 for outputting pixel display signals is the same.
In one embodiment, the number of pins in the first data output pin set and the number of pins in the second data output pin set are 48.
In one embodiment, the circuit board 300 includes a first set of data pads and a second set of data pads thereon.
The plurality of bonding pads in the first data bonding pad group are connected with pins in the first data output pin group in a one-to-one correspondence manner, and the plurality of bonding pads in the second data bonding pad group are connected with pins in the second data output pin group in a one-to-one correspondence manner.
In this embodiment, the first data pad group may be used to solder the first data interface, the second data pad group may be used to solder the second data pin, and the plurality of metal contacts in the first data interface are electrically connected in one-to-one correspondence with the plurality of pads in the first data pad group, and the plurality of metal contacts in the second data interface are electrically connected in one-to-one correspondence with the plurality of pads in the second data pad group. Two data interfaces can be led out from the circuit board 300, and two display panels are correspondingly connected.
In one embodiment, the number of pins in the first data output pin group and the number of pins in the second data output pin group are 12m, where m is a positive integer.
In this embodiment, by providing 12M data pins in each data output pin group, the pixel display signal can be output in the RGB pin output mode and the RGBV pin output mode on each connector.
In a specific application embodiment, the first connector JH1 is correspondingly connected to the first data interface through a metal wire and a bonding pad on the circuit board 300, the second connector JH2 is correspondingly connected to the second data interface through a metal wire and a bonding pad on the circuit board 300, the first data interface and the second data interface may be respectively connected to the first display panel and the second display panel, and the display modes of the first display panel and the second display panel may be different.
In an application embodiment, the functions of the data output pins in the first connector JH1 and the second connector JH2 may be switched according to the type of the display panel connected, for example, when the display type of the display panel connected to the data interface on the circuit board 300 is RGB three-color real pixel display, and the data interface is a three-lamp RGB virtual display interface, the main control chip generates corresponding RGB pixel display signals when the first connector JH1 and the second connector JH2 are inserted, and at this time, the signal mode received by the first connector JH1 and the second connector JH2 is RGB pin output mode; when the display type of the display panel connected to the data interface on the circuit board 300 is RGBV four-color real pixel display, and the data interface is a four-lamp RGBV virtual display interface, the main control chip generates corresponding RGBV pixel display signals when the first plug connector JH1 and the second plug connector JH2 are inserted, and at this time, the signal mode received by the first plug connector JH1 and the second plug connector JH2 is an RGBV pin output mode.
In one embodiment, the sum of the number of pins in the first data output pin group and the number of pins in the second data output pin group is 96.
In this embodiment, the sum of the numbers of the data output pins of the first connector JH1 and the second connector JH2 is 96, so that the parallel 32 groups of RGB pin output modes and 24 groups of RGBV pin output modes can be simultaneously realized, and the problem that the conventional interface only supports the data output of RGB real pixels and cannot support the data output of virtual pixels (V) is solved.
In one embodiment, when the type of the display panel accessed by the circuit board 300 is changed, by sending a panel switching signal to the main control chip, the main control chip converts the display data into corresponding pixel display signals based on the panel switching signal, and simultaneously, two mode selections (namely, a parallel 32-group RGB pin output mode and a 24-group RGBV pin output mode) allocated to the data output pins can simultaneously realize parallel 32-group three-lamp virtual pixels and parallel 24-group four-lamp virtual pixel data output on one high-density connector.
In one embodiment, the first connector JH1 may be coupled to a microprocessor and a memory chip.
The microprocessor can be used as a main control chip to be plugged into a data socket on the first plug connector JH1 and provide pixel display signals for the first plug connector JH 1. The memory chip can be plugged into a memory function interface on the first plug connector JH1 to provide a memory control signal for the first plug connector JH 1.
In one embodiment, the microprocessor may be an FPGA chip.
In one application embodiment, the first connector JH1 may further include at least one of a network card signal pin group, a control signal pin group, a serial peripheral interface (serial peripheral interface, SPI) signal pin group, a debug signal pin group, and a clock signal pin group, a configuration load signal pin group.
In one embodiment, in the case where the signal mode received by the first connector JH1 is the RGB pin output mode, the functional interface of the data output pins in the first connector JH1 is shown in fig. 3, and the pin configuration of the first connector JH1 is shown in table 1.
Table 1:
in one embodiment, in the case where the signal mode received by the second connector JH2 is the RGB pin output mode, the functional interface of the data output pins in the second connector JH2 is shown in fig. 3, and the pin configuration of the second connector JH2 is shown in table 2.
Table 2:
as shown in table 1 and table 2, in the case that the signal mode received by the first connector JH1 and the second connector JH2 is the RGB pin output mode, the numbers 27 to 82 in the first connector JH1 may be used as the data output pins, wherein 56 pins in the numbers 27 to 82 are symmetrically arranged according to two columns of pins, and 1 pair of data ground pins are arranged for every 6 pairs of data output pins, so as to provide a ground signal for the display panel accessed from the outside.
In the second plug connector JH2, the numbers 53 to 108 can be used as data output pins, wherein 56 pins in the numbers 53 to 108 are symmetrically arranged according to two columns of pins, and 1 pair of data grounding pins are arranged every 6 pairs of data output pins to provide grounding signals for a display panel accessed from the outside.
It will be appreciated that the pixel display signals received in the data output pins may be control signals for horizontal scanning, and that the display of each pixel in the display panel may be controlled by a row scan signal and a column scan signal.
And in combination with the tables 1 and 2, the first plug connector JH1 and the second plug connector JH2 are further provided with a plurality of groups of redundant pins, and the functions of the redundant pins can be designed in a self-defined manner according to the needs of users.
The first plug connector JH1 and the second plug connector JH2 are further provided with a plurality of groups of power supply pins and a plurality of groups of grounding pins, so that a plurality of power supplies and a plurality of paths of power supply inputs can be matched, and abundant pin settings are provided for application diversification of receiving equipment.
In one embodiment, in the first plug connector JH1 and the second plug connector JH2, a first empty space is provided between the grounding pin and the adjacent pin, and a second empty space is provided between the redundant pin and the adjacent pin, so that the redundant pin can be distinguished from other pin groups when the redundant pin is used for expanding the functions of the pins, and the problem of confusion or signal interference is avoided.
In one embodiment, the size of the empty space may be the same or different, and the size space may be set according to actual needs.
As shown in table 1 and table 2, a plurality of groups of network card signal pins are further arranged in the first plug connector JH1 and the second plug connector JH2, and the plurality of groups of network card signal pins are used for receiving network signals.
In one embodiment, the network card signal pin may be a gigabit network card signal pin for receiving gigabit network signals.
In one embodiment, in the case where the signal mode received by the first connector JH1 is the RGBV pin output mode, the functional interface of the data output pins in the first connector JH1 is shown in fig. 4, and the pin configuration of the first connector JH1 is shown in table 3.
Table 3:
in one embodiment, in the case where the signal mode received by the second connector JH2 is the RGBV pin output mode, the functional interface of the data output pins in the second connector JH2 is shown in fig. 4, and the pin configuration of the second connector JH2 is shown in table 4.
Table 4:
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as shown in table 3 and table 4, in the case that the signal mode received by the first connector JH1 and the second connector JH2 is the RGBV pin output mode, the numbers 27 to 82 in the first connector JH1 may be used as the data output pins, wherein the 56 data output pins in the numbers 27 to 82 are symmetrically arranged according to two columns of pins, and 1 pair of data ground pins are arranged every 6 pairs of data output pins to provide the ground signal for the display panel externally connected.
In the second plug connector JH2, the numbers 53 to 108 can be used as data output pins, wherein 56 pins in the numbers 53 to 108 are symmetrically arranged according to two columns of pins, and 1 pair of data grounding pins are arranged every 6 pairs of data output pins to provide grounding signals for a display panel accessed from the outside.
It will be appreciated that the pixel display signals received in the data output pins may be control signals for horizontal scanning, and that the display of each pixel in the display panel may be controlled by a row scan signal and a column scan signal.
And in combination with the tables 3 and 4, the first plug connector JH1 and the second plug connector JH2 are further provided with a plurality of groups of redundant pins, and the functions of the redundant pins can be designed in a self-defined manner according to the needs of users.
The first plug connector JH1 and the second plug connector JH2 are further provided with a plurality of groups of power supply pins and a plurality of groups of grounding pins, so that a plurality of power supplies and a plurality of paths of power supply inputs can be matched, and abundant pin settings are provided for application diversification of receiving equipment.
In one embodiment, in the first plug connector JH1 and the second plug connector JH2, a first empty space is provided between the grounding pin and the adjacent pin, and a second empty space is provided between the redundant pin and the adjacent pin, so that the redundant pin can be distinguished from other pin groups when the redundant pin is used for expanding the functions of the pins, and the problem of confusion or signal interference is avoided.
In one embodiment, the size of the empty space may be the same or different, and the size space may be set according to actual needs.
As shown in table 3 and table 4, a plurality of groups of network card signal pins are further arranged in the first plug connector JH1 and the second plug connector JH2, and the plurality of groups of network card signal pins are used for receiving network signals.
In one embodiment, the network card signal pin may be a gigabit network card signal pin for receiving gigabit network signals.
The embodiment of the utility model also provides a receiving system, which comprises: a receiving device as claimed in any one of the preceding claims.
In this embodiment, the receiving system includes a display panel and a main control chip, where the display screen is connected to the main control chip through any one of the receiving devices, and the main control chip sends a corresponding control signal to the receiving device through an instruction signal input by a user, and the control signal is forwarded to the display panel by the receiving device, so as to adjust a picture on the display panel.
Based on the receiving device in the embodiment, the receiving system of the utility model can be compatible with various types of display panels, and when a user changes the display panel, the same receiving device can still realize the signal interaction between the display panel and the main control chip without disassembly and reset.
The embodiment of the utility model also provides electronic equipment, which comprises: a display panel; and the receiving system according to the above embodiment, the receiving system is connected with the display panel.
It will be apparent to those skilled in the art that the foregoing functional units and circuits are merely illustrated for convenience and brevity of description, and in practical application, the foregoing functional allocation may be performed by different functional units and circuits, that is, the internal structure of the apparatus is divided into different functional units or circuits, so as to perform all or part of the functions described above. The functional units and circuits in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit, where the integrated units may be implemented in a form of hardware or a form of a software functional unit. In addition, the specific names of the functional units and the circuits are only for distinguishing from each other, and are not used for limiting the protection scope of the present utility model. The specific working process of the units and circuits in the above system may refer to the corresponding process in the foregoing method embodiment, which is not described herein again.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.
In the embodiments provided in the present utility model, it should be understood that the disclosed apparatus/terminal device and method may be implemented in other manners. For example, the apparatus/terminal device embodiments described above are merely illustrative, e.g., the division of circuits or elements is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple elements or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection via interfaces, devices or units, which may be in electrical, mechanical or other forms.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
The above embodiments are only for illustrating the technical solution of the present utility model, and are not limiting; although the utility model has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present utility model, and are intended to be included in the scope of the present utility model.
Claims (10)
1. A receiving apparatus, characterized in that the receiving apparatus comprises: the circuit board, the first plug connector and the second plug connector; wherein,
the first plug connector and the second plug connector are arranged on the circuit board;
the first plug connector comprises a first data output pin group, the second plug connector comprises a second data output pin group, the sum of the number of pins in the first data output pin group and the number of pins in the second data output pin group is 12N, and N is a positive integer;
and a plurality of pins in the first plug connector and the second plug connector are electrically connected with a plurality of bonding pad groups on the circuit board in a one-to-one correspondence manner.
2. The receiving device of claim 1, wherein the first plug and the second plug further comprise at least one of a control signal pin set, a serial peripheral interface signal pin set, a clock signal pin set, a power pin set, a ground pin set, and a load signal pin set.
3. The receiving device of claim 1 or 2, wherein the number of pins in the first data output pin group is the same as the number of pins in the second data output pin group.
4. The receiving device of claim 3, wherein the circuit board includes a first set of data pads and a second set of data pads thereon;
the plurality of bonding pads in the first data bonding pad group are connected with pins in the first data output pin group in a one-to-one correspondence manner, and the plurality of bonding pads in the second data bonding pad group are connected with pins in the second data output pin group in a one-to-one correspondence manner.
5. The receiving device of claim 3, wherein the number of pins in the first data output pin set and the number of pins in the second data output pin set are 12m, m being a positive integer.
6. The receiving device of claim 3, wherein a sum of the number of pins in the first data output pin set and the number of pins in the second data output pin set is 96.
7. The receiving device of claim 1, wherein the first connector couples a microprocessor and a memory chip.
8. The receiving device of claim 7, wherein the microprocessor is an FPGA chip.
9. A receiving system, comprising: the receiving device of any of claims 1-8.
10. An electronic device, comprising:
a display panel; and
the receiving system of claim 9, the receiving system being coupled to the display panel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321024158.3U CN220137930U (en) | 2023-04-28 | 2023-04-28 | Receiving equipment, receiving system and electronic equipment |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321024158.3U CN220137930U (en) | 2023-04-28 | 2023-04-28 | Receiving equipment, receiving system and electronic equipment |
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| Publication Number | Publication Date |
|---|---|
| CN220137930U true CN220137930U (en) | 2023-12-05 |
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|---|---|---|---|
| CN202321024158.3U Active CN220137930U (en) | 2023-04-28 | 2023-04-28 | Receiving equipment, receiving system and electronic equipment |
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| CN (1) | CN220137930U (en) |
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- 2023-04-28 CN CN202321024158.3U patent/CN220137930U/en active Active
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