CN220121869U - High-reflection sapphire wafer substrate and LED light source - Google Patents
High-reflection sapphire wafer substrate and LED light source Download PDFInfo
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- CN220121869U CN220121869U CN202223471491.7U CN202223471491U CN220121869U CN 220121869 U CN220121869 U CN 220121869U CN 202223471491 U CN202223471491 U CN 202223471491U CN 220121869 U CN220121869 U CN 220121869U
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- 239000000758 substrate Substances 0.000 title claims abstract description 72
- 229910052594 sapphire Inorganic materials 0.000 title claims abstract description 69
- 239000010980 sapphire Substances 0.000 title claims abstract description 69
- 239000003989 dielectric material Substances 0.000 claims abstract description 44
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 32
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 16
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 abstract description 15
- 239000000463 material Substances 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract description 4
- 238000000605 extraction Methods 0.000 abstract description 3
- 235000012431 wafers Nutrition 0.000 description 27
- 238000010586 diagram Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 238000009616 inductively coupled plasma Methods 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- 230000001788 irregular Effects 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
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- Surface Treatment Of Optical Elements (AREA)
Abstract
The utility model provides a high-reflection sapphire wafer substrate, which comprises: a sapphire substrate; the patterned dielectric material layer is arranged on the sapphire substrate, the material of the dielectric material layer is silicon dioxide, and the thickness of the dielectric material layer is 1.0-1.8 mu m; the refractive index of the dielectric material layer is lower than that of the sapphire substrate, the patterned dielectric material layer comprises a plurality of first protrusions which are arranged at intervals, and the cross section of each first protrusion along the vertical direction is a symmetrical pentagon. The high-reflection sapphire wafer substrate provided by the utility model has the advantages that the patterned substrate is subsequently sent for epitaxial growth, and the effects that the internal quantum efficiency and the light extraction rate of components can be achieved compared with the traditional patterned substrate made of sapphire can be achieved; further, the utility model can remarkably reduce the cost by etching the dielectric material layer.
Description
Technical Field
The utility model relates to a high-reflection sapphire wafer substrate and an LED light source.
Background
At present, an LED (light emitting diode) is solid lighting, has the advantages of small volume, low power consumption, long service life, high brightness, environmental protection, firmness, durability and the like, is accepted by consumers, and the scale of domestic LED production is gradually expanded; the demands on the brightness and light efficiency of LEDs in the market are increasing. Growing better epitaxial wafers is increasingly important because the quality of epitaxial layers is improved, and the performance of LED devices can be improved. The sapphire substrate is the most widely used substrate material in the semiconductor lighting industry, and the sapphire substrate patterning technology is the currently mainstream method for improving the light emitting efficiency of the semiconductor lighting device and the epitaxial crystallization quality. At present, in the existing epitaxial process, patterning is directly performed on a flat sapphire wafer substrate to increase the internal quantum efficiency of the epitaxial wafer and the light extraction rate of the component, but the cost required for patterning is high.
Disclosure of Invention
The utility model provides a high-reflection sapphire wafer substrate and an LED light source, which can effectively solve the problems.
The utility model is realized in the following way:
the embodiment of the utility model provides a high-reflection sapphire wafer substrate, which comprises the following steps:
a sapphire substrate;
the patterned dielectric material layer is arranged on the sapphire substrate, wherein the refractive index of the dielectric material layer is lower than that of the sapphire substrate, the patterned dielectric material layer comprises a plurality of first bulges arranged at intervals, the distance between the first bulges is defined as P, the maximum width of the first bulges is defined as D, the ratio of the width of D to the width of P is 5-15, the included angle formed by the inclined surface of the first bulges and the sapphire substrate is defined as Q, and theta is 30-60 degrees.
The embodiment of the utility model further provides an LED light source comprising the high-reflection sapphire wafer substrate.
The beneficial effects of the utility model are as follows: according to the preparation method of the high-reflection sapphire wafer substrate, the patterned substrate is subjected to subsequent epitaxial growth, so that the same effects as that of the conventional patterned substrate made of sapphire can be achieved, and the internal quantum efficiency and the light extraction rate of the component can be achieved; further, the utility model can remarkably reduce the cost by etching the dielectric material layer.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some examples of the present utility model and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of a preparation method of a high reflection sapphire wafer substrate provided by an embodiment of the present utility model.
Fig. 2 is a schematic structural diagram of a high reflection sapphire wafer substrate according to an embodiment of the present utility model.
Fig. 3 is a schematic diagram of a partial flow in a preparation method of a high reflection sapphire wafer substrate according to an embodiment of the present utility model.
Fig. 4 is a schematic structural diagram of a highly reflective sapphire wafer substrate according to another embodiment of the present utility model.
Fig. 5 is a schematic diagram of a partial flow in a preparation method of a high reflection sapphire wafer substrate according to another embodiment of the present utility model.
Fig. 6 is a schematic structural diagram of a highly reflective sapphire wafer substrate according to another embodiment of the present utility model.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present utility model more apparent, the technical solutions of the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model, and it is apparent that the described embodiments are some embodiments of the present utility model, but not all embodiments. All other embodiments, based on the embodiments of the utility model, which are apparent to those of ordinary skill in the art without inventive faculty, are intended to be within the scope of the utility model. Thus, the following detailed description of the embodiments of the utility model, as presented in the figures, is not intended to limit the scope of the utility model, as claimed, but is merely representative of selected embodiments of the utility model. All other embodiments, based on the embodiments of the utility model, which are apparent to those of ordinary skill in the art without inventive faculty, are intended to be within the scope of the utility model.
In the description of the present utility model, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present utility model, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
Referring to fig. 1, an embodiment of the present utility model provides a method for manufacturing a high reflection sapphire wafer substrate, including the following steps:
s1, providing a cleaned sapphire substrate 10;
s2, forming a dielectric material layer 12 on the surface of the sapphire substrate 10, wherein the refractive index of the dielectric material layer 12 is lower than that of the sapphire substrate 10;
s3, forming a photoresist layer 13 on the surface of the dielectric material layer 12, and opening an array pattern in a yellow light development mode;
s4, performing transverse etching and longitudinal etching on the dielectric material layer 12 under the graph by adopting ICP or Wet etching to form a patterned dielectric material layer 12';
and S5, removing the residual photoresist to obtain the high-reflection sapphire wafer substrate 100.
In step S1, the thickness and the dimension of the sapphire substrate 10 may be selected according to actual needs, which will not be described here. The step of cleaning the sapphire substrate 10 specifically includes:
immersing the sapphire substrate 10 in an acetone solution, performing auxiliary cleaning by ultrasonic waves, and drying after the cleaning is finished, thereby removing greasy dirt and dust on the sapphire substrate 10.
In step S2, siO having a film thickness of about 1.0 μm to 1.8 μm can be formed by PECVD (plasma enhanced chemical vapor deposition) or E-Gu 2 (silicon dioxide). The refractive index of silica is low, about 1.5. It will be appreciated that the present utility model is implemented by selecting a dielectric material (SiO 2 N-1.45) is patterned and then subjected to epitaxial growth, so that light can reach the total reflection effect at the bottom of the substrate from low refractive index to high refractive index. Preferably, the thickness of the silica is 1.2 μm to 1.6 μm. In one embodiment, the thickness of the silicon dioxide is about 1.5 μm.
In step S3, the method for forming the patterned photoresist layer is not limited to the prior art, and will not be described here. The shape of the pattern is not limited and may be selected according to practical needs, for example, a circular shape, a rectangular shape, a square shape, a triangular shape, a trapezoid shape, an elliptical shape, a regular pattern or an irregular geometric shape. The interval of the patterns can also be set according to actual needs, and the interval between the patterns is larger than or equal to the interval of the subsequent patterned silicon dioxide.
In step S4, the step of forming the patterned dielectric material layer 12' by performing lateral etching and longitudinal etching on the dielectric material layer 12 under the pattern using icp (inductively coupled plasma) or Wet etching includes:
the exposed dielectric material layer 12 is etched longitudinally and the unexposed dielectric material layer 12 is etched laterally, thereby forming a patterned dielectric material layer 12'.
It will be appreciated that the shape of the layer of dielectric material 12' may be adjusted by controlling different etching times. Specifically, referring to fig. 1-2, by adjusting the etching time, a protrusion (a land or a truncated cone) having a trapezoid cross section as shown in fig. 1-2 can be formed. Referring to fig. 3, by extending the etching time, a protrusion (cone, e.g., a triangular pyramid or a polygonal pyramid) having a triangular cross section as shown in fig. 3-4 may be formed.
Further, in the process of using ICP (inductively coupled plasma) or Wet etching, the concentration of etching gas or the concentration of etching liquid can be adjusted so that the speed of lateral etching is different, and irregular protrusions with different broken line structures are formed on the cross sections as shown in FIGS. 5-6. Specifically, the concentration of the whole etching gas can be reduced or increased; or to reduce or increase the concentration of the etching liquid so that the lateral etching speed is different.
Referring to fig. 2, an embodiment of the present utility model further provides a highly reflective sapphire wafer substrate 100, where the highly reflective sapphire wafer substrate 100 includes:
a sapphire substrate 10;
the patterned dielectric material layer 12' is disposed on the sapphire substrate 10, wherein the refractive index of the dielectric material layer 12' is lower than that of the sapphire substrate 10, and the patterned dielectric material layer 12' includes a plurality of first protrusions disposed at intervals, and the first protrusions are in the shape of prisms or truncated cones.
The material of the dielectric material layer 12 'is silicon dioxide, and the height of the dielectric material layer 12' is 1.0 μm-1.8 μm. Preferably, the thickness of the silica is 1.2 μm to 1.6 μm. In one embodiment, the thickness of the silicon dioxide is about 1.5 μm. The pitch of the first protrusions is defined as p, the width of the bottom of the first protrusions is D, the width of the top of the first protrusions is D, and the included angle formed by the inclined surfaces of the first protrusions and the sapphire substrate 10 is Q. In order to make the high reflection sapphire wafer substrate 100 have good total reflection effect, it is preferable that the D/P width ratio is between 5 and 15, θ is between 30 ° and 60 °, and the D/D width ratio is between 0.5 and 0.7. Preferably, the D/P width ratio is between 8 and 12, and θ is between 40 and 50. In one embodiment, the D/P width ratio is around 10, and θ is about 45, and the D/D width ratio is 0.6.
Referring to fig. 4, another embodiment of the present utility model further provides a highly reflective sapphire wafer substrate 200, where the highly reflective sapphire wafer substrate 200 includes:
a sapphire substrate 10;
the patterned dielectric material layer 12″ is disposed on the sapphire substrate 10, wherein the refractive index of the dielectric material layer 12″ is lower than that of the sapphire substrate 10, and the patterned dielectric material layer 12″ includes a plurality of second protrusions disposed at intervals, and the second protrusions are pyramid or cone shaped.
The material of the dielectric material layer 12 "is silicon dioxide, and the height of the dielectric material layer 12" is 1.0 μm-1.8 μm. Preferably, the thickness of the silica is 1.2 μm to 1.6 μm. In one embodiment, the thickness of the silicon dioxide is about 1.5 μm. The pitch of the second protrusions is defined as p, the maximum width of the second protrusions is defined as D, and an included angle formed by the inclined surface of the second protrusions and the sapphire substrate 10 is defined as Q. In order to provide the high reflection sapphire wafer substrate 200 with good total reflection, it is preferable that the D/P width ratio is 5 to 15 and θ is 30 ° to 60 °. Preferably, the D/P width ratio is between 8 and 12, and θ is between 40 and 50. In one embodiment, the D/P width ratio is about 10 and θ is about 45.
Referring to fig. 6, another embodiment of the present utility model further provides a highly reflective sapphire wafer substrate 300, where the highly reflective sapphire wafer substrate 300 includes:
a sapphire substrate 10;
the patterned dielectric material layer 12' "is disposed on the sapphire substrate 10, wherein the refractive index of the dielectric material layer 12 '" is lower than that of the sapphire substrate 10, and the patterned dielectric material layer 12' "includes a plurality of third protrusions disposed at intervals, and cross sections of the third protrusions along the vertical direction are symmetrical pentagons.
The material of the dielectric material layer 12 '"is silicon dioxide, and the height of the dielectric material layer 12'" is 1.0 μm to 1.8 μm. Preferably, the thickness of the silica is 1.2 μm to 1.6 μm. In one embodiment, the thickness of the silicon dioxide is about 1.5 μm. The third protrusion is defined as p, the maximum width of the third protrusion is D, an included angle formed by the first inclined surface of the third protrusion and the dielectric material layer 11 is Q1, and an included angle formed by the first inclined surface of the third protrusion and the second inclined surface of the third protrusion is Q2. In order to provide the high reflection sapphire wafer substrate 300 with good total reflection, it is preferable that the ratio of D/P width is 5-15, Q1 is 30-60 °, and Q2 is 100-170 °. Preferably, the D/P width ratio is between 8 and 12, and Q1 is between 40 and 50, and Q2 is between 120 and 150. In one embodiment, the D/P width ratio is about 10, and Q1 is about 45, and Q2 is about 135. Specifically, the angles of Q1 and Q2 may be controlled by controlling different concentrations.
The embodiment of the utility model further comprises the LED light source of the high-reflection sapphire wafer substrate 100/200/300.
The above description is only of the preferred embodiments of the present utility model and is not intended to limit the present utility model, and various modifications and variations may be made to the present utility model by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present utility model should be included in the protection scope of the present utility model.
Claims (8)
1. The utility model provides a high reflection sapphire wafer base plate which characterized in that includes:
a sapphire substrate;
the patterned dielectric material layer is arranged on the sapphire substrate, wherein the refractive index of the dielectric material layer is lower than that of the sapphire substrate, the patterned dielectric material layer comprises a plurality of first bulges arranged at intervals, the distance between the first bulges is defined as P, the maximum width of the first bulges is defined as D, the ratio of the width of D to the width of P is 5-15, the included angle formed by the inclined surface of the first bulges and the sapphire substrate is defined as Q, and theta is 30-60 degrees.
2. The highly reflective sapphire wafer substrate of claim 1, wherein the dielectric material layer is silicon dioxide.
3. The highly reflective sapphire wafer substrate of claim 2, wherein the dielectric material layer has a thickness of 1.0 μm to 1.8 μm.
4. The highly reflective sapphire wafer substrate of claim 1, wherein the first protrusions are in the shape of prisms or lands.
5. The highly reflective sapphire wafer substrate of claim 1, wherein the first protrusions are pyramid or cone shaped.
6. The highly reflective sapphire wafer substrate of claim 1, wherein the first protrusions have a cross-section in the vertical direction that is a symmetrical pentagon.
7. The highly reflective sapphire wafer substrate of claim 6, wherein the first inclined surface of the first bump and the dielectric material layer define an angle Q1, the first inclined surface of the first bump and the second inclined surface define an angle Q2, Q1 is between 30 ° and 60 °, and Q2 is between 100 ° and 170 °.
8. An LED light source comprising the highly reflective sapphire wafer substrate of any of claims 1-7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223471491.7U CN220121869U (en) | 2022-12-23 | 2022-12-23 | High-reflection sapphire wafer substrate and LED light source |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223471491.7U CN220121869U (en) | 2022-12-23 | 2022-12-23 | High-reflection sapphire wafer substrate and LED light source |
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| Publication Number | Publication Date |
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| CN220121869U true CN220121869U (en) | 2023-12-01 |
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| CN202223471491.7U Active CN220121869U (en) | 2022-12-23 | 2022-12-23 | High-reflection sapphire wafer substrate and LED light source |
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Address after: No. 101, Xiangxing Road, Industrial Zone, Xiamen Torch High-tech Zone (Xiang'an), Xiamen, Fujian, 361115 Patentee after: Purui Optoelectronics (Xiamen) Co.,Ltd. Country or region after: China Address before: No. 101, Xiangxing Road, Industrial Zone, Xiamen Torch High-tech Zone (Xiang'an), Xiamen, Fujian, 361115 Patentee before: KAISTAR LIGHTING (XIAMEN) Co.,Ltd. Country or region before: China |