CN220121827U - Packaging structure for semiconductor component - Google Patents
Packaging structure for semiconductor component Download PDFInfo
- Publication number
- CN220121827U CN220121827U CN202321667590.4U CN202321667590U CN220121827U CN 220121827 U CN220121827 U CN 220121827U CN 202321667590 U CN202321667590 U CN 202321667590U CN 220121827 U CN220121827 U CN 220121827U
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- CN
- China
- Prior art keywords
- cooling
- heat dissipation
- packaging layer
- packaging
- partition plate
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 93
- 239000004065 semiconductor Substances 0.000 title claims abstract description 73
- 238000001816 cooling Methods 0.000 claims abstract description 80
- 230000017525 heat dissipation Effects 0.000 claims abstract description 47
- 239000000872 buffer Substances 0.000 claims abstract description 36
- 239000010410 layer Substances 0.000 claims description 60
- 238000005192 partition Methods 0.000 claims description 23
- 239000011229 interlayer Substances 0.000 claims description 11
- 238000007789 sealing Methods 0.000 claims description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 4
- 238000005253 cladding Methods 0.000 claims description 2
- 230000009977 dual effect Effects 0.000 abstract description 3
- 230000005855 radiation Effects 0.000 description 13
- 239000002826 coolant Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229920006247 high-performance elastomer Polymers 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Abstract
The utility model provides a packaging structure for a semiconductor component, which comprises a semiconductor element, wherein the top and the bottom of the semiconductor element are respectively provided with a packaging plate, radiating fins are arranged on the packaging plates, one side, far away from the semiconductor element, of the packaging plates is provided with a cooling packaging layer, the bottoms of the radiating fins are in contact with the outer surface of the semiconductor element, the upper ends of the radiating fins are arranged in the cooling packaging layer, a flow guide component is arranged in the cooling packaging layer, the outer side of the semiconductor element is coated with an outer packaging layer, the packaging plates and the cooling packaging layer are both arranged in the outer packaging layer, and a buffer mechanism is arranged between the packaging plates and the semiconductor element. The utility model combines the heat conduction and heat dissipation of the heat dissipation fins and the cooling and heat dissipation of the cooling packaging layer by arranging a series of structures, realizes the dual heat dissipation function of the semiconductor component packaging structure, has good heat dissipation performance, and increases the cooling and circulating space area by the continuous U-shaped structure flow channel, and has large cooling and circulating heat dissipation surface and rapid heat dissipation.
Description
Technical Field
The utility model relates to the technical field of semiconductor packaging, in particular to a packaging structure for a semiconductor component.
Background
A semiconductor device is an electronic device whose conductivity is between that of a good conductor and an insulator, and which can perform a specific function by utilizing the special electrical characteristics of a semiconductor material, and is widely used for generating, controlling, receiving, converting, amplifying a signal, and performing energy conversion. The semiconductor material used in the semiconductor device is silicon, germanium or gallium arsenide, and can be used as equipment such as rectifiers, oscillators, light emitters, amplifiers, photometers and the like.
The packaging layer arranged outside the semiconductor component can cover and protect the semiconductor element packaged inside, but the heat dissipation of the semiconductor element is inevitably blocked by the packaging at the same time, so that the heat of the semiconductor element in the packaging layer cannot be rapidly dissipated, the semiconductor element has high temperature and is easy to consume, and the semiconductor component has simple heat dissipation holes, small heat dissipation space and heat dissipation surface, slow heat dissipation and poor effect.
Disclosure of Invention
Aiming at the defects of the prior art, the utility model provides a packaging structure for a semiconductor component, which has good heat dissipation performance.
The technical scheme adopted for solving the technical problems is as follows:
the utility model provides a packaging structure for semiconductor components, includes semiconductor component, semiconductor component's top and bottom all are equipped with the package plate, be equipped with cooling fin on the package plate, one side that semiconductor component was kept away from to the package plate is equipped with the cooling packaging layer, cooling fin's bottom and semiconductor component's surface contact setting, cooling packaging layer's inside is located to cooling fin's upper end, cooling packaging layer's inside is equipped with the water conservancy diversion subassembly, semiconductor component's outside cladding is equipped with outer packaging layer, the inside of outer packaging layer is all located to package plate and cooling packaging layer, be equipped with buffer gear between package plate and the semiconductor component.
Preferably, the water conservancy diversion subassembly includes baffle, no. two baffles, circulation breach and flow channel, and the inside of cooling packaging layer is equipped with baffle and No. two baffles, and interval distribution sets up between baffle and No. two baffles, all is equipped with the circulation breach between baffle and No. two baffles's one end and the cooling packaging layer inner wall, is equipped with the flow channel between two adjacent baffles and No. two baffles, through the integrative setting of circulation breach intercommunication between the flow channel, and the one end of cooling packaging layer is equipped with the inflow port, and the other end of cooling packaging layer is equipped with the egress opening.
Preferably, the flow channel is arranged in a U-shaped structure, and the upper ends of the radiating fins are arranged in the flow channel.
Preferably, the buffer mechanism comprises a buffer interlayer and a buffer block, the buffer interlayer is arranged between the packaging plate and the semiconductor element in a packaging mode, and the buffer block is arranged in the buffer interlayer.
Preferably, the buffer block is arranged in a hemispherical structure, and the buffer block is arranged in one-to-one correspondence with the first partition board and the second partition board inside the cooling packaging layer.
Preferably, the heat dissipation fins comprise a first heat dissipation fin and a second heat dissipation fin, the first heat dissipation fin is arranged between the packaging plate and the semiconductor element, the top of the first heat dissipation fin penetrates through the packaging plate to be connected with the second heat dissipation fin, the second heat dissipation fin is arranged in the flow channel, and the second heat dissipation fin is provided with a flow opening.
Preferably, a sealing sheet is arranged between the second radiating sheet and the packaging plate.
Compared with the prior art, the utility model has the beneficial effects that:
1. according to the packaging structure for the semiconductor component, the outer packaging layer is coated on the outer side of the semiconductor component, the packaging plate and the cooling packaging layer are arranged in the inner packaging of the outer packaging layer, the radiating fins are arranged on the packaging plate, and the heat conduction and the heat dissipation of the radiating fins are combined with the cooling and heat dissipation of the cooling packaging layer, so that the dual heat dissipation function of the packaging structure of the semiconductor component is realized, and the heat dissipation performance is better.
2. According to the packaging structure for the semiconductor component, the first partition plate and the second partition plate are arranged in the cooling packaging layer, the first partition plate and the second partition plate divide the internal cooling space of the cooling packaging layer through the circulation gaps to form a continuous U-shaped structure flow channel, the cooling circulation space area is increased, and the cooling circulation cooling surface is large and the cooling is fast due to the combination of the circulation openings on the second cooling fins.
Drawings
FIG. 1 is a schematic overall structure of embodiment 1 of the present utility model;
FIG. 2 is a schematic diagram of a cooling package layer in embodiment 1 of the present utility model;
fig. 3 is a schematic structural diagram of a heat sink fin according to embodiment 2 of the present utility model.
In the figure: 1. a semiconductor element; 2. a package plate; 3. cooling the encapsulation layer; 31. a first partition board; 32. a second separator; 33. a flow gap; 34. a flow channel; 35. an inflow port; 36. an outflow port; 4. a heat radiation fin; 41. a first heat sink; 42. a second heat sink; 421. a flow port; 43. a sealing sheet; 5. an outer encapsulation layer; 6. a buffer interlayer; 7. and a buffer block.
Detailed Description
The technical scheme of the present utility model will be clearly and completely described below with reference to the accompanying drawings.
Example 1: as shown in fig. 1 and 2, the package structure for a semiconductor component of this embodiment includes a semiconductor element 1, wherein the top and bottom of the semiconductor element 1 are both provided with a package board 2, a heat dissipation fin 4 is provided on the package board 2, one side of the package board 2 away from the semiconductor element 1 is provided with a cooling package layer 3, the bottom of the heat dissipation fin 4 is disposed in contact with the outer surface of the semiconductor element 1, the upper end of the heat dissipation fin 4 is disposed in the cooling package layer 3, a flow guiding component is disposed in the cooling package layer 3, the outer side of the semiconductor element 1 is coated with an outer package layer 5, the package board 2 and the cooling package layer 3 are both disposed in the outer package layer 5, a buffer mechanism is disposed between the package board 2 and the semiconductor element 1, the package board 2 is provided with the heat dissipation fin 4, two opposite sides of the semiconductor element 1 are provided with pins, the pins are disposed to penetrate through the outer package layer 5 in a sealing manner, the heat dissipation of the heat dissipation fin 4 is combined with the heat dissipation of the cooling package layer 2, and the heat dissipation of the semiconductor element package structure is realized, and the heat dissipation performance of the semiconductor component package structure is better.
Specifically, the water conservancy diversion subassembly includes baffle 31, no. two baffles 32, circulation breach 33 and flow channel 34, the inside of cooling packaging layer 3 is equipped with baffle 31 and No. two baffles 32, interval distribution sets up between baffle 31 and No. two baffles 32, all be equipped with circulation breach 33 between baffle 31 and No. two baffles 32's one end and the cooling packaging layer 3 inner wall, be equipped with flow channel 34 between two adjacent baffles 31 and No. two baffles 32, through the integrative setting of circulation breach 33 intercommunication between the flow channel 34, the one end of cooling packaging layer 3 is equipped with inflow port 35, the other end of cooling packaging layer 3 is equipped with egress port 36, inflow port 35, egress port 36 are connected with the cooling medium circulation mechanism for the cooling through external pipeline, increase the inside cooling circulation space area of cooling packaging layer 3.
Further, the flow channel 34 is arranged in a U-shaped structure, the upper ends of the heat dissipation fins 4 are arranged in the flow channel 34, the flow channel 34 is continuous, and the heat dissipation medium in the flow channel 34 flows through the upper ends of the heat dissipation fins 4, so that heat dissipation is fast.
Further, the buffer mechanism comprises a buffer interlayer 6 and a buffer block 7, the buffer interlayer 6 is arranged between the packaging plate 2 and the semiconductor element 1 in a packaged mode, the buffer block 7 is arranged in the buffer interlayer 6, the buffer block 7 is made of a high-performance rubber material with buffer elasticity, and the buffer block 7 is used for buffering and supporting between the packaging plate 2 and the semiconductor element 1.
Furthermore, the buffer block 7 is arranged in a hemispherical structure, the buffer block 7 is arranged in one-to-one correspondence with the first partition plate 31 and the second partition plate 32 inside the cooling packaging layer 3, and the packaging support between the packaging board 2 and the semiconductor element 1 is stable.
The application method of the embodiment is as follows: the packaging plate 2 and the cooling packaging layer 3 carrying the heat radiation fins 4 are packaged in the outer packaging layer 5 of the semiconductor element 1, the buffer block 7 in the buffer interlayer 6 between the packaging plate 2 and the semiconductor element 1 buffers and supports the semiconductor element 1, the ends of the inflow opening 35 and the outflow opening 36 on the cooling packaging layer 3 are exposed out of the outer packaging layer 5, the heat radiation fins 4 transfer heat generated inside the semiconductor element 1 into the cooling packaging layer 3 through the heat conduction transmission performance of the heat radiation fins, a heat radiation medium enters the cooling packaging layer 3 from the inflow opening 35, the first partition plate 31 and the second partition plate 32 divide the internal cooling space of the cooling packaging layer 3 through the circulation notch 33 to form a continuous U-shaped structure flow channel 34, the heat radiation medium flows through the cooling packaging layer 3 through the flow channel 34, the heat radiation fin 4 is discharged out of the cooling packaging layer 3 through the outflow opening 36, the heat radiation of the heat radiation fins 4 is combined with the cooling heat radiation of the cooling packaging layer 3, the dual heat radiation function of the semiconductor element packaging structure is realized, the heat radiation performance is better, the continuous U-shaped structure flow channel 34 inside the cooling packaging layer 3 is increased, the cooling space area is increased, and the heat radiation is fast.
Example 2: the structure of the package structure for a semiconductor device of this embodiment is substantially the same as that of the package structure for a semiconductor device of embodiment 1, except that: the radiator fins 4 include a first radiator fin 41 and a second radiator fin 42 (see fig. 3). A first cooling fin 41 is arranged between the packaging plate 2 and the semiconductor element 1, the top of the first cooling fin 41 penetrates through the packaging plate 2 and is connected with a second cooling fin 42, the second cooling fin 42 is arranged in the flow channel 34, a circulation port 421 is formed in the second cooling fin 42, the first cooling fin 41 conducts heat to the second cooling fin 42 through the heat conduction and transfer performance of the cooling fin, the heat is conducted to a cooling medium in the cooling packaging layer 3 through the second cooling fin 42, and the circulation port 421 on the second cooling fin 42 increases the contact heat dissipation area of the cooling fin and the cooling medium.
Specifically, a sealing sheet 43 is provided between the second heat sink 42 and the package plate 2 to seal the cooling package layer 2.
Finally, it should be noted that: the above description is only a preferred embodiment of the present utility model, and is not intended to limit the present utility model, and those skilled in the art may make modifications and equivalents to the technical solutions described in the foregoing embodiments. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present utility model should be included in the protection scope of the present utility model.
Claims (7)
1. The package structure for semiconductor components comprises a semiconductor element (1), and is characterized in that: the top and the bottom of semiconductor component (1) all are equipped with package board (2), be equipped with radiator fin (4) on package board (2), one side that semiconductor component (1) was kept away from to package board (2) is equipped with cooling packaging layer (3), the bottom of radiator fin (4) and the surface contact setting of semiconductor component (1), the inside of cooling packaging layer (3) is located to radiator fin (4)'s upper end, the inside of cooling packaging layer (3) is equipped with the water conservancy diversion subassembly, the outside cladding of semiconductor component (1) is equipped with outer packaging layer (5), the inside of outer packaging layer (5) is all located to package board (2) and cooling packaging layer (3), be equipped with buffer gear between package board (2) and semiconductor component (1).
2. The package structure for semiconductor components according to claim 1, wherein: the flow guide assembly comprises a first partition plate (31), a second partition plate (32), a flow gap (33) and a flow channel (34), wherein the first partition plate (31) and the second partition plate (32) are arranged inside the cooling packaging layer (3), the first partition plate (31) and the second partition plate (32) are arranged in a spaced mode, the flow gap (33) is formed between one ends of the first partition plate (31) and the second partition plate (32) and the inner wall of the cooling packaging layer (3), the flow channel (34) is arranged between two adjacent first partition plates (31) and the second partition plate (32), the flow channel (34) is integrally connected through the flow gap (33), an inflow opening (35) is formed in one end of the cooling packaging layer (3), and an outflow opening (36) is formed in the other end of the cooling packaging layer (3).
3. The package structure for semiconductor components according to claim 2, wherein: the flow channel (34) is arranged in a U-shaped structure, and the upper ends of the radiating fins (4) are arranged in the flow channel (34).
4. The package structure for semiconductor components according to claim 2, wherein: the buffer mechanism comprises a buffer interlayer (6) and a buffer block (7), the buffer interlayer (6) is arranged between the packaging plate (2) and the semiconductor element (1) in a packaged mode, and the buffer block (7) is arranged in the buffer interlayer (6).
5. The package structure for semiconductor devices according to claim 4, wherein: the buffer block (7) is arranged in a hemispherical structure, and the buffer block (7) is arranged in one-to-one correspondence with a first partition plate (31) and a second partition plate (32) in the cooling packaging layer (3).
6. The package structure for semiconductor components according to claim 2, wherein: the heat dissipation fin (4) comprises a first heat dissipation fin (41) and a second heat dissipation fin (42), the first heat dissipation fin (41) is arranged between the packaging plate (2) and the semiconductor element (1), the top of the first heat dissipation fin (41) penetrates through the packaging plate (2) to be connected with the second heat dissipation fin (42), the second heat dissipation fin (42) is arranged in the flow channel (34), and the second heat dissipation fin (42) is provided with a flow opening (421).
7. The package structure for semiconductor components as defined in claim 6, wherein: and a sealing sheet (43) is arranged between the second radiating sheet (42) and the packaging plate (2).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321667590.4U CN220121827U (en) | 2023-06-28 | 2023-06-28 | Packaging structure for semiconductor component |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321667590.4U CN220121827U (en) | 2023-06-28 | 2023-06-28 | Packaging structure for semiconductor component |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN220121827U true CN220121827U (en) | 2023-12-01 |
Family
ID=88896474
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202321667590.4U Active CN220121827U (en) | 2023-06-28 | 2023-06-28 | Packaging structure for semiconductor component |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN220121827U (en) |
-
2023
- 2023-06-28 CN CN202321667590.4U patent/CN220121827U/en active Active
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| GR01 | Patent grant | ||
| GR01 | Patent grant |