CN220108613U

CN220108613U - Semiconductor memory

Info

Publication number: CN220108613U
Application number: CN202321132522.8U
Authority: CN
Inventors: 童宇诚; 张钦福
Original assignee: Fujian Jinhua Integrated Circuit Co Ltd
Current assignee: Fujian Jinhua Integrated Circuit Co Ltd
Priority date: 2023-05-11
Filing date: 2023-05-11
Publication date: 2023-11-28
Anticipated expiration: 2033-05-11

Abstract

The utility model relates to the technical field of semiconductor memories, and provides a semiconductor memory. The semiconductor memory includes a substrate, a connection layer disposed on the substrate, and a capacitor structure disposed on the connection layer. The connecting layer comprises a connecting pad array, a peripheral structure adjacent to the connecting pad array and a plurality of first extending pads arranged between the peripheral structure and the connecting pad array, wherein part of bottom electrodes of the capacitor structure are arranged on the first extending pads, so that the peripheral part of the capacitor structure is supported more, and the defects of deformation or collapse are reduced.

Description

Semiconductor memory

Technical Field

The present utility model relates to semiconductor memory technology, and more particularly, to a semiconductor memory including a connection layer and a capacitor structure disposed on the connection layer.

Background

The dynamic random access memory (dynamic random access memory, DRAM) is a volatile memory, and includes an array area (array area) formed by a plurality of memory cells (memory cells) and a peripheral area (peripheral area) formed by a control circuit. Each memory cell is composed of a transistor (transducer) and a capacitor (capacitor) electrically connected with the transistor, and the transistor controls the storage or release of charges in the capacitor to achieve the purpose of storing data. Control circuitry controls access of data to each memory cell by addressing each memory cell through Word Lines (WL) and Bit Lines (BL) that span the array region and are electrically connected to each memory cell.

To reduce the size of memory cells to produce chips with higher density, the structure of memory cells has been advanced toward three-dimensional (three-dimensional) technology, such as using buried word line (word line) and stacked capacitors (stacked capacitor). The stacked capacitor is vertically arranged above the substrate, thereby saving the substrate area occupied by the capacitor and conveniently obtaining larger capacitance by increasing the electrode height of the capacitor. However, as the height increases, problems with tipping of the capacitive structure, particularly in the portions adjacent to the peripheral region, often occur.

Disclosure of Invention

In view of this, the present utility model provides a semiconductor memory including a stacked capacitor (stacked capacitor) whose bottom electrode is electrically connected to a circuit element of a substrate through a connection layer provided under the capacitor structure. The semiconductor memory can solve the problem that the capacitor structure, particularly the part adjacent to the peripheral area, is prone to toppling along with the increase of the height in the prior art.

An embodiment of the utility model provides a semiconductor memory, which comprises a substrate, a connecting layer arranged on the substrate, and a capacitor structure arranged on the connecting layer. The connection layer comprises a connection pad array, a peripheral structure and a plurality of extension pads, wherein the connection pad array comprises a plurality of connection pads arranged along a first direction and a second direction, the peripheral structure comprises a first edge and a second edge which are adjacent to two adjacent sides of the connection pad array, and the plurality of first extension pads are arranged between the first edge and the connection pad array. The capacitor structure comprises a plurality of bottom electrodes, wherein 1 bottom electrode is respectively arranged on the connecting pad, and 2 bottom electrodes are respectively arranged on the first extending pad.

Another embodiment of the present utility model provides a semiconductor memory device including a substrate, a connection layer disposed on the substrate, and a capacitor structure disposed on the connection layer. The connecting layer comprises a connecting pad array, a peripheral structure and a plurality of connecting pads, wherein the connecting pad array comprises a plurality of connecting pads which are arranged along a first direction and a second direction, the peripheral structure comprises a first edge and a second edge which are adjacent to two adjacent sides of the connecting pad array, and a plurality of first extending pads and a plurality of second extending pads which are alternately arranged between the first edge and the connecting pad array. Along the first direction, the length of the first extension pad is greater than the length of the second extension pad. The capacitor structure comprises a plurality of bottom electrodes, wherein 1 bottom electrode is respectively arranged on the connecting pad, n+1 bottom electrodes are respectively arranged on the first extending pad, and N bottom electrodes are respectively arranged on the second extending pad.

Advantageous effects

According to the utility model, the extension pad is arranged in the connecting layer, and the bottom electrode (the dummy bottom electrode) at the outer side part of the capacitor structure is selectively arranged on the extension pad, so that the peripheral region part of the capacitor structure can be supported more, the defect of deformation or collapse is reduced, the capacitor structure with better integrity is obtained, and the stability and quality of the whole semiconductor memory are improved.

Drawings

The accompanying drawings provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. These drawings and description serve to illustrate principles of some embodiments. It should be noted that all illustrations are schematic, and relative dimensions and proportions are adjusted for ease of illustration and drawing. The same reference signs represent corresponding or similar features in different embodiments.

Fig. 1 is a schematic plan view of a semiconductor memory according to an embodiment of the present utility model.

Fig. 2 is a partially enlarged schematic view of the semiconductor memory shown in fig. 1.

FIG. 3 is a schematic cross-sectional view of the semiconductor memory device shown in FIG. 2 along the AA' line.

Fig. 4 is a schematic cross-sectional view of the semiconductor memory shown in fig. 2 along a BB' tangent line.

Fig. 5 is a partially enlarged schematic view of a semiconductor memory according to an embodiment of the utility model.

Fig. 6 is a partially enlarged schematic illustration of a semiconductor memory according to an embodiment of the utility model.

Fig. 7 is a partially enlarged schematic illustration of a semiconductor memory according to an embodiment of the utility model.

Fig. 8 is a partially enlarged schematic view of a semiconductor memory according to an embodiment of the present utility model.

Wherein reference numerals are as follows:

Detailed Description

The following description of the preferred embodiments of the present utility model will be presented to enable those skilled in the art to which the utility model pertains and to further illustrate the utility model and its advantages. Those of skill in the art will be able to make substitutions, rearrangements, and combinations of features from several different embodiments to accomplish other embodiments without departing from the spirit of the utility model by referring to the following examples.

Referring to fig. 1, a schematic plan view of a semiconductor memory 100 according to an embodiment of the utility model is shown. The semiconductor memory 100 includes a substrate 10, such as a silicon (Si) substrate, an epitaxial silicon (epi-Si) substrate, a silicon germanium (SiGe) substrate, a silicon carbide (SiC) substrate, or a silicon-on-insulator (SOI) substrate, but is not limited thereto. The substrate 10 includes at least one cell area CA and a peripheral area PA adjoining the edge of the cell area CA. The cell area CA is an area where memory cells (memory cells) are arranged, and is separated from other circuit areas of the substrate 10 by the peripheral area PA. In some embodiments, the periphery of the cell area CA is completely surrounded by the peripheral area PA.

Please refer to fig. 2, fig. 3 and fig. 4. Fig. 2 is an enlarged plan view schematically illustrating an area a of the semiconductor memory 100 shown in fig. 1. The area a includes a corner (corner port) of the cell area CA and a peripheral area PA in the vicinity. Fig. 3 is a schematic cross-sectional view of the semiconductor memory 100 cut along the AA' line indicated in fig. 2. Fig. 4 is a schematic cross-sectional view of the semiconductor memory 100 cut along the BB' line indicated in fig. 2. For simplicity of illustration, some of the constituent components shown in the cross-sectional views of fig. 3 and 4 (e.g., the contact plug 14, the capacitor structure CAP, the support layer 18, the capacitor dielectric layer 34, the top electrode 36, the planar layer 40, etc.) are not shown in the plan view of fig. 2.

The semiconductor memory 100 is a Dynamic Random Access Memory (DRAM) including a stacked capacitor, and includes a connection layer 20 disposed on a substrate 10 and a capacitor structure CAP disposed on the connection layer 20. Circuit elements, such as transistors, buried word lines, bit lines, conductive plugs, for controlling the read and write operations of the memory cells may be included in the substrate 10 or on the substrate 10. For simplicity of illustration, the circuit elements are not shown.

The capacitor structure CAP is a bump structure disposed on the connection layer 20, and overlaps directly above the cell area CA and extends to partially overlap the peripheral area PA. The capacitive structure CAP includes a plurality of bottom electrodes 32 vertically standing on the connection layer 20, a capacitive dielectric layer 34 overlying the surface of the bottom electrodes 32, and a top electrode 36 overlying the capacitive dielectric layer 34 and capacitively coupled to the bottom electrodes 32 through the capacitive dielectric layer 34. The bottom electrode 32 and the top electrode 36 each comprise a conductive material, such as a metal, a suitable metal, such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or a compound, alloy, and/or composite layer of the foregoing metal materials, but are not limited thereto. In some embodiments, the top electrode 36 may comprise a semiconductor material, such as polysilicon. The material of the capacitive dielectric layer 34 may include silicon oxide (SiO) ₂ ) Silicon nitrideSiN), or a high-k dielectric, but is not limited thereto.

The capacitor structure CAP further includes at least one support layer 18 extending horizontally between the bottom electrodes 32 of the capacitor structure CAP, directly contacting and supporting each bottom electrode 32. In some embodiments, an etch stop layer 16 may be disposed between the capacitor structure CAP and the connection layer 20, wherein the bottom of the bottom electrode 32 penetrates the etch stop layer 16 to directly contact the conductive structure (e.g., the connection pad 22) of the connection layer 20. The support layer 18 and the etch stop layer 16 each include a dielectric material such as, but not limited to, silicon nitride (SiN), silicon carbide (SiC), silicon carbide nitride (SiCN), nitrogen doped silicon carbide (nitride doped silicon carbide, NDC).

The planarization layer 40 is disposed on the connection layer 20 for planarizing the surface topography caused by the capacitor structure CAP, and the top surface is substantially flush with the top surface of the capacitor structure CAP. The planarization layer 40 may include a dielectric material, such as silicon oxide (SiO ₂ ) But is not limited thereto. In some embodiments, the planarization layer 40 may be located on the etch stop layer 16 while the etch stop layer 16 outside the capacitive structure CAP remains on the connection layer 20.

The connection layer 20 is arranged between the capacitive structure CAP and the substrate 10 and comprises a dielectric layer and a conductive structure arranged in the dielectric layer. For example, as shown in fig. 2, 3 and 4, the connection layer 20 may include a first dielectric layer 12, a contact plug 14 disposed in the first dielectric layer 12, a second dielectric layer 26, and a connection pad 22, a peripheral structure 24, and an extension pad 25 disposed between the connection pad 22 and the peripheral structure 24, disposed in the second dielectric layer 26. The first dielectric layer 12 and the second dielectric layer 26 comprise a dielectric material, such as silicon oxide (SiO) ₂ ) Silicon nitride (SiN), but is not limited thereto. The contact plug 14, the connection pad 22, the peripheral structure 24, and the extension pad 25 (including the first extension pad P1, the second extension pad P2, the third extension pad P3, the fourth extension pad P4, and the fifth extension pad P5) include conductive materials, such as metals, and suitable metals may include tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or compounds, alloys, and/or composite layers of the foregoing metal materials, but are not limited thereto. According to one embodiment of the utility model, the connection pad 22, the peripheral structure 24 and the extension pad25 is obtained by patterning the same conductive layer.

The connection pads 22 are substantially located directly above the cell area CA of the substrate 10, are island-like structures separated from each other, and are arranged along the first direction DR1 and the second direction DR2 to form a connection pad array 22A. The connection pads 22 are respectively contacted with a bottom electrode 32 of the capacitor structure CAP, and then contacted with a contact plug 14 in the first dielectric layer 12, so as to electrically connect the bottom electrode 32 to a corresponding circuit element in the substrate 10 or on the substrate 10. The bottom electrodes 32 contacting the connection pads 22 are respectively a storage node (storage node) of the semiconductor memory 100.

Peripheral structure 24 is located substantially directly above peripheral region PA of substrate 10, and preferably extends continuously along the outside of bond pad array 22A to partially or completely surround bond pad array 22A. For ease of illustration, the edges of the peripheral structure 24 adjacent to the two sides of the connection pad array 22A shown in fig. 2 are defined herein as a first edge 24a and a second edge 24b, and the portion connected between the first edge 24a and the second edge 24b is defined herein as a third edge 24c. The first edge 24a, the second edge 24b, and the third edge 24c each extend in a different direction and may have the same or different profiles. In some embodiments, the first edge 24a and the second edge 24b extend in directions perpendicular to each other. In some embodiments, the first edge 24a has a straight line profile, the second edge 24b has a wavy profile, and the third edge 24c may have a straight line profile or an arcuate profile.

The extension pads 25 are disposed between the peripheral structure 24 and the connection pad array 22A, and may have different shapes and lengths according to the location. For convenience of explanation, the extension pad 25 is divided into a first extension pad P1, a second extension pad P2, a third extension pad P3, a fourth extension pad P4 and a fifth extension pad P5 according to the position and shape of the extension pad 25, and features are described below.

The first extension pads P1 and the second extension pads P2 are alternately arranged between the first edge 24a and the connection pad array 22A, respectively, in a long segment (long segment) structure, and the long axis extends along the first direction DR1, aligned with the connection pad 22 along the first direction DR 1. The first extension pad P1 is separated from the first edge 24a by the second dielectric layer 26 without direct contact, and the second extension pad P2 has one end connected to the first edge 24a and the other end aligned with the end of the adjacent first extension pad P1 along the second direction DR 2. The major axis of the first extension pad P1 has a length L1, and the major axis of the second extension pad P2 has a length L2. In some embodiments, length L1 is greater than length L2.

The third extension pad P3 is disposed between the third edge 24c and the connection pad array 22A, separated from direct contact with the third edge 24c by the second dielectric layer 26. The third extension pad P3 has a long segment structure and a long axis extending along the first direction DR1, and is aligned with the connection pad 22 along the first direction DR 1. The long axis of the third extension pad P3 has a length L3. In some embodiments, length L1 is greater than length L3. In some embodiments, length L1 and length L2 are both greater than length L3.

The fourth extension pad P4 is arranged between the second edge 24b and the connection pad array 22A, and is separated from direct contact with the second edge 24b by the second dielectric layer 26. The fourth extension pad P4 may be an island structure in which a distinct major axis and a minor axis are not distinguished, or a short segment (short segment) structure in which the length of the major axis is only slightly longer than that of the minor axis. In some embodiments, the fourth extension pads P4 are arranged along the wavy profile of the second edge 24b and are disposed in an orientation with the long axis alternately parallel to the first direction DR1 or the second direction DR 2. The long axis of the fourth extension pad P4 has a length L4. In some embodiments, length L3 is greater than length L4.

The fifth extension pad P5 is disposed between the first extension pad P1 and the third extension pad P3, and has one end connected to the third edge 24c. The fifth extension pad P5 has a long-segment structure and has a long axis extending along the first direction DR1, and is aligned with the connection pad 22 along the first direction DR 1. The major axis of the fifth extension pad P5 has a length L5. In some embodiments, length L5 is greater than length L3 and less than length L1. In some embodiments, length L5 is less than length L1 and length L2.

In some embodiments, the peripheral structure 24 and the extension pad 25 (including the first extension pad P1, the second extension pad P2, the third extension pad P3, the fourth extension pad P4, and the fifth extension pad P5) are not electrically connected to the outside and are electrically floating.

The present utility model is characterized in that by selectively disposing the bottom electrode 32 (which is an electrically floating dummy bottom electrode) on the extension pad 25, the portion of the peripheral area PA of the capacitor structure CAP can be supported more, the defect that the capacitor structure CAP in the area is deformed or collapsed is reduced, the capacitor structure CAP with better integrity is obtained, and the stability of the overall semiconductor memory 100 is improved.

In addition, the number of bottom electrodes 32 disposed on the extension pad may be different depending on the length and position of the extension pad. For example, when N bottom electrodes 32 are disposed on the second extension pad P2, n+1 bottom electrodes 32 may be disposed on the first extension pad P1 having a length longer than that of the second extension pad P2. As for the third, fourth and fifth extension pads P3, P4 and P5 having a length smaller than that of the second extension pad P2, N or N-1 bottom electrodes 32 may be provided, respectively, or any bottom electrode 32 may not be provided. According to one embodiment of the present utility model, N is preferably equal to 0, 1 or 2. Some embodiments of the layout of the bottom electrode 32 and the extension pad 25 will be described below to assist those skilled in the art in understanding the present utility model.

Referring to the embodiment shown in fig. 2, the first extension pad P1 is respectively provided with 2 bottom electrodes 32, the second extension pad P2 and the fifth extension pad P5 are respectively provided with 1 bottom electrode 32, the fourth extension pad P4 is provided with 1 bottom electrode 32 at intervals, and the third extension pad P3 is not provided with any bottom electrode 32. In this embodiment, N is equal to 1.

Referring to the embodiment shown in fig. 5, the first extension pad P1 is provided with 2 bottom electrodes 32, the second extension pad P2 and the fifth extension pad P5 are provided with 1 bottom electrode 32, and the fourth extension pad P4 and the third extension pad P3 are not provided with any bottom electrode 32. In this embodiment, N is equal to 1.

Referring to the embodiment shown in fig. 6, 1 bottom electrode 32 is disposed on the first extension pad P1, no bottom electrode 32 is disposed on the second extension pad P2 and the fifth extension pad P5, and no bottom electrode 32 is disposed on the fourth extension pad P4 and the third extension pad P3. In this embodiment, N is equal to 0.

Referring to the embodiment shown in fig. 7, 3 bottom electrodes 32 are respectively disposed on the first extension pad P1, 2 bottom electrodes 32 are respectively disposed on the second extension pad P2 and the fifth extension pad P5, 1 bottom electrode 32 is disposed on the fourth extension pad P4 at intervals, and no bottom electrode 32 is disposed on the third extension pad P3. In this embodiment, N is equal to 2.

Referring to the embodiment shown in fig. 8, 3 bottom electrodes 32 are respectively disposed on the first extension pad P1, 2 bottom electrodes 32 are respectively disposed on the second extension pad P2 and the fifth extension pad P5, and no bottom electrode 32 is disposed on the fourth extension pad P4 and the third extension pad P3. In this embodiment, N is equal to 2.

In summary, the peripheral region of the capacitor structure of the semiconductor memory of the present utility model can be supported more, and the defects of deformation or collapse are reduced, so that the capacitor structure with better integrity is obtained, the quality of the semiconductor memory is improved, and the stability of the overall semiconductor memory is improved.

The above description is only of the preferred embodiments of the present utility model and is not intended to limit the present utility model, but various modifications and variations can be made to the present utility model by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present utility model should be included in the protection scope of the present utility model.

Claims

1. A semiconductor memory device, comprising:

a substrate;

a connection layer disposed on the substrate, comprising:

a connection pad array including a plurality of connection pads arranged along a first direction and a second direction;

a peripheral structure including a first edge and a second edge adjacent to adjacent sides of the array of connection pads; and

a plurality of first extension pads arranged between the first edge and the connection pad array; and

the capacitor structure comprises a plurality of bottom electrodes arranged on the connecting layer, wherein 1 bottom electrode is respectively arranged on the connecting pad, and 2 bottom electrodes are respectively arranged on the first extending pad.

2. The semiconductor memory according to claim 1, wherein the first edge and the second edge extend in different directions and are connected by a third edge, the semiconductor memory further comprising:

a third extension pad disposed between the third edge and the connection pad array; and

and a plurality of fourth extension pads arranged between the second edge and the connection pad array, wherein a length of the first extension pad is greater than a length of the third extension pad along the first direction, and the length of the third extension pad is greater than the length of the fourth extension pad.

3. The semiconductor memory according to claim 2, wherein 1 of the bottom electrodes is provided at intervals on the fourth extension pad.

4. The semiconductor memory according to claim 2, further comprising:

and a fifth extension pad disposed between the first extension pad and the third extension pad and connected to the third edge, wherein a length of the fifth extension pad is greater than a length of the third extension pad and less than a length of the first extension pad along the first direction.

5. The semiconductor memory according to claim 4, wherein 1 bottom electrode is provided on the fifth extension pad.

6. The semiconductor memory according to claim 1, further comprising:

and a plurality of second extension pads and the first extension pads are alternately arranged between the first edge and the connection pad array, wherein 1 bottom electrode is respectively arranged on the second extension pads.

7. The semiconductor memory according to claim 6, wherein a length of the first extension pad is greater than a length of the second extension pad along the first direction.

8. The semiconductor memory of claim 6, wherein the second extension pad is connected to the first edge, the first extension pad being completely separated from the first edge by a dielectric layer.

9. The semiconductor memory according to claim 6, wherein the first edge and the second edge extend in different directions and are connected by a third edge, the semiconductor memory further comprising:

and a plurality of fourth extension pads arranged between the second edge and the connection pad array, wherein a length of the second extension pad is greater than a length of the third extension pad along the first direction, and the length of the third extension pad is greater than the length of the fourth extension pad.

10. The semiconductor memory according to claim 9, further comprising:

and a fifth extension pad disposed between the first extension pad and the third extension pad and connected to the third edge, wherein a length of the fifth extension pad is greater than a length of the third extension pad and less than a length of the second extension pad along the first direction.

11. The semiconductor memory according to claim 1, wherein the first edge has a straight line profile and the second edge has a wavy profile.

12. A semiconductor memory device, comprising:

a substrate;

a connection layer disposed on the substrate, comprising:

a plurality of first extension pads and a plurality of second extension pads alternately arranged between the first edge and the connection pad array, wherein a length of the first extension pads is greater than a length of the second extension pads along the first direction; and

the capacitor structure comprises a plurality of bottom electrodes arranged on the connecting layer, wherein 1 bottom electrode is respectively arranged on the connecting pad, n+1 bottom electrodes are respectively arranged on the first extending pad, and N bottom electrodes are respectively arranged on the second extending pad.

13. The semiconductor memory according to claim 12, wherein N is equal to 0, 1, or 2.

14. The semiconductor memory of claim 12, wherein the second extension pads are respectively connected to the first edges, the first extension pads being completely separated from the first edges by a dielectric layer.

15. The semiconductor memory according to claim 12, wherein the first edge has a straight line profile and the second edge has a wavy profile.

16. The semiconductor memory according to claim 12, wherein the first edge and the second edge extend in different directions and are connected by a third edge, the semiconductor memory further comprising:

17. The semiconductor memory according to claim 16, wherein a length of the second extension pad is longer than a length of the third extension pad.

18. The semiconductor memory according to claim 16, wherein 1 bottom electrode is provided at an interval on the fourth extension pad.

19. The semiconductor memory according to claim 16, further comprising:

and a fifth extension pad disposed between the first extension pad and the third extension pad and connected to the third edge, wherein the second extension pad has a length greater than a length of the fifth extension pad along the first direction, and the fifth extension pad has a length greater than a length of the third extension pad.

20. The semiconductor memory according to claim 19, wherein N of the bottom electrodes are provided on the fifth extension pad.